1 //===- R600MCCodeEmitter.cpp - Code Emitter for R600->Cayman GPU families -===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 /// \file 11 /// 12 /// \brief The R600 code emitter produces machine code that can be executed 13 /// directly on the GPU device. 14 // 15 //===----------------------------------------------------------------------===// 16 17 #include "R600Defines.h" 18 #include "MCTargetDesc/AMDGPUMCCodeEmitter.h" 19 #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 20 #include "llvm/MC/MCCodeEmitter.h" 21 #include "llvm/MC/MCContext.h" 22 #include "llvm/MC/MCInst.h" 23 #include "llvm/MC/MCInstrInfo.h" 24 #include "llvm/MC/MCRegisterInfo.h" 25 #include "llvm/MC/MCSubtargetInfo.h" 26 #include "llvm/Support/EndianStream.h" 27 #include "llvm/Support/raw_ostream.h" 28 29 using namespace llvm; 30 31 namespace { 32 33 class R600MCCodeEmitter : public AMDGPUMCCodeEmitter { 34 R600MCCodeEmitter(const R600MCCodeEmitter &) = delete; 35 void operator=(const R600MCCodeEmitter &) = delete; 36 const MCInstrInfo &MCII; 37 const MCRegisterInfo &MRI; 38 39 public: 40 41 R600MCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &mri) 42 : MCII(mcii), MRI(mri) { } 43 44 /// \brief Encode the instruction and write it to the OS. 45 void encodeInstruction(const MCInst &MI, raw_ostream &OS, 46 SmallVectorImpl<MCFixup> &Fixups, 47 const MCSubtargetInfo &STI) const override; 48 49 /// \returns the encoding for an MCOperand. 50 uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, 51 SmallVectorImpl<MCFixup> &Fixups, 52 const MCSubtargetInfo &STI) const override; 53 private: 54 55 void EmitByte(unsigned int byte, raw_ostream &OS) const; 56 57 void Emit(uint32_t value, raw_ostream &OS) const; 58 void Emit(uint64_t value, raw_ostream &OS) const; 59 60 unsigned getHWRegChan(unsigned reg) const; 61 unsigned getHWReg(unsigned regNo) const; 62 63 }; 64 65 } // End anonymous namespace 66 67 enum RegElement { 68 ELEMENT_X = 0, 69 ELEMENT_Y, 70 ELEMENT_Z, 71 ELEMENT_W 72 }; 73 74 enum FCInstr { 75 FC_IF_PREDICATE = 0, 76 FC_ELSE, 77 FC_ENDIF, 78 FC_BGNLOOP, 79 FC_ENDLOOP, 80 FC_BREAK_PREDICATE, 81 FC_CONTINUE 82 }; 83 84 MCCodeEmitter *llvm::createR600MCCodeEmitter(const MCInstrInfo &MCII, 85 const MCRegisterInfo &MRI, 86 MCContext &Ctx) { 87 return new R600MCCodeEmitter(MCII, MRI); 88 } 89 90 void R600MCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS, 91 SmallVectorImpl<MCFixup> &Fixups, 92 const MCSubtargetInfo &STI) const { 93 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); 94 if (MI.getOpcode() == AMDGPU::RETURN || 95 MI.getOpcode() == AMDGPU::FETCH_CLAUSE || 96 MI.getOpcode() == AMDGPU::ALU_CLAUSE || 97 MI.getOpcode() == AMDGPU::BUNDLE || 98 MI.getOpcode() == AMDGPU::KILL) { 99 return; 100 } else if (IS_VTX(Desc)) { 101 uint64_t InstWord01 = getBinaryCodeForInstr(MI, Fixups, STI); 102 uint32_t InstWord2 = MI.getOperand(2).getImm(); // Offset 103 if (!(STI.getFeatureBits()[AMDGPU::FeatureCaymanISA])) { 104 InstWord2 |= 1 << 19; // Mega-Fetch bit 105 } 106 107 Emit(InstWord01, OS); 108 Emit(InstWord2, OS); 109 Emit((uint32_t) 0, OS); 110 } else if (IS_TEX(Desc)) { 111 int64_t Sampler = MI.getOperand(14).getImm(); 112 113 int64_t SrcSelect[4] = { 114 MI.getOperand(2).getImm(), 115 MI.getOperand(3).getImm(), 116 MI.getOperand(4).getImm(), 117 MI.getOperand(5).getImm() 118 }; 119 int64_t Offsets[3] = { 120 MI.getOperand(6).getImm() & 0x1F, 121 MI.getOperand(7).getImm() & 0x1F, 122 MI.getOperand(8).getImm() & 0x1F 123 }; 124 125 uint64_t Word01 = getBinaryCodeForInstr(MI, Fixups, STI); 126 uint32_t Word2 = Sampler << 15 | SrcSelect[ELEMENT_X] << 20 | 127 SrcSelect[ELEMENT_Y] << 23 | SrcSelect[ELEMENT_Z] << 26 | 128 SrcSelect[ELEMENT_W] << 29 | Offsets[0] << 0 | Offsets[1] << 5 | 129 Offsets[2] << 10; 130 131 Emit(Word01, OS); 132 Emit(Word2, OS); 133 Emit((uint32_t) 0, OS); 134 } else { 135 uint64_t Inst = getBinaryCodeForInstr(MI, Fixups, STI); 136 if ((STI.getFeatureBits()[AMDGPU::FeatureR600ALUInst]) && 137 ((Desc.TSFlags & R600_InstFlag::OP1) || 138 Desc.TSFlags & R600_InstFlag::OP2)) { 139 uint64_t ISAOpCode = Inst & (0x3FFULL << 39); 140 Inst &= ~(0x3FFULL << 39); 141 Inst |= ISAOpCode << 1; 142 } 143 Emit(Inst, OS); 144 } 145 } 146 147 void R600MCCodeEmitter::EmitByte(unsigned int Byte, raw_ostream &OS) const { 148 OS.write((uint8_t) Byte & 0xff); 149 } 150 151 void R600MCCodeEmitter::Emit(uint32_t Value, raw_ostream &OS) const { 152 support::endian::Writer<support::little>(OS).write(Value); 153 } 154 155 void R600MCCodeEmitter::Emit(uint64_t Value, raw_ostream &OS) const { 156 support::endian::Writer<support::little>(OS).write(Value); 157 } 158 159 unsigned R600MCCodeEmitter::getHWRegChan(unsigned reg) const { 160 return MRI.getEncodingValue(reg) >> HW_CHAN_SHIFT; 161 } 162 163 unsigned R600MCCodeEmitter::getHWReg(unsigned RegNo) const { 164 return MRI.getEncodingValue(RegNo) & HW_REG_MASK; 165 } 166 167 uint64_t R600MCCodeEmitter::getMachineOpValue(const MCInst &MI, 168 const MCOperand &MO, 169 SmallVectorImpl<MCFixup> &Fixup, 170 const MCSubtargetInfo &STI) const { 171 if (MO.isReg()) { 172 if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags)) 173 return MRI.getEncodingValue(MO.getReg()); 174 return getHWReg(MO.getReg()); 175 } 176 177 assert(MO.isImm()); 178 return MO.getImm(); 179 } 180 181 #include "AMDGPUGenMCCodeEmitter.inc" 182