1 //===- R600MCCodeEmitter.cpp - Code Emitter for R600->Cayman GPU families -===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 /// \file 10 /// 11 /// The R600 code emitter produces machine code that can be executed 12 /// directly on the GPU device. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #include "MCTargetDesc/R600MCTargetDesc.h" 17 #include "R600Defines.h" 18 #include "llvm/MC/MCCodeEmitter.h" 19 #include "llvm/MC/MCContext.h" 20 #include "llvm/MC/MCInst.h" 21 #include "llvm/MC/MCInstrInfo.h" 22 #include "llvm/MC/MCRegisterInfo.h" 23 #include "llvm/MC/MCSubtargetInfo.h" 24 #include "llvm/MC/SubtargetFeature.h" 25 #include "llvm/Support/EndianStream.h" 26 27 using namespace llvm; 28 29 namespace { 30 31 class R600MCCodeEmitter : public MCCodeEmitter { 32 const MCRegisterInfo &MRI; 33 const MCInstrInfo &MCII; 34 35 public: 36 R600MCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &mri) 37 : MRI(mri), MCII(mcii) {} 38 R600MCCodeEmitter(const R600MCCodeEmitter &) = delete; 39 R600MCCodeEmitter &operator=(const R600MCCodeEmitter &) = delete; 40 41 /// Encode the instruction and write it to the OS. 42 void encodeInstruction(const MCInst &MI, raw_ostream &OS, 43 SmallVectorImpl<MCFixup> &Fixups, 44 const MCSubtargetInfo &STI) const override; 45 46 /// \returns the encoding for an MCOperand. 47 uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, 48 SmallVectorImpl<MCFixup> &Fixups, 49 const MCSubtargetInfo &STI) const; 50 51 private: 52 53 void Emit(uint32_t value, raw_ostream &OS) const; 54 void Emit(uint64_t value, raw_ostream &OS) const; 55 56 unsigned getHWReg(unsigned regNo) const; 57 58 uint64_t getBinaryCodeForInstr(const MCInst &MI, 59 SmallVectorImpl<MCFixup> &Fixups, 60 const MCSubtargetInfo &STI) const; 61 FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) const; 62 void 63 verifyInstructionPredicates(const MCInst &MI, 64 const FeatureBitset &AvailableFeatures) const; 65 66 }; 67 68 } // end anonymous namespace 69 70 enum RegElement { 71 ELEMENT_X = 0, 72 ELEMENT_Y, 73 ELEMENT_Z, 74 ELEMENT_W 75 }; 76 77 enum FCInstr { 78 FC_IF_PREDICATE = 0, 79 FC_ELSE, 80 FC_ENDIF, 81 FC_BGNLOOP, 82 FC_ENDLOOP, 83 FC_BREAK_PREDICATE, 84 FC_CONTINUE 85 }; 86 87 MCCodeEmitter *llvm::createR600MCCodeEmitter(const MCInstrInfo &MCII, 88 const MCRegisterInfo &MRI, 89 MCContext &Ctx) { 90 return new R600MCCodeEmitter(MCII, MRI); 91 } 92 93 void R600MCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS, 94 SmallVectorImpl<MCFixup> &Fixups, 95 const MCSubtargetInfo &STI) const { 96 verifyInstructionPredicates(MI, 97 computeAvailableFeatures(STI.getFeatureBits())); 98 99 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); 100 if (MI.getOpcode() == R600::RETURN || 101 MI.getOpcode() == R600::FETCH_CLAUSE || 102 MI.getOpcode() == R600::ALU_CLAUSE || 103 MI.getOpcode() == R600::BUNDLE || 104 MI.getOpcode() == R600::KILL) { 105 return; 106 } else if (IS_VTX(Desc)) { 107 uint64_t InstWord01 = getBinaryCodeForInstr(MI, Fixups, STI); 108 uint32_t InstWord2 = MI.getOperand(2).getImm(); // Offset 109 if (!(STI.getFeatureBits()[R600::FeatureCaymanISA])) { 110 InstWord2 |= 1 << 19; // Mega-Fetch bit 111 } 112 113 Emit(InstWord01, OS); 114 Emit(InstWord2, OS); 115 Emit((uint32_t) 0, OS); 116 } else if (IS_TEX(Desc)) { 117 int64_t Sampler = MI.getOperand(14).getImm(); 118 119 int64_t SrcSelect[4] = { 120 MI.getOperand(2).getImm(), 121 MI.getOperand(3).getImm(), 122 MI.getOperand(4).getImm(), 123 MI.getOperand(5).getImm() 124 }; 125 int64_t Offsets[3] = { 126 MI.getOperand(6).getImm() & 0x1F, 127 MI.getOperand(7).getImm() & 0x1F, 128 MI.getOperand(8).getImm() & 0x1F 129 }; 130 131 uint64_t Word01 = getBinaryCodeForInstr(MI, Fixups, STI); 132 uint32_t Word2 = Sampler << 15 | SrcSelect[ELEMENT_X] << 20 | 133 SrcSelect[ELEMENT_Y] << 23 | SrcSelect[ELEMENT_Z] << 26 | 134 SrcSelect[ELEMENT_W] << 29 | Offsets[0] << 0 | Offsets[1] << 5 | 135 Offsets[2] << 10; 136 137 Emit(Word01, OS); 138 Emit(Word2, OS); 139 Emit((uint32_t) 0, OS); 140 } else { 141 uint64_t Inst = getBinaryCodeForInstr(MI, Fixups, STI); 142 if ((STI.getFeatureBits()[R600::FeatureR600ALUInst]) && 143 ((Desc.TSFlags & R600_InstFlag::OP1) || 144 Desc.TSFlags & R600_InstFlag::OP2)) { 145 uint64_t ISAOpCode = Inst & (0x3FFULL << 39); 146 Inst &= ~(0x3FFULL << 39); 147 Inst |= ISAOpCode << 1; 148 } 149 Emit(Inst, OS); 150 } 151 } 152 153 void R600MCCodeEmitter::Emit(uint32_t Value, raw_ostream &OS) const { 154 support::endian::write(OS, Value, support::little); 155 } 156 157 void R600MCCodeEmitter::Emit(uint64_t Value, raw_ostream &OS) const { 158 support::endian::write(OS, Value, support::little); 159 } 160 161 unsigned R600MCCodeEmitter::getHWReg(unsigned RegNo) const { 162 return MRI.getEncodingValue(RegNo) & HW_REG_MASK; 163 } 164 165 uint64_t R600MCCodeEmitter::getMachineOpValue(const MCInst &MI, 166 const MCOperand &MO, 167 SmallVectorImpl<MCFixup> &Fixups, 168 const MCSubtargetInfo &STI) const { 169 if (MO.isReg()) { 170 if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags)) 171 return MRI.getEncodingValue(MO.getReg()); 172 return getHWReg(MO.getReg()); 173 } 174 175 if (MO.isExpr()) { 176 // We put rodata at the end of code section, then map the entire 177 // code secetion as vtx buf. Thus the section relative address is the 178 // correct one. 179 // Each R600 literal instruction has two operands 180 // We can't easily get the order of the current one, so compare against 181 // the first one and adjust offset. 182 const unsigned offset = (&MO == &MI.getOperand(0)) ? 0 : 4; 183 Fixups.push_back(MCFixup::create(offset, MO.getExpr(), FK_SecRel_4, MI.getLoc())); 184 return 0; 185 } 186 187 assert(MO.isImm()); 188 return MO.getImm(); 189 } 190 191 #define ENABLE_INSTR_PREDICATE_VERIFIER 192 #include "R600GenMCCodeEmitter.inc" 193