1 //===- R600MCCodeEmitter.cpp - Code Emitter for R600->Cayman GPU families -===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 /// \file 11 /// 12 /// \brief The R600 code emitter produces machine code that can be executed 13 /// directly on the GPU device. 14 // 15 //===----------------------------------------------------------------------===// 16 17 #include "R600Defines.h" 18 #include "MCTargetDesc/AMDGPUFixupKinds.h" 19 #include "MCTargetDesc/AMDGPUMCCodeEmitter.h" 20 #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 21 #include "llvm/MC/MCCodeEmitter.h" 22 #include "llvm/MC/MCContext.h" 23 #include "llvm/MC/MCInst.h" 24 #include "llvm/MC/MCInstrInfo.h" 25 #include "llvm/MC/MCRegisterInfo.h" 26 #include "llvm/MC/MCSubtargetInfo.h" 27 #include "llvm/Support/EndianStream.h" 28 #include "llvm/Support/raw_ostream.h" 29 30 using namespace llvm; 31 32 namespace { 33 34 class R600MCCodeEmitter : public AMDGPUMCCodeEmitter { 35 R600MCCodeEmitter(const R600MCCodeEmitter &) = delete; 36 void operator=(const R600MCCodeEmitter &) = delete; 37 const MCRegisterInfo &MRI; 38 39 public: 40 R600MCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &mri) 41 : AMDGPUMCCodeEmitter(mcii), MRI(mri) { } 42 43 /// \brief Encode the instruction and write it to the OS. 44 void encodeInstruction(const MCInst &MI, raw_ostream &OS, 45 SmallVectorImpl<MCFixup> &Fixups, 46 const MCSubtargetInfo &STI) const override; 47 48 /// \returns the encoding for an MCOperand. 49 uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, 50 SmallVectorImpl<MCFixup> &Fixups, 51 const MCSubtargetInfo &STI) const override; 52 53 private: 54 void Emit(uint32_t value, raw_ostream &OS) const; 55 void Emit(uint64_t value, raw_ostream &OS) const; 56 57 unsigned getHWReg(unsigned regNo) const; 58 }; 59 60 } // End anonymous namespace 61 62 enum RegElement { 63 ELEMENT_X = 0, 64 ELEMENT_Y, 65 ELEMENT_Z, 66 ELEMENT_W 67 }; 68 69 enum FCInstr { 70 FC_IF_PREDICATE = 0, 71 FC_ELSE, 72 FC_ENDIF, 73 FC_BGNLOOP, 74 FC_ENDLOOP, 75 FC_BREAK_PREDICATE, 76 FC_CONTINUE 77 }; 78 79 MCCodeEmitter *llvm::createR600MCCodeEmitter(const MCInstrInfo &MCII, 80 const MCRegisterInfo &MRI, 81 MCContext &Ctx) { 82 return new R600MCCodeEmitter(MCII, MRI); 83 } 84 85 void R600MCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS, 86 SmallVectorImpl<MCFixup> &Fixups, 87 const MCSubtargetInfo &STI) const { 88 verifyInstructionPredicates(MI, 89 computeAvailableFeatures(STI.getFeatureBits())); 90 91 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); 92 if (MI.getOpcode() == AMDGPU::RETURN || 93 MI.getOpcode() == AMDGPU::FETCH_CLAUSE || 94 MI.getOpcode() == AMDGPU::ALU_CLAUSE || 95 MI.getOpcode() == AMDGPU::BUNDLE || 96 MI.getOpcode() == AMDGPU::KILL) { 97 return; 98 } else if (IS_VTX(Desc)) { 99 uint64_t InstWord01 = getBinaryCodeForInstr(MI, Fixups, STI); 100 uint32_t InstWord2 = MI.getOperand(2).getImm(); // Offset 101 if (!(STI.getFeatureBits()[AMDGPU::FeatureCaymanISA])) { 102 InstWord2 |= 1 << 19; // Mega-Fetch bit 103 } 104 105 Emit(InstWord01, OS); 106 Emit(InstWord2, OS); 107 Emit((uint32_t) 0, OS); 108 } else if (IS_TEX(Desc)) { 109 int64_t Sampler = MI.getOperand(14).getImm(); 110 111 int64_t SrcSelect[4] = { 112 MI.getOperand(2).getImm(), 113 MI.getOperand(3).getImm(), 114 MI.getOperand(4).getImm(), 115 MI.getOperand(5).getImm() 116 }; 117 int64_t Offsets[3] = { 118 MI.getOperand(6).getImm() & 0x1F, 119 MI.getOperand(7).getImm() & 0x1F, 120 MI.getOperand(8).getImm() & 0x1F 121 }; 122 123 uint64_t Word01 = getBinaryCodeForInstr(MI, Fixups, STI); 124 uint32_t Word2 = Sampler << 15 | SrcSelect[ELEMENT_X] << 20 | 125 SrcSelect[ELEMENT_Y] << 23 | SrcSelect[ELEMENT_Z] << 26 | 126 SrcSelect[ELEMENT_W] << 29 | Offsets[0] << 0 | Offsets[1] << 5 | 127 Offsets[2] << 10; 128 129 Emit(Word01, OS); 130 Emit(Word2, OS); 131 Emit((uint32_t) 0, OS); 132 } else { 133 uint64_t Inst = getBinaryCodeForInstr(MI, Fixups, STI); 134 if ((STI.getFeatureBits()[AMDGPU::FeatureR600ALUInst]) && 135 ((Desc.TSFlags & R600_InstFlag::OP1) || 136 Desc.TSFlags & R600_InstFlag::OP2)) { 137 uint64_t ISAOpCode = Inst & (0x3FFULL << 39); 138 Inst &= ~(0x3FFULL << 39); 139 Inst |= ISAOpCode << 1; 140 } 141 Emit(Inst, OS); 142 } 143 } 144 145 void R600MCCodeEmitter::Emit(uint32_t Value, raw_ostream &OS) const { 146 support::endian::Writer<support::little>(OS).write(Value); 147 } 148 149 void R600MCCodeEmitter::Emit(uint64_t Value, raw_ostream &OS) const { 150 support::endian::Writer<support::little>(OS).write(Value); 151 } 152 153 unsigned R600MCCodeEmitter::getHWReg(unsigned RegNo) const { 154 return MRI.getEncodingValue(RegNo) & HW_REG_MASK; 155 } 156 157 uint64_t R600MCCodeEmitter::getMachineOpValue(const MCInst &MI, 158 const MCOperand &MO, 159 SmallVectorImpl<MCFixup> &Fixups, 160 const MCSubtargetInfo &STI) const { 161 if (MO.isReg()) { 162 if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags)) 163 return MRI.getEncodingValue(MO.getReg()); 164 return getHWReg(MO.getReg()); 165 } 166 167 if (MO.isExpr()) { 168 // We put rodata at the end of code section, then map the entire 169 // code secetion as vtx buf. Thus the section relative address is the 170 // correct one. 171 // Each R600 literal instruction has two operands 172 // We can't easily get the order of the current one, so compare against 173 // the first one and adjust offset. 174 const unsigned offset = (&MO == &MI.getOperand(0)) ? 0 : 4; 175 Fixups.push_back(MCFixup::create(offset, MO.getExpr(), FK_SecRel_4, MI.getLoc())); 176 return 0; 177 } 178 179 assert(MO.isImm()); 180 return MO.getImm(); 181 } 182 183 #define ENABLE_INSTR_PREDICATE_VERIFIER 184 #include "AMDGPUGenMCCodeEmitter.inc" 185