1 //===-- AMDGPUMCTargetDesc.h - AMDGPU Target Descriptions -----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 /// \file 11 /// \brief Provides AMDGPU specific target descriptions. 12 // 13 //===----------------------------------------------------------------------===// 14 // 15 16 #ifndef LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUMCTARGETDESC_H 17 #define LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUMCTARGETDESC_H 18 19 #include "llvm/Support/DataTypes.h" 20 21 namespace llvm { 22 class MCAsmBackend; 23 class MCCodeEmitter; 24 class MCContext; 25 class MCInstrInfo; 26 class MCObjectWriter; 27 class MCRegisterInfo; 28 class MCSubtargetInfo; 29 class MCTargetOptions; 30 class StringRef; 31 class Target; 32 class Triple; 33 class raw_pwrite_stream; 34 35 Target &getTheAMDGPUTarget(); 36 Target &getTheGCNTarget(); 37 38 MCCodeEmitter *createR600MCCodeEmitter(const MCInstrInfo &MCII, 39 const MCRegisterInfo &MRI, 40 MCContext &Ctx); 41 42 MCCodeEmitter *createSIMCCodeEmitter(const MCInstrInfo &MCII, 43 const MCRegisterInfo &MRI, 44 MCContext &Ctx); 45 46 MCAsmBackend *createAMDGPUAsmBackend(const Target &T, const MCRegisterInfo &MRI, 47 const Triple &TT, StringRef CPU, 48 const MCTargetOptions &Options); 49 50 MCObjectWriter *createAMDGPUELFObjectWriter(bool Is64Bit, 51 bool HasRelocationAddend, 52 raw_pwrite_stream &OS); 53 } // End llvm namespace 54 55 #define GET_REGINFO_ENUM 56 #include "AMDGPUGenRegisterInfo.inc" 57 58 #define GET_INSTRINFO_ENUM 59 #include "AMDGPUGenInstrInfo.inc" 60 61 #define GET_SUBTARGETINFO_ENUM 62 #include "AMDGPUGenSubtargetInfo.inc" 63 64 #endif 65