1 //===-- AMDGPUMCTargetDesc.cpp - AMDGPU Target Descriptions ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 /// \file 10 /// This file provides AMDGPU specific target descriptions. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "AMDGPUMCTargetDesc.h" 15 #include "AMDGPUELFStreamer.h" 16 #include "AMDGPUInstPrinter.h" 17 #include "AMDGPUMCAsmInfo.h" 18 #include "AMDGPUTargetStreamer.h" 19 #include "R600InstPrinter.h" 20 #include "R600MCTargetDesc.h" 21 #include "TargetInfo/AMDGPUTargetInfo.h" 22 #include "llvm/MC/LaneBitmask.h" 23 #include "llvm/MC/MCAsmBackend.h" 24 #include "llvm/MC/MCCodeEmitter.h" 25 #include "llvm/MC/MCELFStreamer.h" 26 #include "llvm/MC/MCInstPrinter.h" 27 #include "llvm/MC/MCInstrAnalysis.h" 28 #include "llvm/MC/MCInstrDesc.h" 29 #include "llvm/MC/MCInstrInfo.h" 30 #include "llvm/MC/MCObjectWriter.h" 31 #include "llvm/MC/MCRegisterInfo.h" 32 #include "llvm/MC/MCStreamer.h" 33 #include "llvm/MC/MCSubtargetInfo.h" 34 #include "llvm/MC/TargetRegistry.h" 35 36 using namespace llvm; 37 38 #define GET_INSTRINFO_MC_DESC 39 #include "AMDGPUGenInstrInfo.inc" 40 41 #define GET_SUBTARGETINFO_MC_DESC 42 #include "AMDGPUGenSubtargetInfo.inc" 43 44 #define NoSchedModel NoSchedModelR600 45 #define GET_SUBTARGETINFO_MC_DESC 46 #include "R600GenSubtargetInfo.inc" 47 #undef NoSchedModelR600 48 49 #define GET_REGINFO_MC_DESC 50 #include "AMDGPUGenRegisterInfo.inc" 51 52 #define GET_REGINFO_MC_DESC 53 #include "R600GenRegisterInfo.inc" 54 55 static MCInstrInfo *createAMDGPUMCInstrInfo() { 56 MCInstrInfo *X = new MCInstrInfo(); 57 InitAMDGPUMCInstrInfo(X); 58 return X; 59 } 60 61 static MCRegisterInfo *createAMDGPUMCRegisterInfo(const Triple &TT) { 62 MCRegisterInfo *X = new MCRegisterInfo(); 63 if (TT.getArch() == Triple::r600) 64 InitR600MCRegisterInfo(X, 0); 65 else 66 InitAMDGPUMCRegisterInfo(X, AMDGPU::PC_REG); 67 return X; 68 } 69 70 MCRegisterInfo *llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour DwarfFlavour) { 71 MCRegisterInfo *X = new MCRegisterInfo(); 72 InitAMDGPUMCRegisterInfo(X, AMDGPU::PC_REG, DwarfFlavour); 73 return X; 74 } 75 76 static MCSubtargetInfo * 77 createAMDGPUMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { 78 if (TT.getArch() == Triple::r600) 79 return createR600MCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS); 80 return createAMDGPUMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS); 81 } 82 83 static MCInstPrinter *createAMDGPUMCInstPrinter(const Triple &T, 84 unsigned SyntaxVariant, 85 const MCAsmInfo &MAI, 86 const MCInstrInfo &MII, 87 const MCRegisterInfo &MRI) { 88 if (T.getArch() == Triple::r600) 89 return new R600InstPrinter(MAI, MII, MRI); 90 else 91 return new AMDGPUInstPrinter(MAI, MII, MRI); 92 } 93 94 static MCTargetStreamer *createAMDGPUAsmTargetStreamer(MCStreamer &S, 95 formatted_raw_ostream &OS, 96 MCInstPrinter *InstPrint, 97 bool isVerboseAsm) { 98 return new AMDGPUTargetAsmStreamer(S, OS); 99 } 100 101 static MCTargetStreamer * createAMDGPUObjectTargetStreamer( 102 MCStreamer &S, 103 const MCSubtargetInfo &STI) { 104 return new AMDGPUTargetELFStreamer(S, STI); 105 } 106 107 static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context, 108 std::unique_ptr<MCAsmBackend> &&MAB, 109 std::unique_ptr<MCObjectWriter> &&OW, 110 std::unique_ptr<MCCodeEmitter> &&Emitter, 111 bool RelaxAll) { 112 return createAMDGPUELFStreamer(T, Context, std::move(MAB), std::move(OW), 113 std::move(Emitter), RelaxAll); 114 } 115 116 namespace { 117 118 class AMDGPUMCInstrAnalysis : public MCInstrAnalysis { 119 public: 120 explicit AMDGPUMCInstrAnalysis(const MCInstrInfo *Info) 121 : MCInstrAnalysis(Info) {} 122 123 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size, 124 uint64_t &Target) const override { 125 if (Inst.getNumOperands() == 0 || !Inst.getOperand(0).isImm() || 126 Info->get(Inst.getOpcode()).OpInfo[0].OperandType != 127 MCOI::OPERAND_PCREL) 128 return false; 129 130 int64_t Imm = Inst.getOperand(0).getImm(); 131 // Our branches take a simm16, but we need two extra bits to account for 132 // the factor of 4. 133 APInt SignedOffset(18, Imm * 4, true); 134 Target = (SignedOffset.sext(64) + Addr + Size).getZExtValue(); 135 return true; 136 } 137 }; 138 139 } // end anonymous namespace 140 141 static MCInstrAnalysis *createAMDGPUMCInstrAnalysis(const MCInstrInfo *Info) { 142 return new AMDGPUMCInstrAnalysis(Info); 143 } 144 145 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTargetMC() { 146 147 TargetRegistry::RegisterMCInstrInfo(getTheGCNTarget(), createAMDGPUMCInstrInfo); 148 TargetRegistry::RegisterMCInstrInfo(getTheAMDGPUTarget(), createR600MCInstrInfo); 149 for (Target *T : {&getTheAMDGPUTarget(), &getTheGCNTarget()}) { 150 RegisterMCAsmInfo<AMDGPUMCAsmInfo> X(*T); 151 152 TargetRegistry::RegisterMCRegInfo(*T, createAMDGPUMCRegisterInfo); 153 TargetRegistry::RegisterMCSubtargetInfo(*T, createAMDGPUMCSubtargetInfo); 154 TargetRegistry::RegisterMCInstPrinter(*T, createAMDGPUMCInstPrinter); 155 TargetRegistry::RegisterMCInstrAnalysis(*T, createAMDGPUMCInstrAnalysis); 156 TargetRegistry::RegisterMCAsmBackend(*T, createAMDGPUAsmBackend); 157 TargetRegistry::RegisterELFStreamer(*T, createMCStreamer); 158 } 159 160 // R600 specific registration 161 TargetRegistry::RegisterMCCodeEmitter(getTheAMDGPUTarget(), 162 createR600MCCodeEmitter); 163 TargetRegistry::RegisterObjectTargetStreamer( 164 getTheAMDGPUTarget(), createAMDGPUObjectTargetStreamer); 165 166 // GCN specific registration 167 TargetRegistry::RegisterMCCodeEmitter(getTheGCNTarget(), 168 createSIMCCodeEmitter); 169 170 TargetRegistry::RegisterAsmTargetStreamer(getTheGCNTarget(), 171 createAMDGPUAsmTargetStreamer); 172 TargetRegistry::RegisterObjectTargetStreamer( 173 getTheGCNTarget(), createAMDGPUObjectTargetStreamer); 174 } 175