1 //===-- AMDGPUMCTargetDesc.cpp - AMDGPU Target Descriptions ---------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// This file provides AMDGPU specific target descriptions.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPUMCTargetDesc.h"
16 #include "AMDGPUELFStreamer.h"
17 #include "AMDGPUMCAsmInfo.h"
18 #include "AMDGPUTargetStreamer.h"
19 #include "InstPrinter/AMDGPUInstPrinter.h"
20 #include "SIDefines.h"
21 #include "llvm/MC/MCAsmBackend.h"
22 #include "llvm/MC/MCCodeEmitter.h"
23 #include "llvm/MC/MCContext.h"
24 #include "llvm/MC/MCInstrInfo.h"
25 #include "llvm/MC/MCObjectWriter.h"
26 #include "llvm/MC/MCRegisterInfo.h"
27 #include "llvm/MC/MCStreamer.h"
28 #include "llvm/MC/MCSubtargetInfo.h"
29 #include "llvm/MC/MachineLocation.h"
30 #include "llvm/Support/ErrorHandling.h"
31 #include "llvm/Support/TargetRegistry.h"
32 
33 using namespace llvm;
34 
35 #define GET_INSTRINFO_MC_DESC
36 #include "AMDGPUGenInstrInfo.inc"
37 
38 #define GET_SUBTARGETINFO_MC_DESC
39 #include "AMDGPUGenSubtargetInfo.inc"
40 
41 #define GET_REGINFO_MC_DESC
42 #include "AMDGPUGenRegisterInfo.inc"
43 
44 static MCInstrInfo *createAMDGPUMCInstrInfo() {
45   MCInstrInfo *X = new MCInstrInfo();
46   InitAMDGPUMCInstrInfo(X);
47   return X;
48 }
49 
50 static MCRegisterInfo *createAMDGPUMCRegisterInfo(const Triple &TT) {
51   MCRegisterInfo *X = new MCRegisterInfo();
52   InitAMDGPUMCRegisterInfo(X, 0);
53   return X;
54 }
55 
56 static MCSubtargetInfo *
57 createAMDGPUMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
58   return createAMDGPUMCSubtargetInfoImpl(TT, CPU, FS);
59 }
60 
61 static MCInstPrinter *createAMDGPUMCInstPrinter(const Triple &T,
62                                                 unsigned SyntaxVariant,
63                                                 const MCAsmInfo &MAI,
64                                                 const MCInstrInfo &MII,
65                                                 const MCRegisterInfo &MRI) {
66   return T.getArch() == Triple::r600 ? new R600InstPrinter(MAI, MII, MRI) :
67                                        new AMDGPUInstPrinter(MAI, MII, MRI);
68 }
69 
70 static MCTargetStreamer *createAMDGPUAsmTargetStreamer(MCStreamer &S,
71                                                       formatted_raw_ostream &OS,
72                                                       MCInstPrinter *InstPrint,
73                                                       bool isVerboseAsm) {
74   return new AMDGPUTargetAsmStreamer(S, OS);
75 }
76 
77 static MCTargetStreamer * createAMDGPUObjectTargetStreamer(
78                                                    MCStreamer &S,
79                                                    const MCSubtargetInfo &STI) {
80   return new AMDGPUTargetELFStreamer(S, STI);
81 }
82 
83 static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context,
84                                     std::unique_ptr<MCAsmBackend> &&MAB,
85                                     std::unique_ptr<MCObjectWriter> &&OW,
86                                     std::unique_ptr<MCCodeEmitter> &&Emitter,
87                                     bool RelaxAll) {
88   return createAMDGPUELFStreamer(T, Context, std::move(MAB), std::move(OW),
89                                  std::move(Emitter), RelaxAll);
90 }
91 
92 extern "C" void LLVMInitializeAMDGPUTargetMC() {
93   for (Target *T : {&getTheAMDGPUTarget(), &getTheGCNTarget()}) {
94     RegisterMCAsmInfo<AMDGPUMCAsmInfo> X(*T);
95 
96     TargetRegistry::RegisterMCInstrInfo(*T, createAMDGPUMCInstrInfo);
97     TargetRegistry::RegisterMCRegInfo(*T, createAMDGPUMCRegisterInfo);
98     TargetRegistry::RegisterMCSubtargetInfo(*T, createAMDGPUMCSubtargetInfo);
99     TargetRegistry::RegisterMCInstPrinter(*T, createAMDGPUMCInstPrinter);
100     TargetRegistry::RegisterMCAsmBackend(*T, createAMDGPUAsmBackend);
101     TargetRegistry::RegisterELFStreamer(*T, createMCStreamer);
102   }
103 
104   // R600 specific registration
105   TargetRegistry::RegisterMCCodeEmitter(getTheAMDGPUTarget(),
106                                         createR600MCCodeEmitter);
107   TargetRegistry::RegisterObjectTargetStreamer(
108       getTheAMDGPUTarget(), createAMDGPUObjectTargetStreamer);
109 
110   // GCN specific registration
111   TargetRegistry::RegisterMCCodeEmitter(getTheGCNTarget(),
112                                         createSIMCCodeEmitter);
113 
114   TargetRegistry::RegisterAsmTargetStreamer(getTheGCNTarget(),
115                                             createAMDGPUAsmTargetStreamer);
116   TargetRegistry::RegisterObjectTargetStreamer(
117       getTheGCNTarget(), createAMDGPUObjectTargetStreamer);
118 }
119