1 //===-- AMDGPUMCTargetDesc.cpp - AMDGPU Target Descriptions ---------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief This file provides AMDGPU specific target descriptions.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPUMCTargetDesc.h"
16 #include "AMDGPUMCAsmInfo.h"
17 #include "AMDGPUTargetStreamer.h"
18 #include "InstPrinter/AMDGPUInstPrinter.h"
19 #include "SIDefines.h"
20 #include "llvm/MC/MCCodeGenInfo.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/MC/MCStreamer.h"
25 #include "llvm/MC/MCSubtargetInfo.h"
26 #include "llvm/MC/MachineLocation.h"
27 #include "llvm/Support/ErrorHandling.h"
28 #include "llvm/Support/TargetRegistry.h"
29 
30 using namespace llvm;
31 
32 #define GET_INSTRINFO_MC_DESC
33 #include "AMDGPUGenInstrInfo.inc"
34 
35 #define GET_SUBTARGETINFO_MC_DESC
36 #include "AMDGPUGenSubtargetInfo.inc"
37 
38 #define GET_REGINFO_MC_DESC
39 #include "AMDGPUGenRegisterInfo.inc"
40 
41 static MCInstrInfo *createAMDGPUMCInstrInfo() {
42   MCInstrInfo *X = new MCInstrInfo();
43   InitAMDGPUMCInstrInfo(X);
44   return X;
45 }
46 
47 static MCRegisterInfo *createAMDGPUMCRegisterInfo(const Triple &TT) {
48   MCRegisterInfo *X = new MCRegisterInfo();
49   InitAMDGPUMCRegisterInfo(X, 0);
50   return X;
51 }
52 
53 static MCSubtargetInfo *
54 createAMDGPUMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
55   return createAMDGPUMCSubtargetInfoImpl(TT, CPU, FS);
56 }
57 
58 static MCCodeGenInfo *createAMDGPUMCCodeGenInfo(const Triple &TT,
59                                                 Reloc::Model RM,
60                                                 CodeModel::Model CM,
61                                                 CodeGenOpt::Level OL) {
62   MCCodeGenInfo *X = new MCCodeGenInfo();
63   X->initMCCodeGenInfo(RM, CM, OL);
64   return X;
65 }
66 
67 static MCInstPrinter *createAMDGPUMCInstPrinter(const Triple &T,
68                                                 unsigned SyntaxVariant,
69                                                 const MCAsmInfo &MAI,
70                                                 const MCInstrInfo &MII,
71                                                 const MCRegisterInfo &MRI) {
72   return new AMDGPUInstPrinter(MAI, MII, MRI);
73 }
74 
75 static MCTargetStreamer *createAMDGPUAsmTargetStreamer(MCStreamer &S,
76                                                       formatted_raw_ostream &OS,
77                                                       MCInstPrinter *InstPrint,
78                                                       bool isVerboseAsm) {
79   return new AMDGPUTargetAsmStreamer(S, OS);
80 }
81 
82 static MCTargetStreamer * createAMDGPUObjectTargetStreamer(
83                                                    MCStreamer &S,
84                                                    const MCSubtargetInfo &STI) {
85   return new AMDGPUTargetELFStreamer(S);
86 }
87 
88 extern "C" void LLVMInitializeAMDGPUTargetMC() {
89   for (Target *T : {&TheAMDGPUTarget, &TheGCNTarget}) {
90     RegisterMCAsmInfo<AMDGPUMCAsmInfo> X(*T);
91 
92     TargetRegistry::RegisterMCCodeGenInfo(*T, createAMDGPUMCCodeGenInfo);
93     TargetRegistry::RegisterMCInstrInfo(*T, createAMDGPUMCInstrInfo);
94     TargetRegistry::RegisterMCRegInfo(*T, createAMDGPUMCRegisterInfo);
95     TargetRegistry::RegisterMCSubtargetInfo(*T, createAMDGPUMCSubtargetInfo);
96     TargetRegistry::RegisterMCInstPrinter(*T, createAMDGPUMCInstPrinter);
97     TargetRegistry::RegisterMCAsmBackend(*T, createAMDGPUAsmBackend);
98   }
99 
100   // R600 specific registration
101   TargetRegistry::RegisterMCCodeEmitter(TheAMDGPUTarget,
102                                         createR600MCCodeEmitter);
103 
104   // GCN specific registration
105   TargetRegistry::RegisterMCCodeEmitter(TheGCNTarget, createSIMCCodeEmitter);
106 
107   TargetRegistry::RegisterAsmTargetStreamer(TheGCNTarget,
108                                             createAMDGPUAsmTargetStreamer);
109   TargetRegistry::RegisterObjectTargetStreamer(TheGCNTarget,
110                                               createAMDGPUObjectTargetStreamer);
111 }
112