1 //===-- AMDGPUMCTargetDesc.cpp - AMDGPU Target Descriptions ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// This file provides AMDGPU specific target descriptions.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "AMDGPUMCTargetDesc.h"
15 #include "AMDGPUELFStreamer.h"
16 #include "AMDGPUMCAsmInfo.h"
17 #include "AMDGPUTargetStreamer.h"
18 #include "InstPrinter/AMDGPUInstPrinter.h"
19 #include "SIDefines.h"
20 #include "llvm/MC/MCAsmBackend.h"
21 #include "llvm/MC/MCCodeEmitter.h"
22 #include "llvm/MC/MCContext.h"
23 #include "llvm/MC/MCInstrInfo.h"
24 #include "llvm/MC/MCObjectWriter.h"
25 #include "llvm/MC/MCRegisterInfo.h"
26 #include "llvm/MC/MCStreamer.h"
27 #include "llvm/MC/MCSubtargetInfo.h"
28 #include "llvm/MC/MachineLocation.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/TargetRegistry.h"
31 
32 using namespace llvm;
33 
34 #define GET_INSTRINFO_MC_DESC
35 #include "AMDGPUGenInstrInfo.inc"
36 
37 #define GET_SUBTARGETINFO_MC_DESC
38 #include "AMDGPUGenSubtargetInfo.inc"
39 
40 #define NoSchedModel NoSchedModelR600
41 #define GET_SUBTARGETINFO_MC_DESC
42 #include "R600GenSubtargetInfo.inc"
43 #undef NoSchedModelR600
44 
45 #define GET_REGINFO_MC_DESC
46 #include "AMDGPUGenRegisterInfo.inc"
47 
48 #define GET_REGINFO_MC_DESC
49 #include "R600GenRegisterInfo.inc"
50 
51 static MCInstrInfo *createAMDGPUMCInstrInfo() {
52   MCInstrInfo *X = new MCInstrInfo();
53   InitAMDGPUMCInstrInfo(X);
54   return X;
55 }
56 
57 static MCRegisterInfo *createAMDGPUMCRegisterInfo(const Triple &TT) {
58   MCRegisterInfo *X = new MCRegisterInfo();
59   if (TT.getArch() == Triple::r600)
60     InitR600MCRegisterInfo(X, 0);
61   else
62     InitAMDGPUMCRegisterInfo(X, 0);
63   return X;
64 }
65 
66 static MCSubtargetInfo *
67 createAMDGPUMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
68   if (TT.getArch() == Triple::r600)
69     return createR600MCSubtargetInfoImpl(TT, CPU, FS);
70   return createAMDGPUMCSubtargetInfoImpl(TT, CPU, FS);
71 }
72 
73 static MCInstPrinter *createAMDGPUMCInstPrinter(const Triple &T,
74                                                 unsigned SyntaxVariant,
75                                                 const MCAsmInfo &MAI,
76                                                 const MCInstrInfo &MII,
77                                                 const MCRegisterInfo &MRI) {
78   if (T.getArch() == Triple::r600)
79     return new R600InstPrinter(MAI, MII, MRI);
80   else
81     return new AMDGPUInstPrinter(MAI, MII, MRI);
82 }
83 
84 static MCTargetStreamer *createAMDGPUAsmTargetStreamer(MCStreamer &S,
85                                                       formatted_raw_ostream &OS,
86                                                       MCInstPrinter *InstPrint,
87                                                       bool isVerboseAsm) {
88   return new AMDGPUTargetAsmStreamer(S, OS);
89 }
90 
91 static MCTargetStreamer * createAMDGPUObjectTargetStreamer(
92                                                    MCStreamer &S,
93                                                    const MCSubtargetInfo &STI) {
94   return new AMDGPUTargetELFStreamer(S, STI);
95 }
96 
97 static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context,
98                                     std::unique_ptr<MCAsmBackend> &&MAB,
99                                     std::unique_ptr<MCObjectWriter> &&OW,
100                                     std::unique_ptr<MCCodeEmitter> &&Emitter,
101                                     bool RelaxAll) {
102   return createAMDGPUELFStreamer(T, Context, std::move(MAB), std::move(OW),
103                                  std::move(Emitter), RelaxAll);
104 }
105 
106 extern "C" void LLVMInitializeAMDGPUTargetMC() {
107 
108   TargetRegistry::RegisterMCInstrInfo(getTheGCNTarget(), createAMDGPUMCInstrInfo);
109   TargetRegistry::RegisterMCInstrInfo(getTheAMDGPUTarget(), createR600MCInstrInfo);
110   for (Target *T : {&getTheAMDGPUTarget(), &getTheGCNTarget()}) {
111     RegisterMCAsmInfo<AMDGPUMCAsmInfo> X(*T);
112 
113     TargetRegistry::RegisterMCRegInfo(*T, createAMDGPUMCRegisterInfo);
114     TargetRegistry::RegisterMCSubtargetInfo(*T, createAMDGPUMCSubtargetInfo);
115     TargetRegistry::RegisterMCInstPrinter(*T, createAMDGPUMCInstPrinter);
116     TargetRegistry::RegisterMCAsmBackend(*T, createAMDGPUAsmBackend);
117     TargetRegistry::RegisterELFStreamer(*T, createMCStreamer);
118   }
119 
120   // R600 specific registration
121   TargetRegistry::RegisterMCCodeEmitter(getTheAMDGPUTarget(),
122                                         createR600MCCodeEmitter);
123   TargetRegistry::RegisterObjectTargetStreamer(
124       getTheAMDGPUTarget(), createAMDGPUObjectTargetStreamer);
125 
126   // GCN specific registration
127   TargetRegistry::RegisterMCCodeEmitter(getTheGCNTarget(),
128                                         createSIMCCodeEmitter);
129 
130   TargetRegistry::RegisterAsmTargetStreamer(getTheGCNTarget(),
131                                             createAMDGPUAsmTargetStreamer);
132   TargetRegistry::RegisterObjectTargetStreamer(
133       getTheGCNTarget(), createAMDGPUObjectTargetStreamer);
134 }
135