1 //===-- AMDGPUInstPrinter.cpp - AMDGPU MC Inst -> ASM ---------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 // \file
8 //===----------------------------------------------------------------------===//
9 
10 #include "AMDGPUInstPrinter.h"
11 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
12 #include "SIDefines.h"
13 #include "Utils/AMDGPUAsmUtils.h"
14 #include "Utils/AMDGPUBaseInfo.h"
15 #include "llvm/MC/MCExpr.h"
16 #include "llvm/MC/MCInst.h"
17 #include "llvm/MC/MCInstrDesc.h"
18 #include "llvm/MC/MCInstrInfo.h"
19 #include "llvm/MC/MCSubtargetInfo.h"
20 #include "llvm/Support/CommandLine.h"
21 #include "llvm/Support/TargetParser.h"
22 
23 using namespace llvm;
24 using namespace llvm::AMDGPU;
25 
26 static cl::opt<bool> Keep16BitSuffixes(
27   "amdgpu-keep-16-bit-reg-suffixes",
28   cl::desc("Keep .l and .h suffixes in asm for debugging purposes"),
29   cl::init(false),
30   cl::ReallyHidden);
31 
32 void AMDGPUInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
33   // FIXME: The current implementation of
34   // AsmParser::parseRegisterOrRegisterNumber in MC implies we either emit this
35   // as an integer or we provide a name which represents a physical register.
36   // For CFI instructions we really want to emit a name for the DWARF register
37   // instead, because there may be multiple DWARF registers corresponding to a
38   // single physical register. One case where this problem manifests is with
39   // wave32/wave64 where using the physical register name is ambiguous: if we
40   // write e.g. `.cfi_undefined v0` we lose information about the wavefront
41   // size which we need to encode the register in the final DWARF. Ideally we
42   // would extend MC to support parsing DWARF register names so we could do
43   // something like `.cfi_undefined dwarf_wave32_v0`. For now we just live with
44   // non-pretty DWARF register names in assembly text.
45   OS << RegNo;
46 }
47 
48 void AMDGPUInstPrinter::printInst(const MCInst *MI, uint64_t Address,
49                                   StringRef Annot, const MCSubtargetInfo &STI,
50                                   raw_ostream &OS) {
51   OS.flush();
52   printInstruction(MI, Address, STI, OS);
53   printAnnotation(OS, Annot);
54 }
55 
56 void AMDGPUInstPrinter::printU4ImmOperand(const MCInst *MI, unsigned OpNo,
57                                           const MCSubtargetInfo &STI,
58                                           raw_ostream &O) {
59   O << formatHex(MI->getOperand(OpNo).getImm() & 0xf);
60 }
61 
62 void AMDGPUInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo,
63                                           raw_ostream &O) {
64   O << formatHex(MI->getOperand(OpNo).getImm() & 0xff);
65 }
66 
67 void AMDGPUInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
68                                            const MCSubtargetInfo &STI,
69                                            raw_ostream &O) {
70   // It's possible to end up with a 32-bit literal used with a 16-bit operand
71   // with ignored high bits. Print as 32-bit anyway in that case.
72   int64_t Imm = MI->getOperand(OpNo).getImm();
73   if (isInt<16>(Imm) || isUInt<16>(Imm))
74     O << formatHex(static_cast<uint64_t>(Imm & 0xffff));
75   else
76     printU32ImmOperand(MI, OpNo, STI, O);
77 }
78 
79 void AMDGPUInstPrinter::printU4ImmDecOperand(const MCInst *MI, unsigned OpNo,
80                                              raw_ostream &O) {
81   O << formatDec(MI->getOperand(OpNo).getImm() & 0xf);
82 }
83 
84 void AMDGPUInstPrinter::printU8ImmDecOperand(const MCInst *MI, unsigned OpNo,
85                                              raw_ostream &O) {
86   O << formatDec(MI->getOperand(OpNo).getImm() & 0xff);
87 }
88 
89 void AMDGPUInstPrinter::printU16ImmDecOperand(const MCInst *MI, unsigned OpNo,
90                                               raw_ostream &O) {
91   O << formatDec(MI->getOperand(OpNo).getImm() & 0xffff);
92 }
93 
94 void AMDGPUInstPrinter::printU32ImmOperand(const MCInst *MI, unsigned OpNo,
95                                            const MCSubtargetInfo &STI,
96                                            raw_ostream &O) {
97   O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff);
98 }
99 
100 void AMDGPUInstPrinter::printNamedBit(const MCInst *MI, unsigned OpNo,
101                                       raw_ostream &O, StringRef BitName) {
102   if (MI->getOperand(OpNo).getImm()) {
103     O << ' ' << BitName;
104   }
105 }
106 
107 void AMDGPUInstPrinter::printOffen(const MCInst *MI, unsigned OpNo,
108                                    raw_ostream &O) {
109   printNamedBit(MI, OpNo, O, "offen");
110 }
111 
112 void AMDGPUInstPrinter::printIdxen(const MCInst *MI, unsigned OpNo,
113                                    raw_ostream &O) {
114   printNamedBit(MI, OpNo, O, "idxen");
115 }
116 
117 void AMDGPUInstPrinter::printAddr64(const MCInst *MI, unsigned OpNo,
118                                     raw_ostream &O) {
119   printNamedBit(MI, OpNo, O, "addr64");
120 }
121 
122 void AMDGPUInstPrinter::printMBUFOffset(const MCInst *MI, unsigned OpNo,
123                                         raw_ostream &O) {
124   if (MI->getOperand(OpNo).getImm()) {
125     O << " offset:";
126     printU16ImmDecOperand(MI, OpNo, O);
127   }
128 }
129 
130 void AMDGPUInstPrinter::printOffset(const MCInst *MI, unsigned OpNo,
131                                     const MCSubtargetInfo &STI,
132                                     raw_ostream &O) {
133   uint16_t Imm = MI->getOperand(OpNo).getImm();
134   if (Imm != 0) {
135     O << " offset:";
136     printU16ImmDecOperand(MI, OpNo, O);
137   }
138 }
139 
140 void AMDGPUInstPrinter::printFlatOffset(const MCInst *MI, unsigned OpNo,
141                                         const MCSubtargetInfo &STI,
142                                         raw_ostream &O) {
143   uint16_t Imm = MI->getOperand(OpNo).getImm();
144   if (Imm != 0) {
145     O << " offset:";
146 
147     const MCInstrDesc &Desc = MII.get(MI->getOpcode());
148     bool IsFlatSeg = !(Desc.TSFlags &
149         (SIInstrFlags::IsFlatGlobal | SIInstrFlags::IsFlatScratch));
150 
151     if (IsFlatSeg) { // Unsigned offset
152       printU16ImmDecOperand(MI, OpNo, O);
153     } else {         // Signed offset
154       if (AMDGPU::isGFX10Plus(STI)) {
155         O << formatDec(SignExtend32<12>(MI->getOperand(OpNo).getImm()));
156       } else {
157         O << formatDec(SignExtend32<13>(MI->getOperand(OpNo).getImm()));
158       }
159     }
160   }
161 }
162 
163 void AMDGPUInstPrinter::printOffset0(const MCInst *MI, unsigned OpNo,
164                                      const MCSubtargetInfo &STI,
165                                      raw_ostream &O) {
166   if (MI->getOperand(OpNo).getImm()) {
167     O << " offset0:";
168     printU8ImmDecOperand(MI, OpNo, O);
169   }
170 }
171 
172 void AMDGPUInstPrinter::printOffset1(const MCInst *MI, unsigned OpNo,
173                                      const MCSubtargetInfo &STI,
174                                      raw_ostream &O) {
175   if (MI->getOperand(OpNo).getImm()) {
176     O << " offset1:";
177     printU8ImmDecOperand(MI, OpNo, O);
178   }
179 }
180 
181 void AMDGPUInstPrinter::printSMRDOffset8(const MCInst *MI, unsigned OpNo,
182                                         const MCSubtargetInfo &STI,
183                                         raw_ostream &O) {
184   printU32ImmOperand(MI, OpNo, STI, O);
185 }
186 
187 void AMDGPUInstPrinter::printSMEMOffset(const MCInst *MI, unsigned OpNo,
188                                         const MCSubtargetInfo &STI,
189                                         raw_ostream &O) {
190   O << formatHex(MI->getOperand(OpNo).getImm());
191 }
192 
193 void AMDGPUInstPrinter::printSMRDLiteralOffset(const MCInst *MI, unsigned OpNo,
194                                                const MCSubtargetInfo &STI,
195                                                raw_ostream &O) {
196   printU32ImmOperand(MI, OpNo, STI, O);
197 }
198 
199 void AMDGPUInstPrinter::printGDS(const MCInst *MI, unsigned OpNo,
200                                  const MCSubtargetInfo &STI, raw_ostream &O) {
201   printNamedBit(MI, OpNo, O, "gds");
202 }
203 
204 void AMDGPUInstPrinter::printDLC(const MCInst *MI, unsigned OpNo,
205                                  const MCSubtargetInfo &STI, raw_ostream &O) {
206   if (AMDGPU::isGFX10Plus(STI))
207     printNamedBit(MI, OpNo, O, "dlc");
208 }
209 
210 void AMDGPUInstPrinter::printGLC(const MCInst *MI, unsigned OpNo,
211                                  const MCSubtargetInfo &STI, raw_ostream &O) {
212   printNamedBit(MI, OpNo, O, "glc");
213 }
214 
215 void AMDGPUInstPrinter::printSLC(const MCInst *MI, unsigned OpNo,
216                                  const MCSubtargetInfo &STI, raw_ostream &O) {
217   printNamedBit(MI, OpNo, O, "slc");
218 }
219 
220 void AMDGPUInstPrinter::printSWZ(const MCInst *MI, unsigned OpNo,
221                                  const MCSubtargetInfo &STI, raw_ostream &O) {
222 }
223 
224 void AMDGPUInstPrinter::printTFE(const MCInst *MI, unsigned OpNo,
225                                  const MCSubtargetInfo &STI, raw_ostream &O) {
226   printNamedBit(MI, OpNo, O, "tfe");
227 }
228 
229 void AMDGPUInstPrinter::printDMask(const MCInst *MI, unsigned OpNo,
230                                    const MCSubtargetInfo &STI, raw_ostream &O) {
231   if (MI->getOperand(OpNo).getImm()) {
232     O << " dmask:";
233     printU16ImmOperand(MI, OpNo, STI, O);
234   }
235 }
236 
237 void AMDGPUInstPrinter::printDim(const MCInst *MI, unsigned OpNo,
238                                  const MCSubtargetInfo &STI, raw_ostream &O) {
239   unsigned Dim = MI->getOperand(OpNo).getImm();
240   O << " dim:SQ_RSRC_IMG_";
241 
242   const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfoByEncoding(Dim);
243   if (DimInfo)
244     O << DimInfo->AsmSuffix;
245   else
246     O << Dim;
247 }
248 
249 void AMDGPUInstPrinter::printUNorm(const MCInst *MI, unsigned OpNo,
250                                    const MCSubtargetInfo &STI, raw_ostream &O) {
251   printNamedBit(MI, OpNo, O, "unorm");
252 }
253 
254 void AMDGPUInstPrinter::printDA(const MCInst *MI, unsigned OpNo,
255                                 const MCSubtargetInfo &STI, raw_ostream &O) {
256   printNamedBit(MI, OpNo, O, "da");
257 }
258 
259 void AMDGPUInstPrinter::printR128A16(const MCInst *MI, unsigned OpNo,
260                                   const MCSubtargetInfo &STI, raw_ostream &O) {
261   if (STI.hasFeature(AMDGPU::FeatureR128A16))
262     printNamedBit(MI, OpNo, O, "a16");
263   else
264     printNamedBit(MI, OpNo, O, "r128");
265 }
266 
267 void AMDGPUInstPrinter::printGFX10A16(const MCInst *MI, unsigned OpNo,
268                                   const MCSubtargetInfo &STI, raw_ostream &O) {
269   printNamedBit(MI, OpNo, O, "a16");
270 }
271 
272 void AMDGPUInstPrinter::printLWE(const MCInst *MI, unsigned OpNo,
273                                  const MCSubtargetInfo &STI, raw_ostream &O) {
274   printNamedBit(MI, OpNo, O, "lwe");
275 }
276 
277 void AMDGPUInstPrinter::printD16(const MCInst *MI, unsigned OpNo,
278                                  const MCSubtargetInfo &STI, raw_ostream &O) {
279   printNamedBit(MI, OpNo, O, "d16");
280 }
281 
282 void AMDGPUInstPrinter::printExpCompr(const MCInst *MI, unsigned OpNo,
283                                       const MCSubtargetInfo &STI,
284                                       raw_ostream &O) {
285   printNamedBit(MI, OpNo, O, "compr");
286 }
287 
288 void AMDGPUInstPrinter::printExpVM(const MCInst *MI, unsigned OpNo,
289                                    const MCSubtargetInfo &STI,
290                                    raw_ostream &O) {
291   printNamedBit(MI, OpNo, O, "vm");
292 }
293 
294 void AMDGPUInstPrinter::printFORMAT(const MCInst *MI, unsigned OpNo,
295                                     const MCSubtargetInfo &STI,
296                                     raw_ostream &O) {
297 }
298 
299 void AMDGPUInstPrinter::printSymbolicFormat(const MCInst *MI,
300                                             const MCSubtargetInfo &STI,
301                                             raw_ostream &O) {
302   using namespace llvm::AMDGPU::MTBUFFormat;
303 
304   int OpNo =
305     AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::format);
306   assert(OpNo != -1);
307 
308   unsigned Val = MI->getOperand(OpNo).getImm();
309   if (AMDGPU::isGFX10Plus(STI)) {
310     if (Val == UFMT_DEFAULT)
311       return;
312     if (isValidUnifiedFormat(Val)) {
313       O << " format:[" << getUnifiedFormatName(Val) << ']';
314     } else {
315       O << " format:" << Val;
316     }
317   } else {
318     if (Val == DFMT_NFMT_DEFAULT)
319       return;
320     if (isValidDfmtNfmt(Val, STI)) {
321       unsigned Dfmt;
322       unsigned Nfmt;
323       decodeDfmtNfmt(Val, Dfmt, Nfmt);
324       O << " format:[";
325       if (Dfmt != DFMT_DEFAULT) {
326         O << getDfmtName(Dfmt);
327         if (Nfmt != NFMT_DEFAULT) {
328           O << ',';
329         }
330       }
331       if (Nfmt != NFMT_DEFAULT) {
332         O << getNfmtName(Nfmt, STI);
333       }
334       O << ']';
335     } else {
336       O << " format:" << Val;
337     }
338   }
339 }
340 
341 void AMDGPUInstPrinter::printRegOperand(unsigned RegNo, raw_ostream &O,
342                                         const MCRegisterInfo &MRI) {
343 #if !defined(NDEBUG)
344   switch (RegNo) {
345   case AMDGPU::FP_REG:
346   case AMDGPU::SP_REG:
347   case AMDGPU::PRIVATE_RSRC_REG:
348     llvm_unreachable("pseudo-register should not ever be emitted");
349   case AMDGPU::SCC:
350     llvm_unreachable("pseudo scc should not ever be emitted");
351   default:
352     break;
353   }
354 #endif
355 
356   StringRef RegName(getRegisterName(RegNo));
357   if (!Keep16BitSuffixes)
358     if (!RegName.consume_back(".l"))
359       RegName.consume_back(".h");
360 
361   O << RegName;
362 }
363 
364 void AMDGPUInstPrinter::printVOPDst(const MCInst *MI, unsigned OpNo,
365                                     const MCSubtargetInfo &STI, raw_ostream &O) {
366   if (OpNo == 0) {
367     if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::VOP3)
368       O << "_e64 ";
369     else if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::DPP)
370       O << "_dpp ";
371     else if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::SDWA)
372       O << "_sdwa ";
373     else
374       O << "_e32 ";
375   }
376 
377   printOperand(MI, OpNo, STI, O);
378 
379   // Print default vcc/vcc_lo operand.
380   switch (MI->getOpcode()) {
381   default: break;
382 
383   case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10:
384   case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10:
385   case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10:
386   case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10:
387   case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10:
388   case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10:
389   case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10:
390   case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10:
391   case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10:
392   case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10:
393   case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10:
394   case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10:
395     printDefaultVccOperand(1, STI, O);
396     break;
397   }
398 }
399 
400 void AMDGPUInstPrinter::printVINTRPDst(const MCInst *MI, unsigned OpNo,
401                                        const MCSubtargetInfo &STI, raw_ostream &O) {
402   if (AMDGPU::isSI(STI) || AMDGPU::isCI(STI))
403     O << " ";
404   else
405     O << "_e32 ";
406 
407   printOperand(MI, OpNo, STI, O);
408 }
409 
410 void AMDGPUInstPrinter::printImmediateInt16(uint32_t Imm,
411                                             const MCSubtargetInfo &STI,
412                                             raw_ostream &O) {
413   int16_t SImm = static_cast<int16_t>(Imm);
414   if (isInlinableIntLiteral(SImm)) {
415     O << SImm;
416   } else {
417     uint64_t Imm16 = static_cast<uint16_t>(Imm);
418     O << formatHex(Imm16);
419   }
420 }
421 
422 void AMDGPUInstPrinter::printImmediate16(uint32_t Imm,
423                                          const MCSubtargetInfo &STI,
424                                          raw_ostream &O) {
425   int16_t SImm = static_cast<int16_t>(Imm);
426   if (isInlinableIntLiteral(SImm)) {
427     O << SImm;
428     return;
429   }
430 
431   if (Imm == 0x3C00)
432     O<< "1.0";
433   else if (Imm == 0xBC00)
434     O<< "-1.0";
435   else if (Imm == 0x3800)
436     O<< "0.5";
437   else if (Imm == 0xB800)
438     O<< "-0.5";
439   else if (Imm == 0x4000)
440     O<< "2.0";
441   else if (Imm == 0xC000)
442     O<< "-2.0";
443   else if (Imm == 0x4400)
444     O<< "4.0";
445   else if (Imm == 0xC400)
446     O<< "-4.0";
447   else if (Imm == 0x3118 &&
448            STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]) {
449     O << "0.15915494";
450   } else {
451     uint64_t Imm16 = static_cast<uint16_t>(Imm);
452     O << formatHex(Imm16);
453   }
454 }
455 
456 void AMDGPUInstPrinter::printImmediateV216(uint32_t Imm,
457                                            const MCSubtargetInfo &STI,
458                                            raw_ostream &O) {
459   uint16_t Lo16 = static_cast<uint16_t>(Imm);
460   printImmediate16(Lo16, STI, O);
461 }
462 
463 void AMDGPUInstPrinter::printImmediate32(uint32_t Imm,
464                                          const MCSubtargetInfo &STI,
465                                          raw_ostream &O) {
466   int32_t SImm = static_cast<int32_t>(Imm);
467   if (SImm >= -16 && SImm <= 64) {
468     O << SImm;
469     return;
470   }
471 
472   if (Imm == FloatToBits(0.0f))
473     O << "0.0";
474   else if (Imm == FloatToBits(1.0f))
475     O << "1.0";
476   else if (Imm == FloatToBits(-1.0f))
477     O << "-1.0";
478   else if (Imm == FloatToBits(0.5f))
479     O << "0.5";
480   else if (Imm == FloatToBits(-0.5f))
481     O << "-0.5";
482   else if (Imm == FloatToBits(2.0f))
483     O << "2.0";
484   else if (Imm == FloatToBits(-2.0f))
485     O << "-2.0";
486   else if (Imm == FloatToBits(4.0f))
487     O << "4.0";
488   else if (Imm == FloatToBits(-4.0f))
489     O << "-4.0";
490   else if (Imm == 0x3e22f983 &&
491            STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
492     O << "0.15915494";
493   else
494     O << formatHex(static_cast<uint64_t>(Imm));
495 }
496 
497 void AMDGPUInstPrinter::printImmediate64(uint64_t Imm,
498                                          const MCSubtargetInfo &STI,
499                                          raw_ostream &O) {
500   int64_t SImm = static_cast<int64_t>(Imm);
501   if (SImm >= -16 && SImm <= 64) {
502     O << SImm;
503     return;
504   }
505 
506   if (Imm == DoubleToBits(0.0))
507     O << "0.0";
508   else if (Imm == DoubleToBits(1.0))
509     O << "1.0";
510   else if (Imm == DoubleToBits(-1.0))
511     O << "-1.0";
512   else if (Imm == DoubleToBits(0.5))
513     O << "0.5";
514   else if (Imm == DoubleToBits(-0.5))
515     O << "-0.5";
516   else if (Imm == DoubleToBits(2.0))
517     O << "2.0";
518   else if (Imm == DoubleToBits(-2.0))
519     O << "-2.0";
520   else if (Imm == DoubleToBits(4.0))
521     O << "4.0";
522   else if (Imm == DoubleToBits(-4.0))
523     O << "-4.0";
524   else if (Imm == 0x3fc45f306dc9c882 &&
525            STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
526     O << "0.15915494309189532";
527   else {
528     assert(isUInt<32>(Imm) || Imm == 0x3fc45f306dc9c882);
529 
530     // In rare situations, we will have a 32-bit literal in a 64-bit
531     // operand. This is technically allowed for the encoding of s_mov_b64.
532     O << formatHex(static_cast<uint64_t>(Imm));
533   }
534 }
535 
536 void AMDGPUInstPrinter::printBLGP(const MCInst *MI, unsigned OpNo,
537                                   const MCSubtargetInfo &STI,
538                                   raw_ostream &O) {
539   unsigned Imm = MI->getOperand(OpNo).getImm();
540   if (!Imm)
541     return;
542 
543   O << " blgp:" << Imm;
544 }
545 
546 void AMDGPUInstPrinter::printCBSZ(const MCInst *MI, unsigned OpNo,
547                                   const MCSubtargetInfo &STI,
548                                   raw_ostream &O) {
549   unsigned Imm = MI->getOperand(OpNo).getImm();
550   if (!Imm)
551     return;
552 
553   O << " cbsz:" << Imm;
554 }
555 
556 void AMDGPUInstPrinter::printABID(const MCInst *MI, unsigned OpNo,
557                                   const MCSubtargetInfo &STI,
558                                   raw_ostream &O) {
559   unsigned Imm = MI->getOperand(OpNo).getImm();
560   if (!Imm)
561     return;
562 
563   O << " abid:" << Imm;
564 }
565 
566 void AMDGPUInstPrinter::printDefaultVccOperand(unsigned OpNo,
567                                                const MCSubtargetInfo &STI,
568                                                raw_ostream &O) {
569   if (OpNo > 0)
570     O << ", ";
571   printRegOperand(STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ?
572                   AMDGPU::VCC : AMDGPU::VCC_LO, O, MRI);
573   if (OpNo == 0)
574     O << ", ";
575 }
576 
577 void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
578                                      const MCSubtargetInfo &STI,
579                                      raw_ostream &O) {
580   // Print default vcc/vcc_lo operand of VOPC.
581   const MCInstrDesc &Desc = MII.get(MI->getOpcode());
582   if (OpNo == 0 && (Desc.TSFlags & SIInstrFlags::VOPC) &&
583       (Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC) ||
584        Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC_LO)))
585     printDefaultVccOperand(OpNo, STI, O);
586 
587   if (OpNo >= MI->getNumOperands()) {
588     O << "/*Missing OP" << OpNo << "*/";
589     return;
590   }
591 
592   const MCOperand &Op = MI->getOperand(OpNo);
593   if (Op.isReg()) {
594     printRegOperand(Op.getReg(), O, MRI);
595   } else if (Op.isImm()) {
596     const uint8_t OpTy = Desc.OpInfo[OpNo].OperandType;
597     switch (OpTy) {
598     case AMDGPU::OPERAND_REG_IMM_INT32:
599     case AMDGPU::OPERAND_REG_IMM_FP32:
600     case AMDGPU::OPERAND_REG_INLINE_C_INT32:
601     case AMDGPU::OPERAND_REG_INLINE_C_FP32:
602     case AMDGPU::OPERAND_REG_INLINE_AC_INT32:
603     case AMDGPU::OPERAND_REG_INLINE_AC_FP32:
604     case MCOI::OPERAND_IMMEDIATE:
605       printImmediate32(Op.getImm(), STI, O);
606       break;
607     case AMDGPU::OPERAND_REG_IMM_INT64:
608     case AMDGPU::OPERAND_REG_IMM_FP64:
609     case AMDGPU::OPERAND_REG_INLINE_C_INT64:
610     case AMDGPU::OPERAND_REG_INLINE_C_FP64:
611       printImmediate64(Op.getImm(), STI, O);
612       break;
613     case AMDGPU::OPERAND_REG_INLINE_C_INT16:
614     case AMDGPU::OPERAND_REG_INLINE_AC_INT16:
615     case AMDGPU::OPERAND_REG_IMM_INT16:
616       printImmediateInt16(Op.getImm(), STI, O);
617       break;
618     case AMDGPU::OPERAND_REG_INLINE_C_FP16:
619     case AMDGPU::OPERAND_REG_INLINE_AC_FP16:
620     case AMDGPU::OPERAND_REG_IMM_FP16:
621       printImmediate16(Op.getImm(), STI, O);
622       break;
623     case AMDGPU::OPERAND_REG_IMM_V2INT16:
624     case AMDGPU::OPERAND_REG_IMM_V2FP16:
625       if (!isUInt<16>(Op.getImm()) &&
626           STI.getFeatureBits()[AMDGPU::FeatureVOP3Literal]) {
627         printImmediate32(Op.getImm(), STI, O);
628         break;
629       }
630 
631       //  Deal with 16-bit FP inline immediates not working.
632       if (OpTy == AMDGPU::OPERAND_REG_IMM_V2FP16) {
633         printImmediate16(static_cast<uint16_t>(Op.getImm()), STI, O);
634         break;
635       }
636       LLVM_FALLTHROUGH;
637     case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
638     case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:
639       printImmediateInt16(static_cast<uint16_t>(Op.getImm()), STI, O);
640       break;
641     case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
642     case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16:
643       printImmediateV216(Op.getImm(), STI, O);
644       break;
645     case MCOI::OPERAND_UNKNOWN:
646     case MCOI::OPERAND_PCREL:
647       O << formatDec(Op.getImm());
648       break;
649     case MCOI::OPERAND_REGISTER:
650       // FIXME: This should be removed and handled somewhere else. Seems to come
651       // from a disassembler bug.
652       O << "/*invalid immediate*/";
653       break;
654     default:
655       // We hit this for the immediate instruction bits that don't yet have a
656       // custom printer.
657       llvm_unreachable("unexpected immediate operand type");
658     }
659   } else if (Op.isDFPImm()) {
660     double Value = bit_cast<double>(Op.getDFPImm());
661     // We special case 0.0 because otherwise it will be printed as an integer.
662     if (Value == 0.0)
663       O << "0.0";
664     else {
665       const MCInstrDesc &Desc = MII.get(MI->getOpcode());
666       int RCID = Desc.OpInfo[OpNo].RegClass;
667       unsigned RCBits = AMDGPU::getRegBitWidth(MRI.getRegClass(RCID));
668       if (RCBits == 32)
669         printImmediate32(FloatToBits(Value), STI, O);
670       else if (RCBits == 64)
671         printImmediate64(DoubleToBits(Value), STI, O);
672       else
673         llvm_unreachable("Invalid register class size");
674     }
675   } else if (Op.isExpr()) {
676     const MCExpr *Exp = Op.getExpr();
677     Exp->print(O, &MAI);
678   } else {
679     O << "/*INV_OP*/";
680   }
681 
682   // Print default vcc/vcc_lo operand of v_cndmask_b32_e32.
683   switch (MI->getOpcode()) {
684   default: break;
685 
686   case AMDGPU::V_CNDMASK_B32_e32_gfx10:
687   case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10:
688   case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10:
689   case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10:
690   case AMDGPU::V_CNDMASK_B32_dpp_gfx10:
691   case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10:
692   case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10:
693   case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10:
694   case AMDGPU::V_CNDMASK_B32_dpp8_gfx10:
695   case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10:
696   case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10:
697   case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10:
698 
699   case AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7:
700   case AMDGPU::V_CNDMASK_B32_e32_vi:
701     if ((int)OpNo == AMDGPU::getNamedOperandIdx(MI->getOpcode(),
702                                                 AMDGPU::OpName::src1))
703       printDefaultVccOperand(OpNo, STI, O);
704     break;
705   }
706 
707   if (Desc.TSFlags & SIInstrFlags::MTBUF) {
708     int SOffsetIdx =
709       AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::soffset);
710     assert(SOffsetIdx != -1);
711     if ((int)OpNo == SOffsetIdx)
712       printSymbolicFormat(MI, STI, O);
713   }
714 }
715 
716 void AMDGPUInstPrinter::printOperandAndFPInputMods(const MCInst *MI,
717                                                    unsigned OpNo,
718                                                    const MCSubtargetInfo &STI,
719                                                    raw_ostream &O) {
720   unsigned InputModifiers = MI->getOperand(OpNo).getImm();
721 
722   // Use 'neg(...)' instead of '-' to avoid ambiguity.
723   // This is important for integer literals because
724   // -1 is not the same value as neg(1).
725   bool NegMnemo = false;
726 
727   if (InputModifiers & SISrcMods::NEG) {
728     if (OpNo + 1 < MI->getNumOperands() &&
729         (InputModifiers & SISrcMods::ABS) == 0) {
730       const MCOperand &Op = MI->getOperand(OpNo + 1);
731       NegMnemo = Op.isImm() || Op.isDFPImm();
732     }
733     if (NegMnemo) {
734       O << "neg(";
735     } else {
736       O << '-';
737     }
738   }
739 
740   if (InputModifiers & SISrcMods::ABS)
741     O << '|';
742   printOperand(MI, OpNo + 1, STI, O);
743   if (InputModifiers & SISrcMods::ABS)
744     O << '|';
745 
746   if (NegMnemo) {
747     O << ')';
748   }
749 }
750 
751 void AMDGPUInstPrinter::printOperandAndIntInputMods(const MCInst *MI,
752                                                     unsigned OpNo,
753                                                     const MCSubtargetInfo &STI,
754                                                     raw_ostream &O) {
755   unsigned InputModifiers = MI->getOperand(OpNo).getImm();
756   if (InputModifiers & SISrcMods::SEXT)
757     O << "sext(";
758   printOperand(MI, OpNo + 1, STI, O);
759   if (InputModifiers & SISrcMods::SEXT)
760     O << ')';
761 
762   // Print default vcc/vcc_lo operand of VOP2b.
763   switch (MI->getOpcode()) {
764   default: break;
765 
766   case AMDGPU::V_CNDMASK_B32_sdwa_gfx10:
767   case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10:
768   case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10:
769   case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10:
770     if ((int)OpNo + 1 == AMDGPU::getNamedOperandIdx(MI->getOpcode(),
771                                                     AMDGPU::OpName::src1))
772       printDefaultVccOperand(OpNo, STI, O);
773     break;
774   }
775 }
776 
777 void AMDGPUInstPrinter::printDPP8(const MCInst *MI, unsigned OpNo,
778                                   const MCSubtargetInfo &STI,
779                                   raw_ostream &O) {
780   if (!AMDGPU::isGFX10Plus(STI))
781     llvm_unreachable("dpp8 is not supported on ASICs earlier than GFX10");
782 
783   unsigned Imm = MI->getOperand(OpNo).getImm();
784   O << "dpp8:[" << formatDec(Imm & 0x7);
785   for (size_t i = 1; i < 8; ++i) {
786     O << ',' << formatDec((Imm >> (3 * i)) & 0x7);
787   }
788   O << ']';
789 }
790 
791 void AMDGPUInstPrinter::printDPPCtrl(const MCInst *MI, unsigned OpNo,
792                                      const MCSubtargetInfo &STI,
793                                      raw_ostream &O) {
794   using namespace AMDGPU::DPP;
795 
796   unsigned Imm = MI->getOperand(OpNo).getImm();
797   if (Imm <= DppCtrl::QUAD_PERM_LAST) {
798     O << "quad_perm:[";
799     O << formatDec(Imm & 0x3)         << ',';
800     O << formatDec((Imm & 0xc)  >> 2) << ',';
801     O << formatDec((Imm & 0x30) >> 4) << ',';
802     O << formatDec((Imm & 0xc0) >> 6) << ']';
803   } else if ((Imm >= DppCtrl::ROW_SHL_FIRST) &&
804              (Imm <= DppCtrl::ROW_SHL_LAST)) {
805     O << "row_shl:";
806     printU4ImmDecOperand(MI, OpNo, O);
807   } else if ((Imm >= DppCtrl::ROW_SHR_FIRST) &&
808              (Imm <= DppCtrl::ROW_SHR_LAST)) {
809     O << "row_shr:";
810     printU4ImmDecOperand(MI, OpNo, O);
811   } else if ((Imm >= DppCtrl::ROW_ROR_FIRST) &&
812              (Imm <= DppCtrl::ROW_ROR_LAST)) {
813     O << "row_ror:";
814     printU4ImmDecOperand(MI, OpNo, O);
815   } else if (Imm == DppCtrl::WAVE_SHL1) {
816     if (AMDGPU::isGFX10Plus(STI)) {
817       O << "/* wave_shl is not supported starting from GFX10 */";
818       return;
819     }
820     O << "wave_shl:1";
821   } else if (Imm == DppCtrl::WAVE_ROL1) {
822     if (AMDGPU::isGFX10Plus(STI)) {
823       O << "/* wave_rol is not supported starting from GFX10 */";
824       return;
825     }
826     O << "wave_rol:1";
827   } else if (Imm == DppCtrl::WAVE_SHR1) {
828     if (AMDGPU::isGFX10Plus(STI)) {
829       O << "/* wave_shr is not supported starting from GFX10 */";
830       return;
831     }
832     O << "wave_shr:1";
833   } else if (Imm == DppCtrl::WAVE_ROR1) {
834     if (AMDGPU::isGFX10Plus(STI)) {
835       O << "/* wave_ror is not supported starting from GFX10 */";
836       return;
837     }
838     O << "wave_ror:1";
839   } else if (Imm == DppCtrl::ROW_MIRROR) {
840     O << "row_mirror";
841   } else if (Imm == DppCtrl::ROW_HALF_MIRROR) {
842     O << "row_half_mirror";
843   } else if (Imm == DppCtrl::BCAST15) {
844     if (AMDGPU::isGFX10Plus(STI)) {
845       O << "/* row_bcast is not supported starting from GFX10 */";
846       return;
847     }
848     O << "row_bcast:15";
849   } else if (Imm == DppCtrl::BCAST31) {
850     if (AMDGPU::isGFX10Plus(STI)) {
851       O << "/* row_bcast is not supported starting from GFX10 */";
852       return;
853     }
854     O << "row_bcast:31";
855   } else if ((Imm >= DppCtrl::ROW_SHARE_FIRST) &&
856              (Imm <= DppCtrl::ROW_SHARE_LAST)) {
857     if (!AMDGPU::isGFX10Plus(STI)) {
858       O << "/* row_share is not supported on ASICs earlier than GFX10 */";
859       return;
860     }
861     O << "row_share:";
862     printU4ImmDecOperand(MI, OpNo, O);
863   } else if ((Imm >= DppCtrl::ROW_XMASK_FIRST) &&
864              (Imm <= DppCtrl::ROW_XMASK_LAST)) {
865     if (!AMDGPU::isGFX10Plus(STI)) {
866       O << "/* row_xmask is not supported on ASICs earlier than GFX10 */";
867       return;
868     }
869     O << "row_xmask:";
870     printU4ImmDecOperand(MI, OpNo, O);
871   } else {
872     O << "/* Invalid dpp_ctrl value */";
873   }
874 }
875 
876 void AMDGPUInstPrinter::printRowMask(const MCInst *MI, unsigned OpNo,
877                                      const MCSubtargetInfo &STI,
878                                      raw_ostream &O) {
879   O << " row_mask:";
880   printU4ImmOperand(MI, OpNo, STI, O);
881 }
882 
883 void AMDGPUInstPrinter::printBankMask(const MCInst *MI, unsigned OpNo,
884                                       const MCSubtargetInfo &STI,
885                                       raw_ostream &O) {
886   O << " bank_mask:";
887   printU4ImmOperand(MI, OpNo, STI, O);
888 }
889 
890 void AMDGPUInstPrinter::printBoundCtrl(const MCInst *MI, unsigned OpNo,
891                                        const MCSubtargetInfo &STI,
892                                        raw_ostream &O) {
893   unsigned Imm = MI->getOperand(OpNo).getImm();
894   if (Imm) {
895     O << " bound_ctrl:0"; // XXX - this syntax is used in sp3
896   }
897 }
898 
899 void AMDGPUInstPrinter::printFI(const MCInst *MI, unsigned OpNo,
900                                 const MCSubtargetInfo &STI,
901                                 raw_ostream &O) {
902   using namespace llvm::AMDGPU::DPP;
903   unsigned Imm = MI->getOperand(OpNo).getImm();
904   if (Imm == DPP_FI_1 || Imm == DPP8_FI_1) {
905     O << " fi:1";
906   }
907 }
908 
909 void AMDGPUInstPrinter::printSDWASel(const MCInst *MI, unsigned OpNo,
910                                      raw_ostream &O) {
911   using namespace llvm::AMDGPU::SDWA;
912 
913   unsigned Imm = MI->getOperand(OpNo).getImm();
914   switch (Imm) {
915   case SdwaSel::BYTE_0: O << "BYTE_0"; break;
916   case SdwaSel::BYTE_1: O << "BYTE_1"; break;
917   case SdwaSel::BYTE_2: O << "BYTE_2"; break;
918   case SdwaSel::BYTE_3: O << "BYTE_3"; break;
919   case SdwaSel::WORD_0: O << "WORD_0"; break;
920   case SdwaSel::WORD_1: O << "WORD_1"; break;
921   case SdwaSel::DWORD: O << "DWORD"; break;
922   default: llvm_unreachable("Invalid SDWA data select operand");
923   }
924 }
925 
926 void AMDGPUInstPrinter::printSDWADstSel(const MCInst *MI, unsigned OpNo,
927                                         const MCSubtargetInfo &STI,
928                                         raw_ostream &O) {
929   O << "dst_sel:";
930   printSDWASel(MI, OpNo, O);
931 }
932 
933 void AMDGPUInstPrinter::printSDWASrc0Sel(const MCInst *MI, unsigned OpNo,
934                                          const MCSubtargetInfo &STI,
935                                          raw_ostream &O) {
936   O << "src0_sel:";
937   printSDWASel(MI, OpNo, O);
938 }
939 
940 void AMDGPUInstPrinter::printSDWASrc1Sel(const MCInst *MI, unsigned OpNo,
941                                          const MCSubtargetInfo &STI,
942                                          raw_ostream &O) {
943   O << "src1_sel:";
944   printSDWASel(MI, OpNo, O);
945 }
946 
947 void AMDGPUInstPrinter::printSDWADstUnused(const MCInst *MI, unsigned OpNo,
948                                            const MCSubtargetInfo &STI,
949                                            raw_ostream &O) {
950   using namespace llvm::AMDGPU::SDWA;
951 
952   O << "dst_unused:";
953   unsigned Imm = MI->getOperand(OpNo).getImm();
954   switch (Imm) {
955   case DstUnused::UNUSED_PAD: O << "UNUSED_PAD"; break;
956   case DstUnused::UNUSED_SEXT: O << "UNUSED_SEXT"; break;
957   case DstUnused::UNUSED_PRESERVE: O << "UNUSED_PRESERVE"; break;
958   default: llvm_unreachable("Invalid SDWA dest_unused operand");
959   }
960 }
961 
962 void AMDGPUInstPrinter::printExpSrcN(const MCInst *MI, unsigned OpNo,
963                                      const MCSubtargetInfo &STI, raw_ostream &O,
964                                      unsigned N) {
965   unsigned Opc = MI->getOpcode();
966   int EnIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::en);
967   unsigned En = MI->getOperand(EnIdx).getImm();
968 
969   int ComprIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::compr);
970 
971   // If compr is set, print as src0, src0, src1, src1
972   if (MI->getOperand(ComprIdx).getImm())
973     OpNo = OpNo - N + N / 2;
974 
975   if (En & (1 << N))
976     printRegOperand(MI->getOperand(OpNo).getReg(), O, MRI);
977   else
978     O << "off";
979 }
980 
981 void AMDGPUInstPrinter::printExpSrc0(const MCInst *MI, unsigned OpNo,
982                                      const MCSubtargetInfo &STI,
983                                      raw_ostream &O) {
984   printExpSrcN(MI, OpNo, STI, O, 0);
985 }
986 
987 void AMDGPUInstPrinter::printExpSrc1(const MCInst *MI, unsigned OpNo,
988                                      const MCSubtargetInfo &STI,
989                                      raw_ostream &O) {
990   printExpSrcN(MI, OpNo, STI, O, 1);
991 }
992 
993 void AMDGPUInstPrinter::printExpSrc2(const MCInst *MI, unsigned OpNo,
994                                      const MCSubtargetInfo &STI,
995                                      raw_ostream &O) {
996   printExpSrcN(MI, OpNo, STI, O, 2);
997 }
998 
999 void AMDGPUInstPrinter::printExpSrc3(const MCInst *MI, unsigned OpNo,
1000                                      const MCSubtargetInfo &STI,
1001                                      raw_ostream &O) {
1002   printExpSrcN(MI, OpNo, STI, O, 3);
1003 }
1004 
1005 void AMDGPUInstPrinter::printExpTgt(const MCInst *MI, unsigned OpNo,
1006                                     const MCSubtargetInfo &STI,
1007                                     raw_ostream &O) {
1008   using namespace llvm::AMDGPU::Exp;
1009 
1010   // This is really a 6 bit field.
1011   unsigned Id = MI->getOperand(OpNo).getImm() & ((1 << 6) - 1);
1012 
1013   int Index;
1014   StringRef TgtName;
1015   if (getTgtName(Id, TgtName, Index) && isSupportedTgtId(Id, STI)) {
1016     O << ' ' << TgtName;
1017     if (Index >= 0)
1018       O << Index;
1019   } else {
1020     O << " invalid_target_" << Id;
1021   }
1022 }
1023 
1024 static bool allOpsDefaultValue(const int* Ops, int NumOps, int Mod,
1025                                bool IsPacked, bool HasDstSel) {
1026   int DefaultValue = IsPacked && (Mod == SISrcMods::OP_SEL_1);
1027 
1028   for (int I = 0; I < NumOps; ++I) {
1029     if (!!(Ops[I] & Mod) != DefaultValue)
1030       return false;
1031   }
1032 
1033   if (HasDstSel && (Ops[0] & SISrcMods::DST_OP_SEL) != 0)
1034     return false;
1035 
1036   return true;
1037 }
1038 
1039 void AMDGPUInstPrinter::printPackedModifier(const MCInst *MI,
1040                                             StringRef Name,
1041                                             unsigned Mod,
1042                                             raw_ostream &O) {
1043   unsigned Opc = MI->getOpcode();
1044   int NumOps = 0;
1045   int Ops[3];
1046 
1047   for (int OpName : { AMDGPU::OpName::src0_modifiers,
1048                       AMDGPU::OpName::src1_modifiers,
1049                       AMDGPU::OpName::src2_modifiers }) {
1050     int Idx = AMDGPU::getNamedOperandIdx(Opc, OpName);
1051     if (Idx == -1)
1052       break;
1053 
1054     Ops[NumOps++] = MI->getOperand(Idx).getImm();
1055   }
1056 
1057   const bool HasDstSel =
1058     NumOps > 0 &&
1059     Mod == SISrcMods::OP_SEL_0 &&
1060     MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::VOP3_OPSEL;
1061 
1062   const bool IsPacked =
1063     MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::IsPacked;
1064 
1065   if (allOpsDefaultValue(Ops, NumOps, Mod, IsPacked, HasDstSel))
1066     return;
1067 
1068   O << Name;
1069   for (int I = 0; I < NumOps; ++I) {
1070     if (I != 0)
1071       O << ',';
1072 
1073     O << !!(Ops[I] & Mod);
1074   }
1075 
1076   if (HasDstSel) {
1077     O << ',' << !!(Ops[0] & SISrcMods::DST_OP_SEL);
1078   }
1079 
1080   O << ']';
1081 }
1082 
1083 void AMDGPUInstPrinter::printOpSel(const MCInst *MI, unsigned,
1084                                    const MCSubtargetInfo &STI,
1085                                    raw_ostream &O) {
1086   unsigned Opc = MI->getOpcode();
1087   if (Opc == AMDGPU::V_PERMLANE16_B32_gfx10 ||
1088       Opc == AMDGPU::V_PERMLANEX16_B32_gfx10) {
1089     auto FIN = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers);
1090     auto BCN = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers);
1091     unsigned FI = !!(MI->getOperand(FIN).getImm() & SISrcMods::OP_SEL_0);
1092     unsigned BC = !!(MI->getOperand(BCN).getImm() & SISrcMods::OP_SEL_0);
1093     if (FI || BC)
1094       O << " op_sel:[" << FI << ',' << BC << ']';
1095     return;
1096   }
1097 
1098   printPackedModifier(MI, " op_sel:[", SISrcMods::OP_SEL_0, O);
1099 }
1100 
1101 void AMDGPUInstPrinter::printOpSelHi(const MCInst *MI, unsigned OpNo,
1102                                      const MCSubtargetInfo &STI,
1103                                      raw_ostream &O) {
1104   printPackedModifier(MI, " op_sel_hi:[", SISrcMods::OP_SEL_1, O);
1105 }
1106 
1107 void AMDGPUInstPrinter::printNegLo(const MCInst *MI, unsigned OpNo,
1108                                    const MCSubtargetInfo &STI,
1109                                    raw_ostream &O) {
1110   printPackedModifier(MI, " neg_lo:[", SISrcMods::NEG, O);
1111 }
1112 
1113 void AMDGPUInstPrinter::printNegHi(const MCInst *MI, unsigned OpNo,
1114                                    const MCSubtargetInfo &STI,
1115                                    raw_ostream &O) {
1116   printPackedModifier(MI, " neg_hi:[", SISrcMods::NEG_HI, O);
1117 }
1118 
1119 void AMDGPUInstPrinter::printInterpSlot(const MCInst *MI, unsigned OpNum,
1120                                         const MCSubtargetInfo &STI,
1121                                         raw_ostream &O) {
1122   unsigned Imm = MI->getOperand(OpNum).getImm();
1123   switch (Imm) {
1124   case 0:
1125     O << "p10";
1126     break;
1127   case 1:
1128     O << "p20";
1129     break;
1130   case 2:
1131     O << "p0";
1132     break;
1133   default:
1134     O << "invalid_param_" << Imm;
1135   }
1136 }
1137 
1138 void AMDGPUInstPrinter::printInterpAttr(const MCInst *MI, unsigned OpNum,
1139                                         const MCSubtargetInfo &STI,
1140                                         raw_ostream &O) {
1141   unsigned Attr = MI->getOperand(OpNum).getImm();
1142   O << "attr" << Attr;
1143 }
1144 
1145 void AMDGPUInstPrinter::printInterpAttrChan(const MCInst *MI, unsigned OpNum,
1146                                         const MCSubtargetInfo &STI,
1147                                         raw_ostream &O) {
1148   unsigned Chan = MI->getOperand(OpNum).getImm();
1149   O << '.' << "xyzw"[Chan & 0x3];
1150 }
1151 
1152 void AMDGPUInstPrinter::printVGPRIndexMode(const MCInst *MI, unsigned OpNo,
1153                                            const MCSubtargetInfo &STI,
1154                                            raw_ostream &O) {
1155   using namespace llvm::AMDGPU::VGPRIndexMode;
1156   unsigned Val = MI->getOperand(OpNo).getImm();
1157 
1158   if ((Val & ~ENABLE_MASK) != 0) {
1159     O << formatHex(static_cast<uint64_t>(Val));
1160   } else {
1161     O << "gpr_idx(";
1162     bool NeedComma = false;
1163     for (unsigned ModeId = ID_MIN; ModeId <= ID_MAX; ++ModeId) {
1164       if (Val & (1 << ModeId)) {
1165         if (NeedComma)
1166           O << ',';
1167         O << IdSymbolic[ModeId];
1168         NeedComma = true;
1169       }
1170     }
1171     O << ')';
1172   }
1173 }
1174 
1175 void AMDGPUInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo,
1176                                         const MCSubtargetInfo &STI,
1177                                         raw_ostream &O) {
1178   printOperand(MI, OpNo, STI, O);
1179   O  << ", ";
1180   printOperand(MI, OpNo + 1, STI, O);
1181 }
1182 
1183 void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
1184                                    raw_ostream &O, StringRef Asm,
1185                                    StringRef Default) {
1186   const MCOperand &Op = MI->getOperand(OpNo);
1187   assert(Op.isImm());
1188   if (Op.getImm() == 1) {
1189     O << Asm;
1190   } else {
1191     O << Default;
1192   }
1193 }
1194 
1195 void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
1196                                    raw_ostream &O, char Asm) {
1197   const MCOperand &Op = MI->getOperand(OpNo);
1198   assert(Op.isImm());
1199   if (Op.getImm() == 1)
1200     O << Asm;
1201 }
1202 
1203 void AMDGPUInstPrinter::printHigh(const MCInst *MI, unsigned OpNo,
1204                                   const MCSubtargetInfo &STI,
1205                                   raw_ostream &O) {
1206   printNamedBit(MI, OpNo, O, "high");
1207 }
1208 
1209 void AMDGPUInstPrinter::printClampSI(const MCInst *MI, unsigned OpNo,
1210                                      const MCSubtargetInfo &STI,
1211                                      raw_ostream &O) {
1212   printNamedBit(MI, OpNo, O, "clamp");
1213 }
1214 
1215 void AMDGPUInstPrinter::printOModSI(const MCInst *MI, unsigned OpNo,
1216                                     const MCSubtargetInfo &STI,
1217                                     raw_ostream &O) {
1218   int Imm = MI->getOperand(OpNo).getImm();
1219   if (Imm == SIOutMods::MUL2)
1220     O << " mul:2";
1221   else if (Imm == SIOutMods::MUL4)
1222     O << " mul:4";
1223   else if (Imm == SIOutMods::DIV2)
1224     O << " div:2";
1225 }
1226 
1227 void AMDGPUInstPrinter::printSendMsg(const MCInst *MI, unsigned OpNo,
1228                                      const MCSubtargetInfo &STI,
1229                                      raw_ostream &O) {
1230   using namespace llvm::AMDGPU::SendMsg;
1231 
1232   const unsigned Imm16 = MI->getOperand(OpNo).getImm();
1233 
1234   uint16_t MsgId;
1235   uint16_t OpId;
1236   uint16_t StreamId;
1237   decodeMsg(Imm16, MsgId, OpId, StreamId);
1238 
1239   if (isValidMsgId(MsgId, STI) &&
1240       isValidMsgOp(MsgId, OpId) &&
1241       isValidMsgStream(MsgId, OpId, StreamId)) {
1242     O << "sendmsg(" << getMsgName(MsgId);
1243     if (msgRequiresOp(MsgId)) {
1244       O << ", " << getMsgOpName(MsgId, OpId);
1245       if (msgSupportsStream(MsgId, OpId)) {
1246         O << ", " << StreamId;
1247       }
1248     }
1249     O << ')';
1250   } else if (encodeMsg(MsgId, OpId, StreamId) == Imm16) {
1251     O << "sendmsg(" << MsgId << ", " << OpId << ", " << StreamId << ')';
1252   } else {
1253     O << Imm16; // Unknown imm16 code.
1254   }
1255 }
1256 
1257 static void printSwizzleBitmask(const uint16_t AndMask,
1258                                 const uint16_t OrMask,
1259                                 const uint16_t XorMask,
1260                                 raw_ostream &O) {
1261   using namespace llvm::AMDGPU::Swizzle;
1262 
1263   uint16_t Probe0 = ((0            & AndMask) | OrMask) ^ XorMask;
1264   uint16_t Probe1 = ((BITMASK_MASK & AndMask) | OrMask) ^ XorMask;
1265 
1266   O << "\"";
1267 
1268   for (unsigned Mask = 1 << (BITMASK_WIDTH - 1); Mask > 0; Mask >>= 1) {
1269     uint16_t p0 = Probe0 & Mask;
1270     uint16_t p1 = Probe1 & Mask;
1271 
1272     if (p0 == p1) {
1273       if (p0 == 0) {
1274         O << "0";
1275       } else {
1276         O << "1";
1277       }
1278     } else {
1279       if (p0 == 0) {
1280         O << "p";
1281       } else {
1282         O << "i";
1283       }
1284     }
1285   }
1286 
1287   O << "\"";
1288 }
1289 
1290 void AMDGPUInstPrinter::printSwizzle(const MCInst *MI, unsigned OpNo,
1291                                      const MCSubtargetInfo &STI,
1292                                      raw_ostream &O) {
1293   using namespace llvm::AMDGPU::Swizzle;
1294 
1295   uint16_t Imm = MI->getOperand(OpNo).getImm();
1296   if (Imm == 0) {
1297     return;
1298   }
1299 
1300   O << " offset:";
1301 
1302   if ((Imm & QUAD_PERM_ENC_MASK) == QUAD_PERM_ENC) {
1303 
1304     O << "swizzle(" << IdSymbolic[ID_QUAD_PERM];
1305     for (unsigned I = 0; I < LANE_NUM; ++I) {
1306       O << ",";
1307       O << formatDec(Imm & LANE_MASK);
1308       Imm >>= LANE_SHIFT;
1309     }
1310     O << ")";
1311 
1312   } else if ((Imm & BITMASK_PERM_ENC_MASK) == BITMASK_PERM_ENC) {
1313 
1314     uint16_t AndMask = (Imm >> BITMASK_AND_SHIFT) & BITMASK_MASK;
1315     uint16_t OrMask  = (Imm >> BITMASK_OR_SHIFT)  & BITMASK_MASK;
1316     uint16_t XorMask = (Imm >> BITMASK_XOR_SHIFT) & BITMASK_MASK;
1317 
1318     if (AndMask == BITMASK_MAX &&
1319         OrMask == 0 &&
1320         countPopulation(XorMask) == 1) {
1321 
1322       O << "swizzle(" << IdSymbolic[ID_SWAP];
1323       O << ",";
1324       O << formatDec(XorMask);
1325       O << ")";
1326 
1327     } else if (AndMask == BITMASK_MAX &&
1328                OrMask == 0 && XorMask > 0 &&
1329                isPowerOf2_64(XorMask + 1)) {
1330 
1331       O << "swizzle(" << IdSymbolic[ID_REVERSE];
1332       O << ",";
1333       O << formatDec(XorMask + 1);
1334       O << ")";
1335 
1336     } else {
1337 
1338       uint16_t GroupSize = BITMASK_MAX - AndMask + 1;
1339       if (GroupSize > 1 &&
1340           isPowerOf2_64(GroupSize) &&
1341           OrMask < GroupSize &&
1342           XorMask == 0) {
1343 
1344         O << "swizzle(" << IdSymbolic[ID_BROADCAST];
1345         O << ",";
1346         O << formatDec(GroupSize);
1347         O << ",";
1348         O << formatDec(OrMask);
1349         O << ")";
1350 
1351       } else {
1352         O << "swizzle(" << IdSymbolic[ID_BITMASK_PERM];
1353         O << ",";
1354         printSwizzleBitmask(AndMask, OrMask, XorMask, O);
1355         O << ")";
1356       }
1357     }
1358   } else {
1359     printU16ImmDecOperand(MI, OpNo, O);
1360   }
1361 }
1362 
1363 void AMDGPUInstPrinter::printWaitFlag(const MCInst *MI, unsigned OpNo,
1364                                       const MCSubtargetInfo &STI,
1365                                       raw_ostream &O) {
1366   AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(STI.getCPU());
1367 
1368   unsigned SImm16 = MI->getOperand(OpNo).getImm();
1369   unsigned Vmcnt, Expcnt, Lgkmcnt;
1370   decodeWaitcnt(ISA, SImm16, Vmcnt, Expcnt, Lgkmcnt);
1371 
1372   bool NeedSpace = false;
1373 
1374   if (Vmcnt != getVmcntBitMask(ISA)) {
1375     O << "vmcnt(" << Vmcnt << ')';
1376     NeedSpace = true;
1377   }
1378 
1379   if (Expcnt != getExpcntBitMask(ISA)) {
1380     if (NeedSpace)
1381       O << ' ';
1382     O << "expcnt(" << Expcnt << ')';
1383     NeedSpace = true;
1384   }
1385 
1386   if (Lgkmcnt != getLgkmcntBitMask(ISA)) {
1387     if (NeedSpace)
1388       O << ' ';
1389     O << "lgkmcnt(" << Lgkmcnt << ')';
1390   }
1391 }
1392 
1393 void AMDGPUInstPrinter::printHwreg(const MCInst *MI, unsigned OpNo,
1394                                    const MCSubtargetInfo &STI, raw_ostream &O) {
1395   unsigned Id;
1396   unsigned Offset;
1397   unsigned Width;
1398 
1399   using namespace llvm::AMDGPU::Hwreg;
1400   unsigned Val = MI->getOperand(OpNo).getImm();
1401   decodeHwreg(Val, Id, Offset, Width);
1402   StringRef HwRegName = getHwreg(Id, STI);
1403 
1404   O << "hwreg(";
1405   if (!HwRegName.empty()) {
1406     O << HwRegName;
1407   } else {
1408     O << Id;
1409   }
1410   if (Width != WIDTH_DEFAULT_ || Offset != OFFSET_DEFAULT_) {
1411     O << ", " << Offset << ", " << Width;
1412   }
1413   O << ')';
1414 }
1415 
1416 void AMDGPUInstPrinter::printEndpgm(const MCInst *MI, unsigned OpNo,
1417                                     const MCSubtargetInfo &STI,
1418                                     raw_ostream &O) {
1419   uint16_t Imm = MI->getOperand(OpNo).getImm();
1420   if (Imm == 0) {
1421     return;
1422   }
1423 
1424   O << ' ' << formatDec(Imm);
1425 }
1426 
1427 #include "AMDGPUGenAsmWriter.inc"
1428 
1429 void R600InstPrinter::printInst(const MCInst *MI, uint64_t Address,
1430                                 StringRef Annot, const MCSubtargetInfo &STI,
1431                                 raw_ostream &O) {
1432   O.flush();
1433   printInstruction(MI, Address, O);
1434   printAnnotation(O, Annot);
1435 }
1436 
1437 void R600InstPrinter::printAbs(const MCInst *MI, unsigned OpNo,
1438                                raw_ostream &O) {
1439   AMDGPUInstPrinter::printIfSet(MI, OpNo, O, '|');
1440 }
1441 
1442 void R600InstPrinter::printBankSwizzle(const MCInst *MI, unsigned OpNo,
1443                                        raw_ostream &O) {
1444   int BankSwizzle = MI->getOperand(OpNo).getImm();
1445   switch (BankSwizzle) {
1446   case 1:
1447     O << "BS:VEC_021/SCL_122";
1448     break;
1449   case 2:
1450     O << "BS:VEC_120/SCL_212";
1451     break;
1452   case 3:
1453     O << "BS:VEC_102/SCL_221";
1454     break;
1455   case 4:
1456     O << "BS:VEC_201";
1457     break;
1458   case 5:
1459     O << "BS:VEC_210";
1460     break;
1461   default:
1462     break;
1463   }
1464 }
1465 
1466 void R600InstPrinter::printClamp(const MCInst *MI, unsigned OpNo,
1467                                  raw_ostream &O) {
1468   AMDGPUInstPrinter::printIfSet(MI, OpNo, O, "_SAT");
1469 }
1470 
1471 void R600InstPrinter::printCT(const MCInst *MI, unsigned OpNo,
1472                                 raw_ostream &O) {
1473   unsigned CT = MI->getOperand(OpNo).getImm();
1474   switch (CT) {
1475   case 0:
1476     O << 'U';
1477     break;
1478   case 1:
1479     O << 'N';
1480     break;
1481   default:
1482     break;
1483   }
1484 }
1485 
1486 void R600InstPrinter::printKCache(const MCInst *MI, unsigned OpNo,
1487                                   raw_ostream &O) {
1488   int KCacheMode = MI->getOperand(OpNo).getImm();
1489   if (KCacheMode > 0) {
1490     int KCacheBank = MI->getOperand(OpNo - 2).getImm();
1491     O << "CB" << KCacheBank << ':';
1492     int KCacheAddr = MI->getOperand(OpNo + 2).getImm();
1493     int LineSize = (KCacheMode == 1) ? 16 : 32;
1494     O << KCacheAddr * 16 << '-' << KCacheAddr * 16 + LineSize;
1495   }
1496 }
1497 
1498 void R600InstPrinter::printLast(const MCInst *MI, unsigned OpNo,
1499                                 raw_ostream &O) {
1500   AMDGPUInstPrinter::printIfSet(MI, OpNo, O, "*", " ");
1501 }
1502 
1503 void R600InstPrinter::printLiteral(const MCInst *MI, unsigned OpNo,
1504                                    raw_ostream &O) {
1505   const MCOperand &Op = MI->getOperand(OpNo);
1506   assert(Op.isImm() || Op.isExpr());
1507   if (Op.isImm()) {
1508     int64_t Imm = Op.getImm();
1509     O << Imm << '(' << BitsToFloat(Imm) << ')';
1510   }
1511   if (Op.isExpr()) {
1512     Op.getExpr()->print(O << '@', &MAI);
1513   }
1514 }
1515 
1516 void R600InstPrinter::printNeg(const MCInst *MI, unsigned OpNo,
1517                                raw_ostream &O) {
1518   AMDGPUInstPrinter::printIfSet(MI, OpNo, O, '-');
1519 }
1520 
1521 void R600InstPrinter::printOMOD(const MCInst *MI, unsigned OpNo,
1522                                 raw_ostream &O) {
1523   switch (MI->getOperand(OpNo).getImm()) {
1524   default: break;
1525   case 1:
1526     O << " * 2.0";
1527     break;
1528   case 2:
1529     O << " * 4.0";
1530     break;
1531   case 3:
1532     O << " / 2.0";
1533     break;
1534   }
1535 }
1536 
1537 void R600InstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo,
1538                                       raw_ostream &O) {
1539   printOperand(MI, OpNo, O);
1540   O  << ", ";
1541   printOperand(MI, OpNo + 1, O);
1542 }
1543 
1544 void R600InstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
1545                                    raw_ostream &O) {
1546   if (OpNo >= MI->getNumOperands()) {
1547     O << "/*Missing OP" << OpNo << "*/";
1548     return;
1549   }
1550 
1551   const MCOperand &Op = MI->getOperand(OpNo);
1552   if (Op.isReg()) {
1553     switch (Op.getReg()) {
1554     // This is the default predicate state, so we don't need to print it.
1555     case R600::PRED_SEL_OFF:
1556       break;
1557 
1558     default:
1559       O << getRegisterName(Op.getReg());
1560       break;
1561     }
1562   } else if (Op.isImm()) {
1563       O << Op.getImm();
1564   } else if (Op.isDFPImm()) {
1565     // We special case 0.0 because otherwise it will be printed as an integer.
1566     if (Op.getDFPImm() == 0.0)
1567       O << "0.0";
1568     else {
1569       O << bit_cast<double>(Op.getDFPImm());
1570     }
1571   } else if (Op.isExpr()) {
1572     const MCExpr *Exp = Op.getExpr();
1573     Exp->print(O, &MAI);
1574   } else {
1575     O << "/*INV_OP*/";
1576   }
1577 }
1578 
1579 void R600InstPrinter::printRel(const MCInst *MI, unsigned OpNo,
1580                                raw_ostream &O) {
1581   AMDGPUInstPrinter::printIfSet(MI, OpNo, O, '+');
1582 }
1583 
1584 void R600InstPrinter::printRSel(const MCInst *MI, unsigned OpNo,
1585                                   raw_ostream &O) {
1586   unsigned Sel = MI->getOperand(OpNo).getImm();
1587   switch (Sel) {
1588   case 0:
1589     O << 'X';
1590     break;
1591   case 1:
1592     O << 'Y';
1593     break;
1594   case 2:
1595     O << 'Z';
1596     break;
1597   case 3:
1598     O << 'W';
1599     break;
1600   case 4:
1601     O << '0';
1602     break;
1603   case 5:
1604     O << '1';
1605     break;
1606   case 7:
1607     O << '_';
1608     break;
1609   default:
1610     break;
1611   }
1612 }
1613 
1614 void R600InstPrinter::printUpdateExecMask(const MCInst *MI, unsigned OpNo,
1615                                           raw_ostream &O) {
1616   AMDGPUInstPrinter::printIfSet(MI, OpNo, O, "ExecMask,");
1617 }
1618 
1619 void R600InstPrinter::printUpdatePred(const MCInst *MI, unsigned OpNo,
1620                                       raw_ostream &O) {
1621   AMDGPUInstPrinter::printIfSet(MI, OpNo, O, "Pred,");
1622 }
1623 
1624 void R600InstPrinter::printWrite(const MCInst *MI, unsigned OpNo,
1625                                  raw_ostream &O) {
1626   const MCOperand &Op = MI->getOperand(OpNo);
1627   if (Op.getImm() == 0) {
1628     O << " (MASKED)";
1629   }
1630 }
1631 
1632 #include "R600GenAsmWriter.inc"
1633