1 //===-- AMDGPUInstPrinter.cpp - AMDGPU MC Inst -> ASM ---------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 // \file
8 //===----------------------------------------------------------------------===//
9 
10 #include "AMDGPUInstPrinter.h"
11 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
12 #include "SIDefines.h"
13 #include "SIRegisterInfo.h"
14 #include "Utils/AMDGPUAsmUtils.h"
15 #include "Utils/AMDGPUBaseInfo.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCInstrDesc.h"
19 #include "llvm/MC/MCInstrInfo.h"
20 #include "llvm/MC/MCSubtargetInfo.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/TargetParser.h"
23 
24 using namespace llvm;
25 using namespace llvm::AMDGPU;
26 
27 static cl::opt<bool> Keep16BitSuffixes(
28   "amdgpu-keep-16-bit-reg-suffixes",
29   cl::desc("Keep .l and .h suffixes in asm for debugging purposes"),
30   cl::init(false),
31   cl::ReallyHidden);
32 
33 void AMDGPUInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
34   // FIXME: The current implementation of
35   // AsmParser::parseRegisterOrRegisterNumber in MC implies we either emit this
36   // as an integer or we provide a name which represents a physical register.
37   // For CFI instructions we really want to emit a name for the DWARF register
38   // instead, because there may be multiple DWARF registers corresponding to a
39   // single physical register. One case where this problem manifests is with
40   // wave32/wave64 where using the physical register name is ambiguous: if we
41   // write e.g. `.cfi_undefined v0` we lose information about the wavefront
42   // size which we need to encode the register in the final DWARF. Ideally we
43   // would extend MC to support parsing DWARF register names so we could do
44   // something like `.cfi_undefined dwarf_wave32_v0`. For now we just live with
45   // non-pretty DWARF register names in assembly text.
46   OS << RegNo;
47 }
48 
49 void AMDGPUInstPrinter::printInst(const MCInst *MI, uint64_t Address,
50                                   StringRef Annot, const MCSubtargetInfo &STI,
51                                   raw_ostream &OS) {
52   OS.flush();
53   printInstruction(MI, Address, STI, OS);
54   printAnnotation(OS, Annot);
55 }
56 
57 void AMDGPUInstPrinter::printU4ImmOperand(const MCInst *MI, unsigned OpNo,
58                                           const MCSubtargetInfo &STI,
59                                           raw_ostream &O) {
60   O << formatHex(MI->getOperand(OpNo).getImm() & 0xf);
61 }
62 
63 void AMDGPUInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo,
64                                           raw_ostream &O) {
65   O << formatHex(MI->getOperand(OpNo).getImm() & 0xff);
66 }
67 
68 void AMDGPUInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
69                                            const MCSubtargetInfo &STI,
70                                            raw_ostream &O) {
71   // It's possible to end up with a 32-bit literal used with a 16-bit operand
72   // with ignored high bits. Print as 32-bit anyway in that case.
73   int64_t Imm = MI->getOperand(OpNo).getImm();
74   if (isInt<16>(Imm) || isUInt<16>(Imm))
75     O << formatHex(static_cast<uint64_t>(Imm & 0xffff));
76   else
77     printU32ImmOperand(MI, OpNo, STI, O);
78 }
79 
80 void AMDGPUInstPrinter::printU4ImmDecOperand(const MCInst *MI, unsigned OpNo,
81                                              raw_ostream &O) {
82   O << formatDec(MI->getOperand(OpNo).getImm() & 0xf);
83 }
84 
85 void AMDGPUInstPrinter::printU8ImmDecOperand(const MCInst *MI, unsigned OpNo,
86                                              raw_ostream &O) {
87   O << formatDec(MI->getOperand(OpNo).getImm() & 0xff);
88 }
89 
90 void AMDGPUInstPrinter::printU16ImmDecOperand(const MCInst *MI, unsigned OpNo,
91                                               raw_ostream &O) {
92   O << formatDec(MI->getOperand(OpNo).getImm() & 0xffff);
93 }
94 
95 void AMDGPUInstPrinter::printU32ImmOperand(const MCInst *MI, unsigned OpNo,
96                                            const MCSubtargetInfo &STI,
97                                            raw_ostream &O) {
98   O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff);
99 }
100 
101 void AMDGPUInstPrinter::printNamedBit(const MCInst *MI, unsigned OpNo,
102                                       raw_ostream &O, StringRef BitName) {
103   if (MI->getOperand(OpNo).getImm()) {
104     O << ' ' << BitName;
105   }
106 }
107 
108 void AMDGPUInstPrinter::printOffen(const MCInst *MI, unsigned OpNo,
109                                    raw_ostream &O) {
110   printNamedBit(MI, OpNo, O, "offen");
111 }
112 
113 void AMDGPUInstPrinter::printIdxen(const MCInst *MI, unsigned OpNo,
114                                    raw_ostream &O) {
115   printNamedBit(MI, OpNo, O, "idxen");
116 }
117 
118 void AMDGPUInstPrinter::printAddr64(const MCInst *MI, unsigned OpNo,
119                                     raw_ostream &O) {
120   printNamedBit(MI, OpNo, O, "addr64");
121 }
122 
123 void AMDGPUInstPrinter::printOffset(const MCInst *MI, unsigned OpNo,
124                                     const MCSubtargetInfo &STI,
125                                     raw_ostream &O) {
126   uint16_t Imm = MI->getOperand(OpNo).getImm();
127   if (Imm != 0) {
128     O << " offset:";
129     printU16ImmDecOperand(MI, OpNo, O);
130   }
131 }
132 
133 void AMDGPUInstPrinter::printFlatOffset(const MCInst *MI, unsigned OpNo,
134                                         const MCSubtargetInfo &STI,
135                                         raw_ostream &O) {
136   uint16_t Imm = MI->getOperand(OpNo).getImm();
137   if (Imm != 0) {
138     O << " offset:";
139 
140     const MCInstrDesc &Desc = MII.get(MI->getOpcode());
141     bool IsFlatSeg = !(Desc.TSFlags &
142                        (SIInstrFlags::FlatGlobal | SIInstrFlags::FlatScratch));
143 
144     if (IsFlatSeg) { // Unsigned offset
145       printU16ImmDecOperand(MI, OpNo, O);
146     } else {         // Signed offset
147       if (AMDGPU::isGFX10(STI)) {
148         O << formatDec(SignExtend32<12>(MI->getOperand(OpNo).getImm()));
149       } else {
150         O << formatDec(SignExtend32<13>(MI->getOperand(OpNo).getImm()));
151       }
152     }
153   }
154 }
155 
156 void AMDGPUInstPrinter::printOffset0(const MCInst *MI, unsigned OpNo,
157                                      const MCSubtargetInfo &STI,
158                                      raw_ostream &O) {
159   if (MI->getOperand(OpNo).getImm()) {
160     O << " offset0:";
161     printU8ImmDecOperand(MI, OpNo, O);
162   }
163 }
164 
165 void AMDGPUInstPrinter::printOffset1(const MCInst *MI, unsigned OpNo,
166                                      const MCSubtargetInfo &STI,
167                                      raw_ostream &O) {
168   if (MI->getOperand(OpNo).getImm()) {
169     O << " offset1:";
170     printU8ImmDecOperand(MI, OpNo, O);
171   }
172 }
173 
174 void AMDGPUInstPrinter::printSMRDOffset8(const MCInst *MI, unsigned OpNo,
175                                         const MCSubtargetInfo &STI,
176                                         raw_ostream &O) {
177   printU32ImmOperand(MI, OpNo, STI, O);
178 }
179 
180 void AMDGPUInstPrinter::printSMEMOffset(const MCInst *MI, unsigned OpNo,
181                                         const MCSubtargetInfo &STI,
182                                         raw_ostream &O) {
183   O << formatHex(MI->getOperand(OpNo).getImm());
184 }
185 
186 void AMDGPUInstPrinter::printSMEMOffsetMod(const MCInst *MI, unsigned OpNo,
187                                            const MCSubtargetInfo &STI,
188                                            raw_ostream &O) {
189   O << " offset:";
190   printSMEMOffset(MI, OpNo, STI, O);
191 }
192 
193 void AMDGPUInstPrinter::printSMRDLiteralOffset(const MCInst *MI, unsigned OpNo,
194                                                const MCSubtargetInfo &STI,
195                                                raw_ostream &O) {
196   printU32ImmOperand(MI, OpNo, STI, O);
197 }
198 
199 void AMDGPUInstPrinter::printGDS(const MCInst *MI, unsigned OpNo,
200                                  const MCSubtargetInfo &STI, raw_ostream &O) {
201   printNamedBit(MI, OpNo, O, "gds");
202 }
203 
204 void AMDGPUInstPrinter::printCPol(const MCInst *MI, unsigned OpNo,
205                                   const MCSubtargetInfo &STI, raw_ostream &O) {
206   auto Imm = MI->getOperand(OpNo).getImm();
207   if (Imm & CPol::GLC)
208     O << ((AMDGPU::isGFX940(STI) &&
209            !(MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::SMRD)) ? " sc0"
210                                                                      : " glc");
211   if (Imm & CPol::SLC)
212     O << (AMDGPU::isGFX940(STI) ? " nt" : " slc");
213   if ((Imm & CPol::DLC) && AMDGPU::isGFX10Plus(STI))
214     O << " dlc";
215   if ((Imm & CPol::SCC) && AMDGPU::isGFX90A(STI))
216     O << (AMDGPU::isGFX940(STI) ? " sc1" : " scc");
217   if (Imm & ~CPol::ALL)
218     O << " /* unexpected cache policy bit */";
219 }
220 
221 void AMDGPUInstPrinter::printSWZ(const MCInst *MI, unsigned OpNo,
222                                  const MCSubtargetInfo &STI, raw_ostream &O) {
223 }
224 
225 void AMDGPUInstPrinter::printTFE(const MCInst *MI, unsigned OpNo,
226                                  const MCSubtargetInfo &STI, raw_ostream &O) {
227   printNamedBit(MI, OpNo, O, "tfe");
228 }
229 
230 void AMDGPUInstPrinter::printDMask(const MCInst *MI, unsigned OpNo,
231                                    const MCSubtargetInfo &STI, raw_ostream &O) {
232   if (MI->getOperand(OpNo).getImm()) {
233     O << " dmask:";
234     printU16ImmOperand(MI, OpNo, STI, O);
235   }
236 }
237 
238 void AMDGPUInstPrinter::printDim(const MCInst *MI, unsigned OpNo,
239                                  const MCSubtargetInfo &STI, raw_ostream &O) {
240   unsigned Dim = MI->getOperand(OpNo).getImm();
241   O << " dim:SQ_RSRC_IMG_";
242 
243   const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfoByEncoding(Dim);
244   if (DimInfo)
245     O << DimInfo->AsmSuffix;
246   else
247     O << Dim;
248 }
249 
250 void AMDGPUInstPrinter::printUNorm(const MCInst *MI, unsigned OpNo,
251                                    const MCSubtargetInfo &STI, raw_ostream &O) {
252   printNamedBit(MI, OpNo, O, "unorm");
253 }
254 
255 void AMDGPUInstPrinter::printDA(const MCInst *MI, unsigned OpNo,
256                                 const MCSubtargetInfo &STI, raw_ostream &O) {
257   printNamedBit(MI, OpNo, O, "da");
258 }
259 
260 void AMDGPUInstPrinter::printR128A16(const MCInst *MI, unsigned OpNo,
261                                   const MCSubtargetInfo &STI, raw_ostream &O) {
262   if (STI.hasFeature(AMDGPU::FeatureR128A16))
263     printNamedBit(MI, OpNo, O, "a16");
264   else
265     printNamedBit(MI, OpNo, O, "r128");
266 }
267 
268 void AMDGPUInstPrinter::printGFX10A16(const MCInst *MI, unsigned OpNo,
269                                   const MCSubtargetInfo &STI, raw_ostream &O) {
270   printNamedBit(MI, OpNo, O, "a16");
271 }
272 
273 void AMDGPUInstPrinter::printLWE(const MCInst *MI, unsigned OpNo,
274                                  const MCSubtargetInfo &STI, raw_ostream &O) {
275   printNamedBit(MI, OpNo, O, "lwe");
276 }
277 
278 void AMDGPUInstPrinter::printD16(const MCInst *MI, unsigned OpNo,
279                                  const MCSubtargetInfo &STI, raw_ostream &O) {
280   printNamedBit(MI, OpNo, O, "d16");
281 }
282 
283 void AMDGPUInstPrinter::printExpCompr(const MCInst *MI, unsigned OpNo,
284                                       const MCSubtargetInfo &STI,
285                                       raw_ostream &O) {
286   printNamedBit(MI, OpNo, O, "compr");
287 }
288 
289 void AMDGPUInstPrinter::printExpVM(const MCInst *MI, unsigned OpNo,
290                                    const MCSubtargetInfo &STI,
291                                    raw_ostream &O) {
292   printNamedBit(MI, OpNo, O, "vm");
293 }
294 
295 void AMDGPUInstPrinter::printFORMAT(const MCInst *MI, unsigned OpNo,
296                                     const MCSubtargetInfo &STI,
297                                     raw_ostream &O) {
298 }
299 
300 void AMDGPUInstPrinter::printSymbolicFormat(const MCInst *MI,
301                                             const MCSubtargetInfo &STI,
302                                             raw_ostream &O) {
303   using namespace llvm::AMDGPU::MTBUFFormat;
304 
305   int OpNo =
306     AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::format);
307   assert(OpNo != -1);
308 
309   unsigned Val = MI->getOperand(OpNo).getImm();
310   if (AMDGPU::isGFX10Plus(STI)) {
311     if (Val == UFMT_DEFAULT)
312       return;
313     if (isValidUnifiedFormat(Val, STI)) {
314       O << " format:[" << getUnifiedFormatName(Val, STI) << ']';
315     } else {
316       O << " format:" << Val;
317     }
318   } else {
319     if (Val == DFMT_NFMT_DEFAULT)
320       return;
321     if (isValidDfmtNfmt(Val, STI)) {
322       unsigned Dfmt;
323       unsigned Nfmt;
324       decodeDfmtNfmt(Val, Dfmt, Nfmt);
325       O << " format:[";
326       if (Dfmt != DFMT_DEFAULT) {
327         O << getDfmtName(Dfmt);
328         if (Nfmt != NFMT_DEFAULT) {
329           O << ',';
330         }
331       }
332       if (Nfmt != NFMT_DEFAULT) {
333         O << getNfmtName(Nfmt, STI);
334       }
335       O << ']';
336     } else {
337       O << " format:" << Val;
338     }
339   }
340 }
341 
342 void AMDGPUInstPrinter::printRegOperand(unsigned RegNo, raw_ostream &O,
343                                         const MCRegisterInfo &MRI) {
344 #if !defined(NDEBUG)
345   switch (RegNo) {
346   case AMDGPU::FP_REG:
347   case AMDGPU::SP_REG:
348   case AMDGPU::PRIVATE_RSRC_REG:
349     llvm_unreachable("pseudo-register should not ever be emitted");
350   case AMDGPU::SCC:
351     llvm_unreachable("pseudo scc should not ever be emitted");
352   default:
353     break;
354   }
355 #endif
356 
357   StringRef RegName(getRegisterName(RegNo));
358   if (!Keep16BitSuffixes)
359     if (!RegName.consume_back(".l"))
360       RegName.consume_back(".h");
361 
362   O << RegName;
363 }
364 
365 void AMDGPUInstPrinter::printVOPDst(const MCInst *MI, unsigned OpNo,
366                                     const MCSubtargetInfo &STI, raw_ostream &O) {
367   auto Opcode = MI->getOpcode();
368   auto Flags = MII.get(Opcode).TSFlags;
369   if (OpNo == 0) {
370     if (Flags & SIInstrFlags::VOP3 && Flags & SIInstrFlags::DPP)
371       O << "_e64_dpp";
372     else if (Flags & SIInstrFlags::VOP3) {
373       if (!getVOP3IsSingle(Opcode))
374         O << "_e64";
375     } else if (Flags & SIInstrFlags::DPP)
376       O << "_dpp";
377     else if (Flags & SIInstrFlags::SDWA)
378       O << "_sdwa";
379     else if (((Flags & SIInstrFlags::VOP1) && !getVOP1IsSingle(Opcode)) ||
380              ((Flags & SIInstrFlags::VOP2) && !getVOP2IsSingle(Opcode)))
381       O << "_e32";
382     O << " ";
383   }
384 
385   printOperand(MI, OpNo, STI, O);
386 
387   // Print default vcc/vcc_lo operand.
388   switch (Opcode) {
389   default: break;
390 
391   case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10:
392   case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10:
393   case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10:
394   case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10:
395   case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10:
396   case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10:
397   case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10:
398   case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10:
399   case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10:
400   case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10:
401   case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10:
402   case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10:
403   case AMDGPU::V_ADD_CO_CI_U32_e32_gfx11:
404   case AMDGPU::V_SUB_CO_CI_U32_e32_gfx11:
405   case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx11:
406   case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx11:
407   case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx11:
408   case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx11:
409   case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx11:
410   case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx11:
411   case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx11:
412     printDefaultVccOperand(false, STI, O);
413     break;
414   }
415 }
416 
417 void AMDGPUInstPrinter::printVINTRPDst(const MCInst *MI, unsigned OpNo,
418                                        const MCSubtargetInfo &STI, raw_ostream &O) {
419   if (AMDGPU::isSI(STI) || AMDGPU::isCI(STI))
420     O << " ";
421   else
422     O << "_e32 ";
423 
424   printOperand(MI, OpNo, STI, O);
425 }
426 
427 void AMDGPUInstPrinter::printImmediateInt16(uint32_t Imm,
428                                             const MCSubtargetInfo &STI,
429                                             raw_ostream &O) {
430   int16_t SImm = static_cast<int16_t>(Imm);
431   if (isInlinableIntLiteral(SImm)) {
432     O << SImm;
433   } else {
434     uint64_t Imm16 = static_cast<uint16_t>(Imm);
435     O << formatHex(Imm16);
436   }
437 }
438 
439 void AMDGPUInstPrinter::printImmediate16(uint32_t Imm,
440                                          const MCSubtargetInfo &STI,
441                                          raw_ostream &O) {
442   int16_t SImm = static_cast<int16_t>(Imm);
443   if (isInlinableIntLiteral(SImm)) {
444     O << SImm;
445     return;
446   }
447 
448   if (Imm == 0x3C00)
449     O<< "1.0";
450   else if (Imm == 0xBC00)
451     O<< "-1.0";
452   else if (Imm == 0x3800)
453     O<< "0.5";
454   else if (Imm == 0xB800)
455     O<< "-0.5";
456   else if (Imm == 0x4000)
457     O<< "2.0";
458   else if (Imm == 0xC000)
459     O<< "-2.0";
460   else if (Imm == 0x4400)
461     O<< "4.0";
462   else if (Imm == 0xC400)
463     O<< "-4.0";
464   else if (Imm == 0x3118 &&
465            STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]) {
466     O << "0.15915494";
467   } else {
468     uint64_t Imm16 = static_cast<uint16_t>(Imm);
469     O << formatHex(Imm16);
470   }
471 }
472 
473 void AMDGPUInstPrinter::printImmediateV216(uint32_t Imm,
474                                            const MCSubtargetInfo &STI,
475                                            raw_ostream &O) {
476   uint16_t Lo16 = static_cast<uint16_t>(Imm);
477   printImmediate16(Lo16, STI, O);
478 }
479 
480 void AMDGPUInstPrinter::printImmediate32(uint32_t Imm,
481                                          const MCSubtargetInfo &STI,
482                                          raw_ostream &O) {
483   int32_t SImm = static_cast<int32_t>(Imm);
484   if (SImm >= -16 && SImm <= 64) {
485     O << SImm;
486     return;
487   }
488 
489   if (Imm == FloatToBits(0.0f))
490     O << "0.0";
491   else if (Imm == FloatToBits(1.0f))
492     O << "1.0";
493   else if (Imm == FloatToBits(-1.0f))
494     O << "-1.0";
495   else if (Imm == FloatToBits(0.5f))
496     O << "0.5";
497   else if (Imm == FloatToBits(-0.5f))
498     O << "-0.5";
499   else if (Imm == FloatToBits(2.0f))
500     O << "2.0";
501   else if (Imm == FloatToBits(-2.0f))
502     O << "-2.0";
503   else if (Imm == FloatToBits(4.0f))
504     O << "4.0";
505   else if (Imm == FloatToBits(-4.0f))
506     O << "-4.0";
507   else if (Imm == 0x3e22f983 &&
508            STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
509     O << "0.15915494";
510   else
511     O << formatHex(static_cast<uint64_t>(Imm));
512 }
513 
514 void AMDGPUInstPrinter::printImmediate64(uint64_t Imm,
515                                          const MCSubtargetInfo &STI,
516                                          raw_ostream &O) {
517   int64_t SImm = static_cast<int64_t>(Imm);
518   if (SImm >= -16 && SImm <= 64) {
519     O << SImm;
520     return;
521   }
522 
523   if (Imm == DoubleToBits(0.0))
524     O << "0.0";
525   else if (Imm == DoubleToBits(1.0))
526     O << "1.0";
527   else if (Imm == DoubleToBits(-1.0))
528     O << "-1.0";
529   else if (Imm == DoubleToBits(0.5))
530     O << "0.5";
531   else if (Imm == DoubleToBits(-0.5))
532     O << "-0.5";
533   else if (Imm == DoubleToBits(2.0))
534     O << "2.0";
535   else if (Imm == DoubleToBits(-2.0))
536     O << "-2.0";
537   else if (Imm == DoubleToBits(4.0))
538     O << "4.0";
539   else if (Imm == DoubleToBits(-4.0))
540     O << "-4.0";
541   else if (Imm == 0x3fc45f306dc9c882 &&
542            STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
543     O << "0.15915494309189532";
544   else {
545     assert(isUInt<32>(Imm) || Imm == 0x3fc45f306dc9c882);
546 
547     // In rare situations, we will have a 32-bit literal in a 64-bit
548     // operand. This is technically allowed for the encoding of s_mov_b64.
549     O << formatHex(static_cast<uint64_t>(Imm));
550   }
551 }
552 
553 void AMDGPUInstPrinter::printBLGP(const MCInst *MI, unsigned OpNo,
554                                   const MCSubtargetInfo &STI,
555                                   raw_ostream &O) {
556   unsigned Imm = MI->getOperand(OpNo).getImm();
557   if (!Imm)
558     return;
559 
560   if (AMDGPU::isGFX940(STI)) {
561     switch (MI->getOpcode()) {
562     case AMDGPU::V_MFMA_F64_16X16X4F64_gfx940_acd:
563     case AMDGPU::V_MFMA_F64_16X16X4F64_gfx940_vcd:
564     case AMDGPU::V_MFMA_F64_4X4X4F64_gfx940_acd:
565     case AMDGPU::V_MFMA_F64_4X4X4F64_gfx940_vcd:
566       O << " neg:[" << (Imm & 1) << ',' << ((Imm >> 1) & 1) << ','
567         << ((Imm >> 2) & 1) << ']';
568       return;
569     }
570   }
571 
572   O << " blgp:" << Imm;
573 }
574 
575 void AMDGPUInstPrinter::printCBSZ(const MCInst *MI, unsigned OpNo,
576                                   const MCSubtargetInfo &STI,
577                                   raw_ostream &O) {
578   unsigned Imm = MI->getOperand(OpNo).getImm();
579   if (!Imm)
580     return;
581 
582   O << " cbsz:" << Imm;
583 }
584 
585 void AMDGPUInstPrinter::printABID(const MCInst *MI, unsigned OpNo,
586                                   const MCSubtargetInfo &STI,
587                                   raw_ostream &O) {
588   unsigned Imm = MI->getOperand(OpNo).getImm();
589   if (!Imm)
590     return;
591 
592   O << " abid:" << Imm;
593 }
594 
595 void AMDGPUInstPrinter::printDefaultVccOperand(bool FirstOperand,
596                                                const MCSubtargetInfo &STI,
597                                                raw_ostream &O) {
598   if (!FirstOperand)
599     O << ", ";
600   printRegOperand(STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64]
601                       ? AMDGPU::VCC
602                       : AMDGPU::VCC_LO,
603                   O, MRI);
604   if (FirstOperand)
605     O << ", ";
606 }
607 
608 void AMDGPUInstPrinter::printWaitVDST(const MCInst *MI, unsigned OpNo,
609                                       const MCSubtargetInfo &STI,
610                                       raw_ostream &O) {
611   uint8_t Imm = MI->getOperand(OpNo).getImm();
612   if (Imm != 0) {
613     O << " wait_vdst:";
614     printU4ImmDecOperand(MI, OpNo, O);
615   }
616 }
617 
618 void AMDGPUInstPrinter::printWaitEXP(const MCInst *MI, unsigned OpNo,
619                                     const MCSubtargetInfo &STI,
620                                     raw_ostream &O) {
621   uint8_t Imm = MI->getOperand(OpNo).getImm();
622   if (Imm != 0) {
623     O << " wait_exp:";
624     printU4ImmDecOperand(MI, OpNo, O);
625   }
626 }
627 
628 // Print default vcc/vcc_lo operand of VOPC.
629 void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
630                                      const MCSubtargetInfo &STI,
631                                      raw_ostream &O) {
632   // Print default vcc/vcc_lo operand of VOPC.
633   const MCInstrDesc &Desc = MII.get(MI->getOpcode());
634   if (OpNo == 0 && (Desc.TSFlags & SIInstrFlags::VOPC) &&
635       (Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC) ||
636        Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC_LO)))
637     printDefaultVccOperand(true, STI, O);
638 
639   if (OpNo >= MI->getNumOperands()) {
640     O << "/*Missing OP" << OpNo << "*/";
641     return;
642   }
643 
644   const MCOperand &Op = MI->getOperand(OpNo);
645   if (Op.isReg()) {
646     printRegOperand(Op.getReg(), O, MRI);
647   } else if (Op.isImm()) {
648     const uint8_t OpTy = Desc.OpInfo[OpNo].OperandType;
649     switch (OpTy) {
650     case AMDGPU::OPERAND_REG_IMM_INT32:
651     case AMDGPU::OPERAND_REG_IMM_FP32:
652     case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED:
653     case AMDGPU::OPERAND_REG_INLINE_C_INT32:
654     case AMDGPU::OPERAND_REG_INLINE_C_FP32:
655     case AMDGPU::OPERAND_REG_INLINE_AC_INT32:
656     case AMDGPU::OPERAND_REG_INLINE_AC_FP32:
657     case AMDGPU::OPERAND_REG_IMM_V2INT32:
658     case AMDGPU::OPERAND_REG_IMM_V2FP32:
659     case AMDGPU::OPERAND_REG_INLINE_C_V2INT32:
660     case AMDGPU::OPERAND_REG_INLINE_C_V2FP32:
661     case MCOI::OPERAND_IMMEDIATE:
662       printImmediate32(Op.getImm(), STI, O);
663       break;
664     case AMDGPU::OPERAND_REG_IMM_INT64:
665     case AMDGPU::OPERAND_REG_IMM_FP64:
666     case AMDGPU::OPERAND_REG_INLINE_C_INT64:
667     case AMDGPU::OPERAND_REG_INLINE_C_FP64:
668     case AMDGPU::OPERAND_REG_INLINE_AC_FP64:
669       printImmediate64(Op.getImm(), STI, O);
670       break;
671     case AMDGPU::OPERAND_REG_INLINE_C_INT16:
672     case AMDGPU::OPERAND_REG_INLINE_AC_INT16:
673     case AMDGPU::OPERAND_REG_IMM_INT16:
674       printImmediateInt16(Op.getImm(), STI, O);
675       break;
676     case AMDGPU::OPERAND_REG_INLINE_C_FP16:
677     case AMDGPU::OPERAND_REG_INLINE_AC_FP16:
678     case AMDGPU::OPERAND_REG_IMM_FP16:
679     case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED:
680       printImmediate16(Op.getImm(), STI, O);
681       break;
682     case AMDGPU::OPERAND_REG_IMM_V2INT16:
683     case AMDGPU::OPERAND_REG_IMM_V2FP16:
684       if (!isUInt<16>(Op.getImm()) &&
685           STI.getFeatureBits()[AMDGPU::FeatureVOP3Literal]) {
686         printImmediate32(Op.getImm(), STI, O);
687         break;
688       }
689 
690       //  Deal with 16-bit FP inline immediates not working.
691       if (OpTy == AMDGPU::OPERAND_REG_IMM_V2FP16) {
692         printImmediate16(static_cast<uint16_t>(Op.getImm()), STI, O);
693         break;
694       }
695       LLVM_FALLTHROUGH;
696     case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
697     case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:
698       printImmediateInt16(static_cast<uint16_t>(Op.getImm()), STI, O);
699       break;
700     case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
701     case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16:
702       printImmediateV216(Op.getImm(), STI, O);
703       break;
704     case MCOI::OPERAND_UNKNOWN:
705     case MCOI::OPERAND_PCREL:
706       O << formatDec(Op.getImm());
707       break;
708     case MCOI::OPERAND_REGISTER:
709       // FIXME: This should be removed and handled somewhere else. Seems to come
710       // from a disassembler bug.
711       O << "/*invalid immediate*/";
712       break;
713     default:
714       // We hit this for the immediate instruction bits that don't yet have a
715       // custom printer.
716       llvm_unreachable("unexpected immediate operand type");
717     }
718   } else if (Op.isDFPImm()) {
719     double Value = bit_cast<double>(Op.getDFPImm());
720     // We special case 0.0 because otherwise it will be printed as an integer.
721     if (Value == 0.0)
722       O << "0.0";
723     else {
724       const MCInstrDesc &Desc = MII.get(MI->getOpcode());
725       int RCID = Desc.OpInfo[OpNo].RegClass;
726       unsigned RCBits = AMDGPU::getRegBitWidth(MRI.getRegClass(RCID));
727       if (RCBits == 32)
728         printImmediate32(FloatToBits(Value), STI, O);
729       else if (RCBits == 64)
730         printImmediate64(DoubleToBits(Value), STI, O);
731       else
732         llvm_unreachable("Invalid register class size");
733     }
734   } else if (Op.isExpr()) {
735     const MCExpr *Exp = Op.getExpr();
736     Exp->print(O, &MAI);
737   } else {
738     O << "/*INV_OP*/";
739   }
740 
741   // Print default vcc/vcc_lo operand of v_cndmask_b32_e32.
742   switch (MI->getOpcode()) {
743   default: break;
744 
745   case AMDGPU::V_CNDMASK_B32_e32_gfx10:
746   case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10:
747   case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10:
748   case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10:
749   case AMDGPU::V_CNDMASK_B32_dpp_gfx10:
750   case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10:
751   case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10:
752   case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10:
753   case AMDGPU::V_CNDMASK_B32_dpp8_gfx10:
754   case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10:
755   case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10:
756   case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10:
757   case AMDGPU::V_CNDMASK_B32_e32_gfx11:
758   case AMDGPU::V_ADD_CO_CI_U32_e32_gfx11:
759   case AMDGPU::V_SUB_CO_CI_U32_e32_gfx11:
760   case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx11:
761   case AMDGPU::V_CNDMASK_B32_dpp_gfx11:
762   case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx11:
763   case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx11:
764   case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx11:
765   case AMDGPU::V_CNDMASK_B32_dpp8_gfx11:
766   case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx11:
767   case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx11:
768   case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx11:
769 
770   case AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7:
771   case AMDGPU::V_CNDMASK_B32_e32_vi:
772     if ((int)OpNo == AMDGPU::getNamedOperandIdx(MI->getOpcode(),
773                                                 AMDGPU::OpName::src1))
774       printDefaultVccOperand(OpNo == 0, STI, O);
775     break;
776   }
777 
778   if (Desc.TSFlags & SIInstrFlags::MTBUF) {
779     int SOffsetIdx =
780       AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::soffset);
781     assert(SOffsetIdx != -1);
782     if ((int)OpNo == SOffsetIdx)
783       printSymbolicFormat(MI, STI, O);
784   }
785 }
786 
787 void AMDGPUInstPrinter::printOperandAndFPInputMods(const MCInst *MI,
788                                                    unsigned OpNo,
789                                                    const MCSubtargetInfo &STI,
790                                                    raw_ostream &O) {
791   unsigned InputModifiers = MI->getOperand(OpNo).getImm();
792 
793   // Use 'neg(...)' instead of '-' to avoid ambiguity.
794   // This is important for integer literals because
795   // -1 is not the same value as neg(1).
796   bool NegMnemo = false;
797 
798   if (InputModifiers & SISrcMods::NEG) {
799     if (OpNo + 1 < MI->getNumOperands() &&
800         (InputModifiers & SISrcMods::ABS) == 0) {
801       const MCOperand &Op = MI->getOperand(OpNo + 1);
802       NegMnemo = Op.isImm() || Op.isDFPImm();
803     }
804     if (NegMnemo) {
805       O << "neg(";
806     } else {
807       O << '-';
808     }
809   }
810 
811   if (InputModifiers & SISrcMods::ABS)
812     O << '|';
813   printOperand(MI, OpNo + 1, STI, O);
814   if (InputModifiers & SISrcMods::ABS)
815     O << '|';
816 
817   if (NegMnemo) {
818     O << ')';
819   }
820 }
821 
822 void AMDGPUInstPrinter::printOperandAndIntInputMods(const MCInst *MI,
823                                                     unsigned OpNo,
824                                                     const MCSubtargetInfo &STI,
825                                                     raw_ostream &O) {
826   unsigned InputModifiers = MI->getOperand(OpNo).getImm();
827   if (InputModifiers & SISrcMods::SEXT)
828     O << "sext(";
829   printOperand(MI, OpNo + 1, STI, O);
830   if (InputModifiers & SISrcMods::SEXT)
831     O << ')';
832 
833   // Print default vcc/vcc_lo operand of VOP2b.
834   switch (MI->getOpcode()) {
835   default: break;
836 
837   case AMDGPU::V_CNDMASK_B32_sdwa_gfx10:
838   case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10:
839   case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10:
840   case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10:
841     if ((int)OpNo + 1 == AMDGPU::getNamedOperandIdx(MI->getOpcode(),
842                                                     AMDGPU::OpName::src1))
843       printDefaultVccOperand(OpNo == 0, STI, O);
844     break;
845   }
846 }
847 
848 void AMDGPUInstPrinter::printDPP8(const MCInst *MI, unsigned OpNo,
849                                   const MCSubtargetInfo &STI,
850                                   raw_ostream &O) {
851   if (!AMDGPU::isGFX10Plus(STI))
852     llvm_unreachable("dpp8 is not supported on ASICs earlier than GFX10");
853 
854   unsigned Imm = MI->getOperand(OpNo).getImm();
855   O << "dpp8:[" << formatDec(Imm & 0x7);
856   for (size_t i = 1; i < 8; ++i) {
857     O << ',' << formatDec((Imm >> (3 * i)) & 0x7);
858   }
859   O << ']';
860 }
861 
862 void AMDGPUInstPrinter::printDPPCtrl(const MCInst *MI, unsigned OpNo,
863                                      const MCSubtargetInfo &STI,
864                                      raw_ostream &O) {
865   using namespace AMDGPU::DPP;
866 
867   unsigned Imm = MI->getOperand(OpNo).getImm();
868   const MCInstrDesc &Desc = MII.get(MI->getOpcode());
869   int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
870                                            AMDGPU::OpName::src0);
871 
872   if (Src0Idx >= 0 &&
873       Desc.OpInfo[Src0Idx].RegClass == AMDGPU::VReg_64RegClassID &&
874       !AMDGPU::isLegal64BitDPPControl(Imm)) {
875     O << " /* 64 bit dpp only supports row_newbcast */";
876     return;
877   } else if (Imm <= DppCtrl::QUAD_PERM_LAST) {
878     O << "quad_perm:[";
879     O << formatDec(Imm & 0x3)         << ',';
880     O << formatDec((Imm & 0xc)  >> 2) << ',';
881     O << formatDec((Imm & 0x30) >> 4) << ',';
882     O << formatDec((Imm & 0xc0) >> 6) << ']';
883   } else if ((Imm >= DppCtrl::ROW_SHL_FIRST) &&
884              (Imm <= DppCtrl::ROW_SHL_LAST)) {
885     O << "row_shl:";
886     printU4ImmDecOperand(MI, OpNo, O);
887   } else if ((Imm >= DppCtrl::ROW_SHR_FIRST) &&
888              (Imm <= DppCtrl::ROW_SHR_LAST)) {
889     O << "row_shr:";
890     printU4ImmDecOperand(MI, OpNo, O);
891   } else if ((Imm >= DppCtrl::ROW_ROR_FIRST) &&
892              (Imm <= DppCtrl::ROW_ROR_LAST)) {
893     O << "row_ror:";
894     printU4ImmDecOperand(MI, OpNo, O);
895   } else if (Imm == DppCtrl::WAVE_SHL1) {
896     if (AMDGPU::isGFX10Plus(STI)) {
897       O << "/* wave_shl is not supported starting from GFX10 */";
898       return;
899     }
900     O << "wave_shl:1";
901   } else if (Imm == DppCtrl::WAVE_ROL1) {
902     if (AMDGPU::isGFX10Plus(STI)) {
903       O << "/* wave_rol is not supported starting from GFX10 */";
904       return;
905     }
906     O << "wave_rol:1";
907   } else if (Imm == DppCtrl::WAVE_SHR1) {
908     if (AMDGPU::isGFX10Plus(STI)) {
909       O << "/* wave_shr is not supported starting from GFX10 */";
910       return;
911     }
912     O << "wave_shr:1";
913   } else if (Imm == DppCtrl::WAVE_ROR1) {
914     if (AMDGPU::isGFX10Plus(STI)) {
915       O << "/* wave_ror is not supported starting from GFX10 */";
916       return;
917     }
918     O << "wave_ror:1";
919   } else if (Imm == DppCtrl::ROW_MIRROR) {
920     O << "row_mirror";
921   } else if (Imm == DppCtrl::ROW_HALF_MIRROR) {
922     O << "row_half_mirror";
923   } else if (Imm == DppCtrl::BCAST15) {
924     if (AMDGPU::isGFX10Plus(STI)) {
925       O << "/* row_bcast is not supported starting from GFX10 */";
926       return;
927     }
928     O << "row_bcast:15";
929   } else if (Imm == DppCtrl::BCAST31) {
930     if (AMDGPU::isGFX10Plus(STI)) {
931       O << "/* row_bcast is not supported starting from GFX10 */";
932       return;
933     }
934     O << "row_bcast:31";
935   } else if ((Imm >= DppCtrl::ROW_SHARE_FIRST) &&
936              (Imm <= DppCtrl::ROW_SHARE_LAST)) {
937     if (AMDGPU::isGFX90A(STI)) {
938       O << "row_newbcast:";
939     } else if (AMDGPU::isGFX10Plus(STI)) {
940       O << "row_share:";
941     } else {
942       O << " /* row_newbcast/row_share is not supported on ASICs earlier "
943            "than GFX90A/GFX10 */";
944       return;
945     }
946     printU4ImmDecOperand(MI, OpNo, O);
947   } else if ((Imm >= DppCtrl::ROW_XMASK_FIRST) &&
948              (Imm <= DppCtrl::ROW_XMASK_LAST)) {
949     if (!AMDGPU::isGFX10Plus(STI)) {
950       O << "/* row_xmask is not supported on ASICs earlier than GFX10 */";
951       return;
952     }
953     O << "row_xmask:";
954     printU4ImmDecOperand(MI, OpNo, O);
955   } else {
956     O << "/* Invalid dpp_ctrl value */";
957   }
958 }
959 
960 void AMDGPUInstPrinter::printRowMask(const MCInst *MI, unsigned OpNo,
961                                      const MCSubtargetInfo &STI,
962                                      raw_ostream &O) {
963   O << " row_mask:";
964   printU4ImmOperand(MI, OpNo, STI, O);
965 }
966 
967 void AMDGPUInstPrinter::printBankMask(const MCInst *MI, unsigned OpNo,
968                                       const MCSubtargetInfo &STI,
969                                       raw_ostream &O) {
970   O << " bank_mask:";
971   printU4ImmOperand(MI, OpNo, STI, O);
972 }
973 
974 void AMDGPUInstPrinter::printBoundCtrl(const MCInst *MI, unsigned OpNo,
975                                        const MCSubtargetInfo &STI,
976                                        raw_ostream &O) {
977   unsigned Imm = MI->getOperand(OpNo).getImm();
978   if (Imm) {
979     O << " bound_ctrl:1";
980   }
981 }
982 
983 void AMDGPUInstPrinter::printFI(const MCInst *MI, unsigned OpNo,
984                                 const MCSubtargetInfo &STI,
985                                 raw_ostream &O) {
986   using namespace llvm::AMDGPU::DPP;
987   unsigned Imm = MI->getOperand(OpNo).getImm();
988   if (Imm == DPP_FI_1 || Imm == DPP8_FI_1) {
989     O << " fi:1";
990   }
991 }
992 
993 void AMDGPUInstPrinter::printSDWASel(const MCInst *MI, unsigned OpNo,
994                                      raw_ostream &O) {
995   using namespace llvm::AMDGPU::SDWA;
996 
997   unsigned Imm = MI->getOperand(OpNo).getImm();
998   switch (Imm) {
999   case SdwaSel::BYTE_0: O << "BYTE_0"; break;
1000   case SdwaSel::BYTE_1: O << "BYTE_1"; break;
1001   case SdwaSel::BYTE_2: O << "BYTE_2"; break;
1002   case SdwaSel::BYTE_3: O << "BYTE_3"; break;
1003   case SdwaSel::WORD_0: O << "WORD_0"; break;
1004   case SdwaSel::WORD_1: O << "WORD_1"; break;
1005   case SdwaSel::DWORD: O << "DWORD"; break;
1006   default: llvm_unreachable("Invalid SDWA data select operand");
1007   }
1008 }
1009 
1010 void AMDGPUInstPrinter::printSDWADstSel(const MCInst *MI, unsigned OpNo,
1011                                         const MCSubtargetInfo &STI,
1012                                         raw_ostream &O) {
1013   O << "dst_sel:";
1014   printSDWASel(MI, OpNo, O);
1015 }
1016 
1017 void AMDGPUInstPrinter::printSDWASrc0Sel(const MCInst *MI, unsigned OpNo,
1018                                          const MCSubtargetInfo &STI,
1019                                          raw_ostream &O) {
1020   O << "src0_sel:";
1021   printSDWASel(MI, OpNo, O);
1022 }
1023 
1024 void AMDGPUInstPrinter::printSDWASrc1Sel(const MCInst *MI, unsigned OpNo,
1025                                          const MCSubtargetInfo &STI,
1026                                          raw_ostream &O) {
1027   O << "src1_sel:";
1028   printSDWASel(MI, OpNo, O);
1029 }
1030 
1031 void AMDGPUInstPrinter::printSDWADstUnused(const MCInst *MI, unsigned OpNo,
1032                                            const MCSubtargetInfo &STI,
1033                                            raw_ostream &O) {
1034   using namespace llvm::AMDGPU::SDWA;
1035 
1036   O << "dst_unused:";
1037   unsigned Imm = MI->getOperand(OpNo).getImm();
1038   switch (Imm) {
1039   case DstUnused::UNUSED_PAD: O << "UNUSED_PAD"; break;
1040   case DstUnused::UNUSED_SEXT: O << "UNUSED_SEXT"; break;
1041   case DstUnused::UNUSED_PRESERVE: O << "UNUSED_PRESERVE"; break;
1042   default: llvm_unreachable("Invalid SDWA dest_unused operand");
1043   }
1044 }
1045 
1046 void AMDGPUInstPrinter::printExpSrcN(const MCInst *MI, unsigned OpNo,
1047                                      const MCSubtargetInfo &STI, raw_ostream &O,
1048                                      unsigned N) {
1049   unsigned Opc = MI->getOpcode();
1050   int EnIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::en);
1051   unsigned En = MI->getOperand(EnIdx).getImm();
1052 
1053   int ComprIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::compr);
1054 
1055   // If compr is set, print as src0, src0, src1, src1
1056   if (MI->getOperand(ComprIdx).getImm())
1057     OpNo = OpNo - N + N / 2;
1058 
1059   if (En & (1 << N))
1060     printRegOperand(MI->getOperand(OpNo).getReg(), O, MRI);
1061   else
1062     O << "off";
1063 }
1064 
1065 void AMDGPUInstPrinter::printExpSrc0(const MCInst *MI, unsigned OpNo,
1066                                      const MCSubtargetInfo &STI,
1067                                      raw_ostream &O) {
1068   printExpSrcN(MI, OpNo, STI, O, 0);
1069 }
1070 
1071 void AMDGPUInstPrinter::printExpSrc1(const MCInst *MI, unsigned OpNo,
1072                                      const MCSubtargetInfo &STI,
1073                                      raw_ostream &O) {
1074   printExpSrcN(MI, OpNo, STI, O, 1);
1075 }
1076 
1077 void AMDGPUInstPrinter::printExpSrc2(const MCInst *MI, unsigned OpNo,
1078                                      const MCSubtargetInfo &STI,
1079                                      raw_ostream &O) {
1080   printExpSrcN(MI, OpNo, STI, O, 2);
1081 }
1082 
1083 void AMDGPUInstPrinter::printExpSrc3(const MCInst *MI, unsigned OpNo,
1084                                      const MCSubtargetInfo &STI,
1085                                      raw_ostream &O) {
1086   printExpSrcN(MI, OpNo, STI, O, 3);
1087 }
1088 
1089 void AMDGPUInstPrinter::printExpTgt(const MCInst *MI, unsigned OpNo,
1090                                     const MCSubtargetInfo &STI,
1091                                     raw_ostream &O) {
1092   using namespace llvm::AMDGPU::Exp;
1093 
1094   // This is really a 6 bit field.
1095   unsigned Id = MI->getOperand(OpNo).getImm() & ((1 << 6) - 1);
1096 
1097   int Index;
1098   StringRef TgtName;
1099   if (getTgtName(Id, TgtName, Index) && isSupportedTgtId(Id, STI)) {
1100     O << ' ' << TgtName;
1101     if (Index >= 0)
1102       O << Index;
1103   } else {
1104     O << " invalid_target_" << Id;
1105   }
1106 }
1107 
1108 static bool allOpsDefaultValue(const int* Ops, int NumOps, int Mod,
1109                                bool IsPacked, bool HasDstSel) {
1110   int DefaultValue = IsPacked && (Mod == SISrcMods::OP_SEL_1);
1111 
1112   for (int I = 0; I < NumOps; ++I) {
1113     if (!!(Ops[I] & Mod) != DefaultValue)
1114       return false;
1115   }
1116 
1117   if (HasDstSel && (Ops[0] & SISrcMods::DST_OP_SEL) != 0)
1118     return false;
1119 
1120   return true;
1121 }
1122 
1123 void AMDGPUInstPrinter::printPackedModifier(const MCInst *MI,
1124                                             StringRef Name,
1125                                             unsigned Mod,
1126                                             raw_ostream &O) {
1127   unsigned Opc = MI->getOpcode();
1128   int NumOps = 0;
1129   int Ops[3];
1130 
1131   for (int OpName : { AMDGPU::OpName::src0_modifiers,
1132                       AMDGPU::OpName::src1_modifiers,
1133                       AMDGPU::OpName::src2_modifiers }) {
1134     int Idx = AMDGPU::getNamedOperandIdx(Opc, OpName);
1135     if (Idx == -1)
1136       break;
1137 
1138     Ops[NumOps++] = MI->getOperand(Idx).getImm();
1139   }
1140 
1141   const bool HasDstSel =
1142     NumOps > 0 &&
1143     Mod == SISrcMods::OP_SEL_0 &&
1144     MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::VOP3_OPSEL;
1145 
1146   const bool IsPacked =
1147     MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::IsPacked;
1148 
1149   if (allOpsDefaultValue(Ops, NumOps, Mod, IsPacked, HasDstSel))
1150     return;
1151 
1152   O << Name;
1153   for (int I = 0; I < NumOps; ++I) {
1154     if (I != 0)
1155       O << ',';
1156 
1157     O << !!(Ops[I] & Mod);
1158   }
1159 
1160   if (HasDstSel) {
1161     O << ',' << !!(Ops[0] & SISrcMods::DST_OP_SEL);
1162   }
1163 
1164   O << ']';
1165 }
1166 
1167 void AMDGPUInstPrinter::printOpSel(const MCInst *MI, unsigned,
1168                                    const MCSubtargetInfo &STI,
1169                                    raw_ostream &O) {
1170   unsigned Opc = MI->getOpcode();
1171   if (Opc == AMDGPU::V_PERMLANE16_B32_gfx10 ||
1172       Opc == AMDGPU::V_PERMLANEX16_B32_gfx10) {
1173     auto FIN = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers);
1174     auto BCN = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers);
1175     unsigned FI = !!(MI->getOperand(FIN).getImm() & SISrcMods::OP_SEL_0);
1176     unsigned BC = !!(MI->getOperand(BCN).getImm() & SISrcMods::OP_SEL_0);
1177     if (FI || BC)
1178       O << " op_sel:[" << FI << ',' << BC << ']';
1179     return;
1180   }
1181 
1182   printPackedModifier(MI, " op_sel:[", SISrcMods::OP_SEL_0, O);
1183 }
1184 
1185 void AMDGPUInstPrinter::printOpSelHi(const MCInst *MI, unsigned OpNo,
1186                                      const MCSubtargetInfo &STI,
1187                                      raw_ostream &O) {
1188   printPackedModifier(MI, " op_sel_hi:[", SISrcMods::OP_SEL_1, O);
1189 }
1190 
1191 void AMDGPUInstPrinter::printNegLo(const MCInst *MI, unsigned OpNo,
1192                                    const MCSubtargetInfo &STI,
1193                                    raw_ostream &O) {
1194   printPackedModifier(MI, " neg_lo:[", SISrcMods::NEG, O);
1195 }
1196 
1197 void AMDGPUInstPrinter::printNegHi(const MCInst *MI, unsigned OpNo,
1198                                    const MCSubtargetInfo &STI,
1199                                    raw_ostream &O) {
1200   printPackedModifier(MI, " neg_hi:[", SISrcMods::NEG_HI, O);
1201 }
1202 
1203 void AMDGPUInstPrinter::printInterpSlot(const MCInst *MI, unsigned OpNum,
1204                                         const MCSubtargetInfo &STI,
1205                                         raw_ostream &O) {
1206   unsigned Imm = MI->getOperand(OpNum).getImm();
1207   switch (Imm) {
1208   case 0:
1209     O << "p10";
1210     break;
1211   case 1:
1212     O << "p20";
1213     break;
1214   case 2:
1215     O << "p0";
1216     break;
1217   default:
1218     O << "invalid_param_" << Imm;
1219   }
1220 }
1221 
1222 void AMDGPUInstPrinter::printInterpAttr(const MCInst *MI, unsigned OpNum,
1223                                         const MCSubtargetInfo &STI,
1224                                         raw_ostream &O) {
1225   unsigned Attr = MI->getOperand(OpNum).getImm();
1226   O << "attr" << Attr;
1227 }
1228 
1229 void AMDGPUInstPrinter::printInterpAttrChan(const MCInst *MI, unsigned OpNum,
1230                                         const MCSubtargetInfo &STI,
1231                                         raw_ostream &O) {
1232   unsigned Chan = MI->getOperand(OpNum).getImm();
1233   O << '.' << "xyzw"[Chan & 0x3];
1234 }
1235 
1236 void AMDGPUInstPrinter::printVGPRIndexMode(const MCInst *MI, unsigned OpNo,
1237                                            const MCSubtargetInfo &STI,
1238                                            raw_ostream &O) {
1239   using namespace llvm::AMDGPU::VGPRIndexMode;
1240   unsigned Val = MI->getOperand(OpNo).getImm();
1241 
1242   if ((Val & ~ENABLE_MASK) != 0) {
1243     O << formatHex(static_cast<uint64_t>(Val));
1244   } else {
1245     O << "gpr_idx(";
1246     bool NeedComma = false;
1247     for (unsigned ModeId = ID_MIN; ModeId <= ID_MAX; ++ModeId) {
1248       if (Val & (1 << ModeId)) {
1249         if (NeedComma)
1250           O << ',';
1251         O << IdSymbolic[ModeId];
1252         NeedComma = true;
1253       }
1254     }
1255     O << ')';
1256   }
1257 }
1258 
1259 void AMDGPUInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo,
1260                                         const MCSubtargetInfo &STI,
1261                                         raw_ostream &O) {
1262   printOperand(MI, OpNo, STI, O);
1263   O  << ", ";
1264   printOperand(MI, OpNo + 1, STI, O);
1265 }
1266 
1267 void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
1268                                    raw_ostream &O, StringRef Asm,
1269                                    StringRef Default) {
1270   const MCOperand &Op = MI->getOperand(OpNo);
1271   assert(Op.isImm());
1272   if (Op.getImm() == 1) {
1273     O << Asm;
1274   } else {
1275     O << Default;
1276   }
1277 }
1278 
1279 void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
1280                                    raw_ostream &O, char Asm) {
1281   const MCOperand &Op = MI->getOperand(OpNo);
1282   assert(Op.isImm());
1283   if (Op.getImm() == 1)
1284     O << Asm;
1285 }
1286 
1287 void AMDGPUInstPrinter::printHigh(const MCInst *MI, unsigned OpNo,
1288                                   const MCSubtargetInfo &STI,
1289                                   raw_ostream &O) {
1290   printNamedBit(MI, OpNo, O, "high");
1291 }
1292 
1293 void AMDGPUInstPrinter::printClampSI(const MCInst *MI, unsigned OpNo,
1294                                      const MCSubtargetInfo &STI,
1295                                      raw_ostream &O) {
1296   printNamedBit(MI, OpNo, O, "clamp");
1297 }
1298 
1299 void AMDGPUInstPrinter::printOModSI(const MCInst *MI, unsigned OpNo,
1300                                     const MCSubtargetInfo &STI,
1301                                     raw_ostream &O) {
1302   int Imm = MI->getOperand(OpNo).getImm();
1303   if (Imm == SIOutMods::MUL2)
1304     O << " mul:2";
1305   else if (Imm == SIOutMods::MUL4)
1306     O << " mul:4";
1307   else if (Imm == SIOutMods::DIV2)
1308     O << " div:2";
1309 }
1310 
1311 void AMDGPUInstPrinter::printSendMsg(const MCInst *MI, unsigned OpNo,
1312                                      const MCSubtargetInfo &STI,
1313                                      raw_ostream &O) {
1314   using namespace llvm::AMDGPU::SendMsg;
1315 
1316   const unsigned Imm16 = MI->getOperand(OpNo).getImm();
1317 
1318   uint16_t MsgId;
1319   uint16_t OpId;
1320   uint16_t StreamId;
1321   decodeMsg(Imm16, MsgId, OpId, StreamId, STI);
1322 
1323   StringRef MsgName = getMsgName(MsgId, STI);
1324 
1325   if (!MsgName.empty() && isValidMsgOp(MsgId, OpId, STI) &&
1326       isValidMsgStream(MsgId, OpId, StreamId, STI)) {
1327     O << "sendmsg(" << MsgName;
1328     if (msgRequiresOp(MsgId, STI)) {
1329       O << ", " << getMsgOpName(MsgId, OpId, STI);
1330       if (msgSupportsStream(MsgId, OpId, STI)) {
1331         O << ", " << StreamId;
1332       }
1333     }
1334     O << ')';
1335   } else if (encodeMsg(MsgId, OpId, StreamId) == Imm16) {
1336     O << "sendmsg(" << MsgId << ", " << OpId << ", " << StreamId << ')';
1337   } else {
1338     O << Imm16; // Unknown imm16 code.
1339   }
1340 }
1341 
1342 static void printSwizzleBitmask(const uint16_t AndMask,
1343                                 const uint16_t OrMask,
1344                                 const uint16_t XorMask,
1345                                 raw_ostream &O) {
1346   using namespace llvm::AMDGPU::Swizzle;
1347 
1348   uint16_t Probe0 = ((0            & AndMask) | OrMask) ^ XorMask;
1349   uint16_t Probe1 = ((BITMASK_MASK & AndMask) | OrMask) ^ XorMask;
1350 
1351   O << "\"";
1352 
1353   for (unsigned Mask = 1 << (BITMASK_WIDTH - 1); Mask > 0; Mask >>= 1) {
1354     uint16_t p0 = Probe0 & Mask;
1355     uint16_t p1 = Probe1 & Mask;
1356 
1357     if (p0 == p1) {
1358       if (p0 == 0) {
1359         O << "0";
1360       } else {
1361         O << "1";
1362       }
1363     } else {
1364       if (p0 == 0) {
1365         O << "p";
1366       } else {
1367         O << "i";
1368       }
1369     }
1370   }
1371 
1372   O << "\"";
1373 }
1374 
1375 void AMDGPUInstPrinter::printSwizzle(const MCInst *MI, unsigned OpNo,
1376                                      const MCSubtargetInfo &STI,
1377                                      raw_ostream &O) {
1378   using namespace llvm::AMDGPU::Swizzle;
1379 
1380   uint16_t Imm = MI->getOperand(OpNo).getImm();
1381   if (Imm == 0) {
1382     return;
1383   }
1384 
1385   O << " offset:";
1386 
1387   if ((Imm & QUAD_PERM_ENC_MASK) == QUAD_PERM_ENC) {
1388 
1389     O << "swizzle(" << IdSymbolic[ID_QUAD_PERM];
1390     for (unsigned I = 0; I < LANE_NUM; ++I) {
1391       O << ",";
1392       O << formatDec(Imm & LANE_MASK);
1393       Imm >>= LANE_SHIFT;
1394     }
1395     O << ")";
1396 
1397   } else if ((Imm & BITMASK_PERM_ENC_MASK) == BITMASK_PERM_ENC) {
1398 
1399     uint16_t AndMask = (Imm >> BITMASK_AND_SHIFT) & BITMASK_MASK;
1400     uint16_t OrMask  = (Imm >> BITMASK_OR_SHIFT)  & BITMASK_MASK;
1401     uint16_t XorMask = (Imm >> BITMASK_XOR_SHIFT) & BITMASK_MASK;
1402 
1403     if (AndMask == BITMASK_MAX &&
1404         OrMask == 0 &&
1405         countPopulation(XorMask) == 1) {
1406 
1407       O << "swizzle(" << IdSymbolic[ID_SWAP];
1408       O << ",";
1409       O << formatDec(XorMask);
1410       O << ")";
1411 
1412     } else if (AndMask == BITMASK_MAX &&
1413                OrMask == 0 && XorMask > 0 &&
1414                isPowerOf2_64(XorMask + 1)) {
1415 
1416       O << "swizzle(" << IdSymbolic[ID_REVERSE];
1417       O << ",";
1418       O << formatDec(XorMask + 1);
1419       O << ")";
1420 
1421     } else {
1422 
1423       uint16_t GroupSize = BITMASK_MAX - AndMask + 1;
1424       if (GroupSize > 1 &&
1425           isPowerOf2_64(GroupSize) &&
1426           OrMask < GroupSize &&
1427           XorMask == 0) {
1428 
1429         O << "swizzle(" << IdSymbolic[ID_BROADCAST];
1430         O << ",";
1431         O << formatDec(GroupSize);
1432         O << ",";
1433         O << formatDec(OrMask);
1434         O << ")";
1435 
1436       } else {
1437         O << "swizzle(" << IdSymbolic[ID_BITMASK_PERM];
1438         O << ",";
1439         printSwizzleBitmask(AndMask, OrMask, XorMask, O);
1440         O << ")";
1441       }
1442     }
1443   } else {
1444     printU16ImmDecOperand(MI, OpNo, O);
1445   }
1446 }
1447 
1448 void AMDGPUInstPrinter::printWaitFlag(const MCInst *MI, unsigned OpNo,
1449                                       const MCSubtargetInfo &STI,
1450                                       raw_ostream &O) {
1451   AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(STI.getCPU());
1452 
1453   unsigned SImm16 = MI->getOperand(OpNo).getImm();
1454   unsigned Vmcnt, Expcnt, Lgkmcnt;
1455   decodeWaitcnt(ISA, SImm16, Vmcnt, Expcnt, Lgkmcnt);
1456 
1457   bool IsDefaultVmcnt = Vmcnt == getVmcntBitMask(ISA);
1458   bool IsDefaultExpcnt = Expcnt == getExpcntBitMask(ISA);
1459   bool IsDefaultLgkmcnt = Lgkmcnt == getLgkmcntBitMask(ISA);
1460   bool PrintAll = IsDefaultVmcnt && IsDefaultExpcnt && IsDefaultLgkmcnt;
1461 
1462   bool NeedSpace = false;
1463 
1464   if (!IsDefaultVmcnt || PrintAll) {
1465     O << "vmcnt(" << Vmcnt << ')';
1466     NeedSpace = true;
1467   }
1468 
1469   if (!IsDefaultExpcnt || PrintAll) {
1470     if (NeedSpace)
1471       O << ' ';
1472     O << "expcnt(" << Expcnt << ')';
1473     NeedSpace = true;
1474   }
1475 
1476   if (!IsDefaultLgkmcnt || PrintAll) {
1477     if (NeedSpace)
1478       O << ' ';
1479     O << "lgkmcnt(" << Lgkmcnt << ')';
1480   }
1481 }
1482 
1483 void AMDGPUInstPrinter::printDepCtr(const MCInst *MI, unsigned OpNo,
1484                                     const MCSubtargetInfo &STI,
1485                                     raw_ostream &O) {
1486   using namespace llvm::AMDGPU::DepCtr;
1487 
1488   uint64_t Imm16 = MI->getOperand(OpNo).getImm() & 0xffff;
1489 
1490   bool HasNonDefaultVal = false;
1491   if (isSymbolicDepCtrEncoding(Imm16, HasNonDefaultVal, STI)) {
1492     int Id = 0;
1493     StringRef Name;
1494     unsigned Val;
1495     bool IsDefault;
1496     bool NeedSpace = false;
1497     while (decodeDepCtr(Imm16, Id, Name, Val, IsDefault, STI)) {
1498       if (!IsDefault || !HasNonDefaultVal) {
1499         if (NeedSpace)
1500           O << ' ';
1501         O << Name << '(' << Val << ')';
1502         NeedSpace = true;
1503       }
1504     }
1505   } else {
1506     O << formatHex(Imm16);
1507   }
1508 }
1509 
1510 void AMDGPUInstPrinter::printDelayFlag(const MCInst *MI, unsigned OpNo,
1511                                        const MCSubtargetInfo &STI,
1512                                        raw_ostream &O) {
1513   const char *BadInstId = "/* invalid instid value */";
1514   static const std::array<const char *, 12> InstIds = {
1515       "NO_DEP",        "VALU_DEP_1",    "VALU_DEP_2",
1516       "VALU_DEP_3",    "VALU_DEP_4",    "TRANS32_DEP_1",
1517       "TRANS32_DEP_2", "TRANS32_DEP_3", "FMA_ACCUM_CYCLE_1",
1518       "SALU_CYCLE_1",  "SALU_CYCLE_2",  "SALU_CYCLE_3"};
1519 
1520   const char *BadInstSkip = "/* invalid instskip value */";
1521   static const std::array<const char *, 6> InstSkips = {
1522       "SAME", "NEXT", "SKIP_1", "SKIP_2", "SKIP_3", "SKIP_4"};
1523 
1524   unsigned SImm16 = MI->getOperand(OpNo).getImm();
1525   const char *Prefix = "";
1526 
1527   unsigned Value = SImm16 & 0xF;
1528   if (Value) {
1529     const char *Name = Value < InstIds.size() ? InstIds[Value] : BadInstId;
1530     O << Prefix << "instid0(" << Name << ')';
1531     Prefix = " | ";
1532   }
1533 
1534   Value = (SImm16 >> 4) & 7;
1535   if (Value) {
1536     const char *Name =
1537         Value < InstSkips.size() ? InstSkips[Value] : BadInstSkip;
1538     O << Prefix << "instskip(" << Name << ')';
1539     Prefix = " | ";
1540   }
1541 
1542   Value = (SImm16 >> 7) & 0xF;
1543   if (Value) {
1544     const char *Name = Value < InstIds.size() ? InstIds[Value] : BadInstId;
1545     O << Prefix << "instid1(" << Name << ')';
1546     Prefix = " | ";
1547   }
1548 
1549   if (!*Prefix)
1550     O << "0";
1551 }
1552 
1553 void AMDGPUInstPrinter::printHwreg(const MCInst *MI, unsigned OpNo,
1554                                    const MCSubtargetInfo &STI, raw_ostream &O) {
1555   unsigned Id;
1556   unsigned Offset;
1557   unsigned Width;
1558 
1559   using namespace llvm::AMDGPU::Hwreg;
1560   unsigned Val = MI->getOperand(OpNo).getImm();
1561   decodeHwreg(Val, Id, Offset, Width);
1562   StringRef HwRegName = getHwreg(Id, STI);
1563 
1564   O << "hwreg(";
1565   if (!HwRegName.empty()) {
1566     O << HwRegName;
1567   } else {
1568     O << Id;
1569   }
1570   if (Width != WIDTH_DEFAULT_ || Offset != OFFSET_DEFAULT_) {
1571     O << ", " << Offset << ", " << Width;
1572   }
1573   O << ')';
1574 }
1575 
1576 void AMDGPUInstPrinter::printEndpgm(const MCInst *MI, unsigned OpNo,
1577                                     const MCSubtargetInfo &STI,
1578                                     raw_ostream &O) {
1579   uint16_t Imm = MI->getOperand(OpNo).getImm();
1580   if (Imm == 0) {
1581     return;
1582   }
1583 
1584   O << ' ' << formatDec(Imm);
1585 }
1586 
1587 #include "AMDGPUGenAsmWriter.inc"
1588