1 //===-- AMDGPUInstPrinter.cpp - AMDGPU MC Inst -> ASM ---------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 // \file
8 //===----------------------------------------------------------------------===//
9 
10 #include "AMDGPUInstPrinter.h"
11 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
12 #include "SIDefines.h"
13 #include "SIRegisterInfo.h"
14 #include "Utils/AMDGPUAsmUtils.h"
15 #include "Utils/AMDGPUBaseInfo.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCInstrDesc.h"
19 #include "llvm/MC/MCInstrInfo.h"
20 #include "llvm/MC/MCSubtargetInfo.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/TargetParser.h"
23 
24 using namespace llvm;
25 using namespace llvm::AMDGPU;
26 
27 static cl::opt<bool> Keep16BitSuffixes(
28   "amdgpu-keep-16-bit-reg-suffixes",
29   cl::desc("Keep .l and .h suffixes in asm for debugging purposes"),
30   cl::init(false),
31   cl::ReallyHidden);
32 
33 void AMDGPUInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
34   // FIXME: The current implementation of
35   // AsmParser::parseRegisterOrRegisterNumber in MC implies we either emit this
36   // as an integer or we provide a name which represents a physical register.
37   // For CFI instructions we really want to emit a name for the DWARF register
38   // instead, because there may be multiple DWARF registers corresponding to a
39   // single physical register. One case where this problem manifests is with
40   // wave32/wave64 where using the physical register name is ambiguous: if we
41   // write e.g. `.cfi_undefined v0` we lose information about the wavefront
42   // size which we need to encode the register in the final DWARF. Ideally we
43   // would extend MC to support parsing DWARF register names so we could do
44   // something like `.cfi_undefined dwarf_wave32_v0`. For now we just live with
45   // non-pretty DWARF register names in assembly text.
46   OS << RegNo;
47 }
48 
49 void AMDGPUInstPrinter::printInst(const MCInst *MI, uint64_t Address,
50                                   StringRef Annot, const MCSubtargetInfo &STI,
51                                   raw_ostream &OS) {
52   OS.flush();
53   printInstruction(MI, Address, STI, OS);
54   printAnnotation(OS, Annot);
55 }
56 
57 void AMDGPUInstPrinter::printU4ImmOperand(const MCInst *MI, unsigned OpNo,
58                                           const MCSubtargetInfo &STI,
59                                           raw_ostream &O) {
60   O << formatHex(MI->getOperand(OpNo).getImm() & 0xf);
61 }
62 
63 void AMDGPUInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo,
64                                           raw_ostream &O) {
65   O << formatHex(MI->getOperand(OpNo).getImm() & 0xff);
66 }
67 
68 void AMDGPUInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
69                                            const MCSubtargetInfo &STI,
70                                            raw_ostream &O) {
71   // It's possible to end up with a 32-bit literal used with a 16-bit operand
72   // with ignored high bits. Print as 32-bit anyway in that case.
73   int64_t Imm = MI->getOperand(OpNo).getImm();
74   if (isInt<16>(Imm) || isUInt<16>(Imm))
75     O << formatHex(static_cast<uint64_t>(Imm & 0xffff));
76   else
77     printU32ImmOperand(MI, OpNo, STI, O);
78 }
79 
80 void AMDGPUInstPrinter::printU4ImmDecOperand(const MCInst *MI, unsigned OpNo,
81                                              raw_ostream &O) {
82   O << formatDec(MI->getOperand(OpNo).getImm() & 0xf);
83 }
84 
85 void AMDGPUInstPrinter::printU8ImmDecOperand(const MCInst *MI, unsigned OpNo,
86                                              raw_ostream &O) {
87   O << formatDec(MI->getOperand(OpNo).getImm() & 0xff);
88 }
89 
90 void AMDGPUInstPrinter::printU16ImmDecOperand(const MCInst *MI, unsigned OpNo,
91                                               raw_ostream &O) {
92   O << formatDec(MI->getOperand(OpNo).getImm() & 0xffff);
93 }
94 
95 void AMDGPUInstPrinter::printU32ImmOperand(const MCInst *MI, unsigned OpNo,
96                                            const MCSubtargetInfo &STI,
97                                            raw_ostream &O) {
98   O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff);
99 }
100 
101 void AMDGPUInstPrinter::printNamedBit(const MCInst *MI, unsigned OpNo,
102                                       raw_ostream &O, StringRef BitName) {
103   if (MI->getOperand(OpNo).getImm()) {
104     O << ' ' << BitName;
105   }
106 }
107 
108 void AMDGPUInstPrinter::printOffen(const MCInst *MI, unsigned OpNo,
109                                    raw_ostream &O) {
110   printNamedBit(MI, OpNo, O, "offen");
111 }
112 
113 void AMDGPUInstPrinter::printIdxen(const MCInst *MI, unsigned OpNo,
114                                    raw_ostream &O) {
115   printNamedBit(MI, OpNo, O, "idxen");
116 }
117 
118 void AMDGPUInstPrinter::printAddr64(const MCInst *MI, unsigned OpNo,
119                                     raw_ostream &O) {
120   printNamedBit(MI, OpNo, O, "addr64");
121 }
122 
123 void AMDGPUInstPrinter::printMBUFOffset(const MCInst *MI, unsigned OpNo,
124                                         raw_ostream &O) {
125   if (MI->getOperand(OpNo).getImm()) {
126     O << " offset:";
127     printU16ImmDecOperand(MI, OpNo, O);
128   }
129 }
130 
131 void AMDGPUInstPrinter::printOffset(const MCInst *MI, unsigned OpNo,
132                                     const MCSubtargetInfo &STI,
133                                     raw_ostream &O) {
134   uint16_t Imm = MI->getOperand(OpNo).getImm();
135   if (Imm != 0) {
136     O << " offset:";
137     printU16ImmDecOperand(MI, OpNo, O);
138   }
139 }
140 
141 void AMDGPUInstPrinter::printFlatOffset(const MCInst *MI, unsigned OpNo,
142                                         const MCSubtargetInfo &STI,
143                                         raw_ostream &O) {
144   uint16_t Imm = MI->getOperand(OpNo).getImm();
145   if (Imm != 0) {
146     O << " offset:";
147 
148     const MCInstrDesc &Desc = MII.get(MI->getOpcode());
149     bool IsFlatSeg = !(Desc.TSFlags &
150         (SIInstrFlags::IsFlatGlobal | SIInstrFlags::IsFlatScratch));
151 
152     if (IsFlatSeg) { // Unsigned offset
153       printU16ImmDecOperand(MI, OpNo, O);
154     } else {         // Signed offset
155       if (AMDGPU::isGFX10Plus(STI)) {
156         O << formatDec(SignExtend32<12>(MI->getOperand(OpNo).getImm()));
157       } else {
158         O << formatDec(SignExtend32<13>(MI->getOperand(OpNo).getImm()));
159       }
160     }
161   }
162 }
163 
164 void AMDGPUInstPrinter::printOffset0(const MCInst *MI, unsigned OpNo,
165                                      const MCSubtargetInfo &STI,
166                                      raw_ostream &O) {
167   if (MI->getOperand(OpNo).getImm()) {
168     O << " offset0:";
169     printU8ImmDecOperand(MI, OpNo, O);
170   }
171 }
172 
173 void AMDGPUInstPrinter::printOffset1(const MCInst *MI, unsigned OpNo,
174                                      const MCSubtargetInfo &STI,
175                                      raw_ostream &O) {
176   if (MI->getOperand(OpNo).getImm()) {
177     O << " offset1:";
178     printU8ImmDecOperand(MI, OpNo, O);
179   }
180 }
181 
182 void AMDGPUInstPrinter::printSMRDOffset8(const MCInst *MI, unsigned OpNo,
183                                         const MCSubtargetInfo &STI,
184                                         raw_ostream &O) {
185   printU32ImmOperand(MI, OpNo, STI, O);
186 }
187 
188 void AMDGPUInstPrinter::printSMEMOffset(const MCInst *MI, unsigned OpNo,
189                                         const MCSubtargetInfo &STI,
190                                         raw_ostream &O) {
191   O << formatHex(MI->getOperand(OpNo).getImm());
192 }
193 
194 void AMDGPUInstPrinter::printSMRDLiteralOffset(const MCInst *MI, unsigned OpNo,
195                                                const MCSubtargetInfo &STI,
196                                                raw_ostream &O) {
197   printU32ImmOperand(MI, OpNo, STI, O);
198 }
199 
200 void AMDGPUInstPrinter::printGDS(const MCInst *MI, unsigned OpNo,
201                                  const MCSubtargetInfo &STI, raw_ostream &O) {
202   printNamedBit(MI, OpNo, O, "gds");
203 }
204 
205 void AMDGPUInstPrinter::printCPol(const MCInst *MI, unsigned OpNo,
206                                   const MCSubtargetInfo &STI, raw_ostream &O) {
207   auto Imm = MI->getOperand(OpNo).getImm();
208   if (Imm & CPol::GLC)
209     O << " glc";
210   if (Imm & CPol::SLC)
211     O << " slc";
212   if ((Imm & CPol::DLC) && AMDGPU::isGFX10Plus(STI))
213     O << " dlc";
214   if ((Imm & CPol::SCC) && AMDGPU::isGFX90A(STI))
215     O << " scc";
216   if (Imm & ~CPol::ALL)
217     O << " /* unexpected cache policy bit */";
218 }
219 
220 void AMDGPUInstPrinter::printSWZ(const MCInst *MI, unsigned OpNo,
221                                  const MCSubtargetInfo &STI, raw_ostream &O) {
222 }
223 
224 void AMDGPUInstPrinter::printTFE(const MCInst *MI, unsigned OpNo,
225                                  const MCSubtargetInfo &STI, raw_ostream &O) {
226   printNamedBit(MI, OpNo, O, "tfe");
227 }
228 
229 void AMDGPUInstPrinter::printDMask(const MCInst *MI, unsigned OpNo,
230                                    const MCSubtargetInfo &STI, raw_ostream &O) {
231   if (MI->getOperand(OpNo).getImm()) {
232     O << " dmask:";
233     printU16ImmOperand(MI, OpNo, STI, O);
234   }
235 }
236 
237 void AMDGPUInstPrinter::printDim(const MCInst *MI, unsigned OpNo,
238                                  const MCSubtargetInfo &STI, raw_ostream &O) {
239   unsigned Dim = MI->getOperand(OpNo).getImm();
240   O << " dim:SQ_RSRC_IMG_";
241 
242   const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfoByEncoding(Dim);
243   if (DimInfo)
244     O << DimInfo->AsmSuffix;
245   else
246     O << Dim;
247 }
248 
249 void AMDGPUInstPrinter::printUNorm(const MCInst *MI, unsigned OpNo,
250                                    const MCSubtargetInfo &STI, raw_ostream &O) {
251   printNamedBit(MI, OpNo, O, "unorm");
252 }
253 
254 void AMDGPUInstPrinter::printDA(const MCInst *MI, unsigned OpNo,
255                                 const MCSubtargetInfo &STI, raw_ostream &O) {
256   printNamedBit(MI, OpNo, O, "da");
257 }
258 
259 void AMDGPUInstPrinter::printR128A16(const MCInst *MI, unsigned OpNo,
260                                   const MCSubtargetInfo &STI, raw_ostream &O) {
261   if (STI.hasFeature(AMDGPU::FeatureR128A16))
262     printNamedBit(MI, OpNo, O, "a16");
263   else
264     printNamedBit(MI, OpNo, O, "r128");
265 }
266 
267 void AMDGPUInstPrinter::printGFX10A16(const MCInst *MI, unsigned OpNo,
268                                   const MCSubtargetInfo &STI, raw_ostream &O) {
269   printNamedBit(MI, OpNo, O, "a16");
270 }
271 
272 void AMDGPUInstPrinter::printLWE(const MCInst *MI, unsigned OpNo,
273                                  const MCSubtargetInfo &STI, raw_ostream &O) {
274   printNamedBit(MI, OpNo, O, "lwe");
275 }
276 
277 void AMDGPUInstPrinter::printD16(const MCInst *MI, unsigned OpNo,
278                                  const MCSubtargetInfo &STI, raw_ostream &O) {
279   printNamedBit(MI, OpNo, O, "d16");
280 }
281 
282 void AMDGPUInstPrinter::printExpCompr(const MCInst *MI, unsigned OpNo,
283                                       const MCSubtargetInfo &STI,
284                                       raw_ostream &O) {
285   printNamedBit(MI, OpNo, O, "compr");
286 }
287 
288 void AMDGPUInstPrinter::printExpVM(const MCInst *MI, unsigned OpNo,
289                                    const MCSubtargetInfo &STI,
290                                    raw_ostream &O) {
291   printNamedBit(MI, OpNo, O, "vm");
292 }
293 
294 void AMDGPUInstPrinter::printFORMAT(const MCInst *MI, unsigned OpNo,
295                                     const MCSubtargetInfo &STI,
296                                     raw_ostream &O) {
297 }
298 
299 void AMDGPUInstPrinter::printSymbolicFormat(const MCInst *MI,
300                                             const MCSubtargetInfo &STI,
301                                             raw_ostream &O) {
302   using namespace llvm::AMDGPU::MTBUFFormat;
303 
304   int OpNo =
305     AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::format);
306   assert(OpNo != -1);
307 
308   unsigned Val = MI->getOperand(OpNo).getImm();
309   if (AMDGPU::isGFX10Plus(STI)) {
310     if (Val == UFMT_DEFAULT)
311       return;
312     if (isValidUnifiedFormat(Val)) {
313       O << " format:[" << getUnifiedFormatName(Val) << ']';
314     } else {
315       O << " format:" << Val;
316     }
317   } else {
318     if (Val == DFMT_NFMT_DEFAULT)
319       return;
320     if (isValidDfmtNfmt(Val, STI)) {
321       unsigned Dfmt;
322       unsigned Nfmt;
323       decodeDfmtNfmt(Val, Dfmt, Nfmt);
324       O << " format:[";
325       if (Dfmt != DFMT_DEFAULT) {
326         O << getDfmtName(Dfmt);
327         if (Nfmt != NFMT_DEFAULT) {
328           O << ',';
329         }
330       }
331       if (Nfmt != NFMT_DEFAULT) {
332         O << getNfmtName(Nfmt, STI);
333       }
334       O << ']';
335     } else {
336       O << " format:" << Val;
337     }
338   }
339 }
340 
341 void AMDGPUInstPrinter::printRegOperand(unsigned RegNo, raw_ostream &O,
342                                         const MCRegisterInfo &MRI) {
343 #if !defined(NDEBUG)
344   switch (RegNo) {
345   case AMDGPU::FP_REG:
346   case AMDGPU::SP_REG:
347   case AMDGPU::PRIVATE_RSRC_REG:
348     llvm_unreachable("pseudo-register should not ever be emitted");
349   case AMDGPU::SCC:
350     llvm_unreachable("pseudo scc should not ever be emitted");
351   default:
352     break;
353   }
354 #endif
355 
356   StringRef RegName(getRegisterName(RegNo));
357   if (!Keep16BitSuffixes)
358     if (!RegName.consume_back(".l"))
359       RegName.consume_back(".h");
360 
361   O << RegName;
362 }
363 
364 void AMDGPUInstPrinter::printVOPDst(const MCInst *MI, unsigned OpNo,
365                                     const MCSubtargetInfo &STI, raw_ostream &O) {
366   if (OpNo == 0) {
367     if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::VOP3)
368       O << "_e64 ";
369     else if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::DPP)
370       O << "_dpp ";
371     else if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::SDWA)
372       O << "_sdwa ";
373     else
374       O << "_e32 ";
375   }
376 
377   printOperand(MI, OpNo, STI, O);
378 
379   // Print default vcc/vcc_lo operand.
380   switch (MI->getOpcode()) {
381   default: break;
382 
383   case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10:
384   case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10:
385   case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10:
386   case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10:
387   case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10:
388   case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10:
389   case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10:
390   case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10:
391   case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10:
392   case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10:
393   case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10:
394   case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10:
395     printDefaultVccOperand(1, STI, O);
396     break;
397   }
398 }
399 
400 void AMDGPUInstPrinter::printVINTRPDst(const MCInst *MI, unsigned OpNo,
401                                        const MCSubtargetInfo &STI, raw_ostream &O) {
402   if (AMDGPU::isSI(STI) || AMDGPU::isCI(STI))
403     O << " ";
404   else
405     O << "_e32 ";
406 
407   printOperand(MI, OpNo, STI, O);
408 }
409 
410 void AMDGPUInstPrinter::printImmediateInt16(uint32_t Imm,
411                                             const MCSubtargetInfo &STI,
412                                             raw_ostream &O) {
413   int16_t SImm = static_cast<int16_t>(Imm);
414   if (isInlinableIntLiteral(SImm)) {
415     O << SImm;
416   } else {
417     uint64_t Imm16 = static_cast<uint16_t>(Imm);
418     O << formatHex(Imm16);
419   }
420 }
421 
422 void AMDGPUInstPrinter::printImmediate16(uint32_t Imm,
423                                          const MCSubtargetInfo &STI,
424                                          raw_ostream &O) {
425   int16_t SImm = static_cast<int16_t>(Imm);
426   if (isInlinableIntLiteral(SImm)) {
427     O << SImm;
428     return;
429   }
430 
431   if (Imm == 0x3C00)
432     O<< "1.0";
433   else if (Imm == 0xBC00)
434     O<< "-1.0";
435   else if (Imm == 0x3800)
436     O<< "0.5";
437   else if (Imm == 0xB800)
438     O<< "-0.5";
439   else if (Imm == 0x4000)
440     O<< "2.0";
441   else if (Imm == 0xC000)
442     O<< "-2.0";
443   else if (Imm == 0x4400)
444     O<< "4.0";
445   else if (Imm == 0xC400)
446     O<< "-4.0";
447   else if (Imm == 0x3118 &&
448            STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]) {
449     O << "0.15915494";
450   } else {
451     uint64_t Imm16 = static_cast<uint16_t>(Imm);
452     O << formatHex(Imm16);
453   }
454 }
455 
456 void AMDGPUInstPrinter::printImmediateV216(uint32_t Imm,
457                                            const MCSubtargetInfo &STI,
458                                            raw_ostream &O) {
459   uint16_t Lo16 = static_cast<uint16_t>(Imm);
460   printImmediate16(Lo16, STI, O);
461 }
462 
463 void AMDGPUInstPrinter::printImmediate32(uint32_t Imm,
464                                          const MCSubtargetInfo &STI,
465                                          raw_ostream &O) {
466   int32_t SImm = static_cast<int32_t>(Imm);
467   if (SImm >= -16 && SImm <= 64) {
468     O << SImm;
469     return;
470   }
471 
472   if (Imm == FloatToBits(0.0f))
473     O << "0.0";
474   else if (Imm == FloatToBits(1.0f))
475     O << "1.0";
476   else if (Imm == FloatToBits(-1.0f))
477     O << "-1.0";
478   else if (Imm == FloatToBits(0.5f))
479     O << "0.5";
480   else if (Imm == FloatToBits(-0.5f))
481     O << "-0.5";
482   else if (Imm == FloatToBits(2.0f))
483     O << "2.0";
484   else if (Imm == FloatToBits(-2.0f))
485     O << "-2.0";
486   else if (Imm == FloatToBits(4.0f))
487     O << "4.0";
488   else if (Imm == FloatToBits(-4.0f))
489     O << "-4.0";
490   else if (Imm == 0x3e22f983 &&
491            STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
492     O << "0.15915494";
493   else
494     O << formatHex(static_cast<uint64_t>(Imm));
495 }
496 
497 void AMDGPUInstPrinter::printImmediate64(uint64_t Imm,
498                                          const MCSubtargetInfo &STI,
499                                          raw_ostream &O) {
500   int64_t SImm = static_cast<int64_t>(Imm);
501   if (SImm >= -16 && SImm <= 64) {
502     O << SImm;
503     return;
504   }
505 
506   if (Imm == DoubleToBits(0.0))
507     O << "0.0";
508   else if (Imm == DoubleToBits(1.0))
509     O << "1.0";
510   else if (Imm == DoubleToBits(-1.0))
511     O << "-1.0";
512   else if (Imm == DoubleToBits(0.5))
513     O << "0.5";
514   else if (Imm == DoubleToBits(-0.5))
515     O << "-0.5";
516   else if (Imm == DoubleToBits(2.0))
517     O << "2.0";
518   else if (Imm == DoubleToBits(-2.0))
519     O << "-2.0";
520   else if (Imm == DoubleToBits(4.0))
521     O << "4.0";
522   else if (Imm == DoubleToBits(-4.0))
523     O << "-4.0";
524   else if (Imm == 0x3fc45f306dc9c882 &&
525            STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
526     O << "0.15915494309189532";
527   else {
528     assert(isUInt<32>(Imm) || Imm == 0x3fc45f306dc9c882);
529 
530     // In rare situations, we will have a 32-bit literal in a 64-bit
531     // operand. This is technically allowed for the encoding of s_mov_b64.
532     O << formatHex(static_cast<uint64_t>(Imm));
533   }
534 }
535 
536 void AMDGPUInstPrinter::printBLGP(const MCInst *MI, unsigned OpNo,
537                                   const MCSubtargetInfo &STI,
538                                   raw_ostream &O) {
539   unsigned Imm = MI->getOperand(OpNo).getImm();
540   if (!Imm)
541     return;
542 
543   O << " blgp:" << Imm;
544 }
545 
546 void AMDGPUInstPrinter::printCBSZ(const MCInst *MI, unsigned OpNo,
547                                   const MCSubtargetInfo &STI,
548                                   raw_ostream &O) {
549   unsigned Imm = MI->getOperand(OpNo).getImm();
550   if (!Imm)
551     return;
552 
553   O << " cbsz:" << Imm;
554 }
555 
556 void AMDGPUInstPrinter::printABID(const MCInst *MI, unsigned OpNo,
557                                   const MCSubtargetInfo &STI,
558                                   raw_ostream &O) {
559   unsigned Imm = MI->getOperand(OpNo).getImm();
560   if (!Imm)
561     return;
562 
563   O << " abid:" << Imm;
564 }
565 
566 void AMDGPUInstPrinter::printDefaultVccOperand(unsigned OpNo,
567                                                const MCSubtargetInfo &STI,
568                                                raw_ostream &O) {
569   if (OpNo > 0)
570     O << ", ";
571   printRegOperand(STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ?
572                   AMDGPU::VCC : AMDGPU::VCC_LO, O, MRI);
573   if (OpNo == 0)
574     O << ", ";
575 }
576 
577 void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
578                                      const MCSubtargetInfo &STI,
579                                      raw_ostream &O) {
580   // Print default vcc/vcc_lo operand of VOPC.
581   const MCInstrDesc &Desc = MII.get(MI->getOpcode());
582   if (OpNo == 0 && (Desc.TSFlags & SIInstrFlags::VOPC) &&
583       (Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC) ||
584        Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC_LO)))
585     printDefaultVccOperand(OpNo, STI, O);
586 
587   if (OpNo >= MI->getNumOperands()) {
588     O << "/*Missing OP" << OpNo << "*/";
589     return;
590   }
591 
592   const MCOperand &Op = MI->getOperand(OpNo);
593   if (Op.isReg()) {
594     printRegOperand(Op.getReg(), O, MRI);
595   } else if (Op.isImm()) {
596     const uint8_t OpTy = Desc.OpInfo[OpNo].OperandType;
597     switch (OpTy) {
598     case AMDGPU::OPERAND_REG_IMM_INT32:
599     case AMDGPU::OPERAND_REG_IMM_FP32:
600     case AMDGPU::OPERAND_REG_INLINE_C_INT32:
601     case AMDGPU::OPERAND_REG_INLINE_C_FP32:
602     case AMDGPU::OPERAND_REG_INLINE_AC_INT32:
603     case AMDGPU::OPERAND_REG_INLINE_AC_FP32:
604     case AMDGPU::OPERAND_REG_IMM_V2INT32:
605     case AMDGPU::OPERAND_REG_IMM_V2FP32:
606     case AMDGPU::OPERAND_REG_INLINE_C_V2INT32:
607     case AMDGPU::OPERAND_REG_INLINE_C_V2FP32:
608     case MCOI::OPERAND_IMMEDIATE:
609       printImmediate32(Op.getImm(), STI, O);
610       break;
611     case AMDGPU::OPERAND_REG_IMM_INT64:
612     case AMDGPU::OPERAND_REG_IMM_FP64:
613     case AMDGPU::OPERAND_REG_INLINE_C_INT64:
614     case AMDGPU::OPERAND_REG_INLINE_C_FP64:
615     case AMDGPU::OPERAND_REG_INLINE_AC_FP64:
616       printImmediate64(Op.getImm(), STI, O);
617       break;
618     case AMDGPU::OPERAND_REG_INLINE_C_INT16:
619     case AMDGPU::OPERAND_REG_INLINE_AC_INT16:
620     case AMDGPU::OPERAND_REG_IMM_INT16:
621       printImmediateInt16(Op.getImm(), STI, O);
622       break;
623     case AMDGPU::OPERAND_REG_INLINE_C_FP16:
624     case AMDGPU::OPERAND_REG_INLINE_AC_FP16:
625     case AMDGPU::OPERAND_REG_IMM_FP16:
626       printImmediate16(Op.getImm(), STI, O);
627       break;
628     case AMDGPU::OPERAND_REG_IMM_V2INT16:
629     case AMDGPU::OPERAND_REG_IMM_V2FP16:
630       if (!isUInt<16>(Op.getImm()) &&
631           STI.getFeatureBits()[AMDGPU::FeatureVOP3Literal]) {
632         printImmediate32(Op.getImm(), STI, O);
633         break;
634       }
635 
636       //  Deal with 16-bit FP inline immediates not working.
637       if (OpTy == AMDGPU::OPERAND_REG_IMM_V2FP16) {
638         printImmediate16(static_cast<uint16_t>(Op.getImm()), STI, O);
639         break;
640       }
641       LLVM_FALLTHROUGH;
642     case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
643     case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:
644       printImmediateInt16(static_cast<uint16_t>(Op.getImm()), STI, O);
645       break;
646     case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
647     case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16:
648       printImmediateV216(Op.getImm(), STI, O);
649       break;
650     case MCOI::OPERAND_UNKNOWN:
651     case MCOI::OPERAND_PCREL:
652       O << formatDec(Op.getImm());
653       break;
654     case MCOI::OPERAND_REGISTER:
655       // FIXME: This should be removed and handled somewhere else. Seems to come
656       // from a disassembler bug.
657       O << "/*invalid immediate*/";
658       break;
659     default:
660       // We hit this for the immediate instruction bits that don't yet have a
661       // custom printer.
662       llvm_unreachable("unexpected immediate operand type");
663     }
664   } else if (Op.isDFPImm()) {
665     double Value = bit_cast<double>(Op.getDFPImm());
666     // We special case 0.0 because otherwise it will be printed as an integer.
667     if (Value == 0.0)
668       O << "0.0";
669     else {
670       const MCInstrDesc &Desc = MII.get(MI->getOpcode());
671       int RCID = Desc.OpInfo[OpNo].RegClass;
672       unsigned RCBits = AMDGPU::getRegBitWidth(MRI.getRegClass(RCID));
673       if (RCBits == 32)
674         printImmediate32(FloatToBits(Value), STI, O);
675       else if (RCBits == 64)
676         printImmediate64(DoubleToBits(Value), STI, O);
677       else
678         llvm_unreachable("Invalid register class size");
679     }
680   } else if (Op.isExpr()) {
681     const MCExpr *Exp = Op.getExpr();
682     Exp->print(O, &MAI);
683   } else {
684     O << "/*INV_OP*/";
685   }
686 
687   // Print default vcc/vcc_lo operand of v_cndmask_b32_e32.
688   switch (MI->getOpcode()) {
689   default: break;
690 
691   case AMDGPU::V_CNDMASK_B32_e32_gfx10:
692   case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10:
693   case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10:
694   case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10:
695   case AMDGPU::V_CNDMASK_B32_dpp_gfx10:
696   case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10:
697   case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10:
698   case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10:
699   case AMDGPU::V_CNDMASK_B32_dpp8_gfx10:
700   case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10:
701   case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10:
702   case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10:
703 
704   case AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7:
705   case AMDGPU::V_CNDMASK_B32_e32_vi:
706     if ((int)OpNo == AMDGPU::getNamedOperandIdx(MI->getOpcode(),
707                                                 AMDGPU::OpName::src1))
708       printDefaultVccOperand(OpNo, STI, O);
709     break;
710   }
711 
712   if (Desc.TSFlags & SIInstrFlags::MTBUF) {
713     int SOffsetIdx =
714       AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::soffset);
715     assert(SOffsetIdx != -1);
716     if ((int)OpNo == SOffsetIdx)
717       printSymbolicFormat(MI, STI, O);
718   }
719 }
720 
721 void AMDGPUInstPrinter::printOperandAndFPInputMods(const MCInst *MI,
722                                                    unsigned OpNo,
723                                                    const MCSubtargetInfo &STI,
724                                                    raw_ostream &O) {
725   unsigned InputModifiers = MI->getOperand(OpNo).getImm();
726 
727   // Use 'neg(...)' instead of '-' to avoid ambiguity.
728   // This is important for integer literals because
729   // -1 is not the same value as neg(1).
730   bool NegMnemo = false;
731 
732   if (InputModifiers & SISrcMods::NEG) {
733     if (OpNo + 1 < MI->getNumOperands() &&
734         (InputModifiers & SISrcMods::ABS) == 0) {
735       const MCOperand &Op = MI->getOperand(OpNo + 1);
736       NegMnemo = Op.isImm() || Op.isDFPImm();
737     }
738     if (NegMnemo) {
739       O << "neg(";
740     } else {
741       O << '-';
742     }
743   }
744 
745   if (InputModifiers & SISrcMods::ABS)
746     O << '|';
747   printOperand(MI, OpNo + 1, STI, O);
748   if (InputModifiers & SISrcMods::ABS)
749     O << '|';
750 
751   if (NegMnemo) {
752     O << ')';
753   }
754 }
755 
756 void AMDGPUInstPrinter::printOperandAndIntInputMods(const MCInst *MI,
757                                                     unsigned OpNo,
758                                                     const MCSubtargetInfo &STI,
759                                                     raw_ostream &O) {
760   unsigned InputModifiers = MI->getOperand(OpNo).getImm();
761   if (InputModifiers & SISrcMods::SEXT)
762     O << "sext(";
763   printOperand(MI, OpNo + 1, STI, O);
764   if (InputModifiers & SISrcMods::SEXT)
765     O << ')';
766 
767   // Print default vcc/vcc_lo operand of VOP2b.
768   switch (MI->getOpcode()) {
769   default: break;
770 
771   case AMDGPU::V_CNDMASK_B32_sdwa_gfx10:
772   case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10:
773   case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10:
774   case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10:
775     if ((int)OpNo + 1 == AMDGPU::getNamedOperandIdx(MI->getOpcode(),
776                                                     AMDGPU::OpName::src1))
777       printDefaultVccOperand(OpNo, STI, O);
778     break;
779   }
780 }
781 
782 void AMDGPUInstPrinter::printDPP8(const MCInst *MI, unsigned OpNo,
783                                   const MCSubtargetInfo &STI,
784                                   raw_ostream &O) {
785   if (!AMDGPU::isGFX10Plus(STI))
786     llvm_unreachable("dpp8 is not supported on ASICs earlier than GFX10");
787 
788   unsigned Imm = MI->getOperand(OpNo).getImm();
789   O << "dpp8:[" << formatDec(Imm & 0x7);
790   for (size_t i = 1; i < 8; ++i) {
791     O << ',' << formatDec((Imm >> (3 * i)) & 0x7);
792   }
793   O << ']';
794 }
795 
796 void AMDGPUInstPrinter::printDPPCtrl(const MCInst *MI, unsigned OpNo,
797                                      const MCSubtargetInfo &STI,
798                                      raw_ostream &O) {
799   using namespace AMDGPU::DPP;
800 
801   unsigned Imm = MI->getOperand(OpNo).getImm();
802   const MCInstrDesc &Desc = MII.get(MI->getOpcode());
803   int DstIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
804                                           AMDGPU::OpName::vdst);
805   int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
806                                            AMDGPU::OpName::src0);
807 
808   if (((DstIdx >= 0 &&
809         Desc.OpInfo[DstIdx].RegClass == AMDGPU::VReg_64RegClassID) ||
810       ((Src0Idx >= 0 &&
811         Desc.OpInfo[Src0Idx].RegClass == AMDGPU::VReg_64RegClassID))) &&
812       !AMDGPU::isLegal64BitDPPControl(Imm)) {
813     O << " /* 64 bit dpp only supports row_newbcast */";
814     return;
815   } else if (Imm <= DppCtrl::QUAD_PERM_LAST) {
816     O << "quad_perm:[";
817     O << formatDec(Imm & 0x3)         << ',';
818     O << formatDec((Imm & 0xc)  >> 2) << ',';
819     O << formatDec((Imm & 0x30) >> 4) << ',';
820     O << formatDec((Imm & 0xc0) >> 6) << ']';
821   } else if ((Imm >= DppCtrl::ROW_SHL_FIRST) &&
822              (Imm <= DppCtrl::ROW_SHL_LAST)) {
823     O << "row_shl:";
824     printU4ImmDecOperand(MI, OpNo, O);
825   } else if ((Imm >= DppCtrl::ROW_SHR_FIRST) &&
826              (Imm <= DppCtrl::ROW_SHR_LAST)) {
827     O << "row_shr:";
828     printU4ImmDecOperand(MI, OpNo, O);
829   } else if ((Imm >= DppCtrl::ROW_ROR_FIRST) &&
830              (Imm <= DppCtrl::ROW_ROR_LAST)) {
831     O << "row_ror:";
832     printU4ImmDecOperand(MI, OpNo, O);
833   } else if (Imm == DppCtrl::WAVE_SHL1) {
834     if (AMDGPU::isGFX10Plus(STI)) {
835       O << "/* wave_shl is not supported starting from GFX10 */";
836       return;
837     }
838     O << "wave_shl:1";
839   } else if (Imm == DppCtrl::WAVE_ROL1) {
840     if (AMDGPU::isGFX10Plus(STI)) {
841       O << "/* wave_rol is not supported starting from GFX10 */";
842       return;
843     }
844     O << "wave_rol:1";
845   } else if (Imm == DppCtrl::WAVE_SHR1) {
846     if (AMDGPU::isGFX10Plus(STI)) {
847       O << "/* wave_shr is not supported starting from GFX10 */";
848       return;
849     }
850     O << "wave_shr:1";
851   } else if (Imm == DppCtrl::WAVE_ROR1) {
852     if (AMDGPU::isGFX10Plus(STI)) {
853       O << "/* wave_ror is not supported starting from GFX10 */";
854       return;
855     }
856     O << "wave_ror:1";
857   } else if (Imm == DppCtrl::ROW_MIRROR) {
858     O << "row_mirror";
859   } else if (Imm == DppCtrl::ROW_HALF_MIRROR) {
860     O << "row_half_mirror";
861   } else if (Imm == DppCtrl::BCAST15) {
862     if (AMDGPU::isGFX10Plus(STI)) {
863       O << "/* row_bcast is not supported starting from GFX10 */";
864       return;
865     }
866     O << "row_bcast:15";
867   } else if (Imm == DppCtrl::BCAST31) {
868     if (AMDGPU::isGFX10Plus(STI)) {
869       O << "/* row_bcast is not supported starting from GFX10 */";
870       return;
871     }
872     O << "row_bcast:31";
873   } else if ((Imm >= DppCtrl::ROW_SHARE_FIRST) &&
874              (Imm <= DppCtrl::ROW_SHARE_LAST)) {
875     if (AMDGPU::isGFX90A(STI)) {
876       O << " row_newbcast:";
877     } else if (AMDGPU::isGFX10Plus(STI)) {
878       O << "row_share:";
879     } else {
880       O << " /* row_newbcast/row_share is not supported on ASICs earlier "
881            "than GFX90A/GFX10 */";
882       return;
883     }
884     printU4ImmDecOperand(MI, OpNo, O);
885   } else if ((Imm >= DppCtrl::ROW_XMASK_FIRST) &&
886              (Imm <= DppCtrl::ROW_XMASK_LAST)) {
887     if (!AMDGPU::isGFX10Plus(STI)) {
888       O << "/* row_xmask is not supported on ASICs earlier than GFX10 */";
889       return;
890     }
891     O << "row_xmask:";
892     printU4ImmDecOperand(MI, OpNo, O);
893   } else {
894     O << "/* Invalid dpp_ctrl value */";
895   }
896 }
897 
898 void AMDGPUInstPrinter::printRowMask(const MCInst *MI, unsigned OpNo,
899                                      const MCSubtargetInfo &STI,
900                                      raw_ostream &O) {
901   O << " row_mask:";
902   printU4ImmOperand(MI, OpNo, STI, O);
903 }
904 
905 void AMDGPUInstPrinter::printBankMask(const MCInst *MI, unsigned OpNo,
906                                       const MCSubtargetInfo &STI,
907                                       raw_ostream &O) {
908   O << " bank_mask:";
909   printU4ImmOperand(MI, OpNo, STI, O);
910 }
911 
912 void AMDGPUInstPrinter::printBoundCtrl(const MCInst *MI, unsigned OpNo,
913                                        const MCSubtargetInfo &STI,
914                                        raw_ostream &O) {
915   unsigned Imm = MI->getOperand(OpNo).getImm();
916   if (Imm) {
917     O << " bound_ctrl:1";
918   }
919 }
920 
921 void AMDGPUInstPrinter::printFI(const MCInst *MI, unsigned OpNo,
922                                 const MCSubtargetInfo &STI,
923                                 raw_ostream &O) {
924   using namespace llvm::AMDGPU::DPP;
925   unsigned Imm = MI->getOperand(OpNo).getImm();
926   if (Imm == DPP_FI_1 || Imm == DPP8_FI_1) {
927     O << " fi:1";
928   }
929 }
930 
931 void AMDGPUInstPrinter::printSDWASel(const MCInst *MI, unsigned OpNo,
932                                      raw_ostream &O) {
933   using namespace llvm::AMDGPU::SDWA;
934 
935   unsigned Imm = MI->getOperand(OpNo).getImm();
936   switch (Imm) {
937   case SdwaSel::BYTE_0: O << "BYTE_0"; break;
938   case SdwaSel::BYTE_1: O << "BYTE_1"; break;
939   case SdwaSel::BYTE_2: O << "BYTE_2"; break;
940   case SdwaSel::BYTE_3: O << "BYTE_3"; break;
941   case SdwaSel::WORD_0: O << "WORD_0"; break;
942   case SdwaSel::WORD_1: O << "WORD_1"; break;
943   case SdwaSel::DWORD: O << "DWORD"; break;
944   default: llvm_unreachable("Invalid SDWA data select operand");
945   }
946 }
947 
948 void AMDGPUInstPrinter::printSDWADstSel(const MCInst *MI, unsigned OpNo,
949                                         const MCSubtargetInfo &STI,
950                                         raw_ostream &O) {
951   O << "dst_sel:";
952   printSDWASel(MI, OpNo, O);
953 }
954 
955 void AMDGPUInstPrinter::printSDWASrc0Sel(const MCInst *MI, unsigned OpNo,
956                                          const MCSubtargetInfo &STI,
957                                          raw_ostream &O) {
958   O << "src0_sel:";
959   printSDWASel(MI, OpNo, O);
960 }
961 
962 void AMDGPUInstPrinter::printSDWASrc1Sel(const MCInst *MI, unsigned OpNo,
963                                          const MCSubtargetInfo &STI,
964                                          raw_ostream &O) {
965   O << "src1_sel:";
966   printSDWASel(MI, OpNo, O);
967 }
968 
969 void AMDGPUInstPrinter::printSDWADstUnused(const MCInst *MI, unsigned OpNo,
970                                            const MCSubtargetInfo &STI,
971                                            raw_ostream &O) {
972   using namespace llvm::AMDGPU::SDWA;
973 
974   O << "dst_unused:";
975   unsigned Imm = MI->getOperand(OpNo).getImm();
976   switch (Imm) {
977   case DstUnused::UNUSED_PAD: O << "UNUSED_PAD"; break;
978   case DstUnused::UNUSED_SEXT: O << "UNUSED_SEXT"; break;
979   case DstUnused::UNUSED_PRESERVE: O << "UNUSED_PRESERVE"; break;
980   default: llvm_unreachable("Invalid SDWA dest_unused operand");
981   }
982 }
983 
984 void AMDGPUInstPrinter::printExpSrcN(const MCInst *MI, unsigned OpNo,
985                                      const MCSubtargetInfo &STI, raw_ostream &O,
986                                      unsigned N) {
987   unsigned Opc = MI->getOpcode();
988   int EnIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::en);
989   unsigned En = MI->getOperand(EnIdx).getImm();
990 
991   int ComprIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::compr);
992 
993   // If compr is set, print as src0, src0, src1, src1
994   if (MI->getOperand(ComprIdx).getImm())
995     OpNo = OpNo - N + N / 2;
996 
997   if (En & (1 << N))
998     printRegOperand(MI->getOperand(OpNo).getReg(), O, MRI);
999   else
1000     O << "off";
1001 }
1002 
1003 void AMDGPUInstPrinter::printExpSrc0(const MCInst *MI, unsigned OpNo,
1004                                      const MCSubtargetInfo &STI,
1005                                      raw_ostream &O) {
1006   printExpSrcN(MI, OpNo, STI, O, 0);
1007 }
1008 
1009 void AMDGPUInstPrinter::printExpSrc1(const MCInst *MI, unsigned OpNo,
1010                                      const MCSubtargetInfo &STI,
1011                                      raw_ostream &O) {
1012   printExpSrcN(MI, OpNo, STI, O, 1);
1013 }
1014 
1015 void AMDGPUInstPrinter::printExpSrc2(const MCInst *MI, unsigned OpNo,
1016                                      const MCSubtargetInfo &STI,
1017                                      raw_ostream &O) {
1018   printExpSrcN(MI, OpNo, STI, O, 2);
1019 }
1020 
1021 void AMDGPUInstPrinter::printExpSrc3(const MCInst *MI, unsigned OpNo,
1022                                      const MCSubtargetInfo &STI,
1023                                      raw_ostream &O) {
1024   printExpSrcN(MI, OpNo, STI, O, 3);
1025 }
1026 
1027 void AMDGPUInstPrinter::printExpTgt(const MCInst *MI, unsigned OpNo,
1028                                     const MCSubtargetInfo &STI,
1029                                     raw_ostream &O) {
1030   using namespace llvm::AMDGPU::Exp;
1031 
1032   // This is really a 6 bit field.
1033   unsigned Id = MI->getOperand(OpNo).getImm() & ((1 << 6) - 1);
1034 
1035   int Index;
1036   StringRef TgtName;
1037   if (getTgtName(Id, TgtName, Index) && isSupportedTgtId(Id, STI)) {
1038     O << ' ' << TgtName;
1039     if (Index >= 0)
1040       O << Index;
1041   } else {
1042     O << " invalid_target_" << Id;
1043   }
1044 }
1045 
1046 static bool allOpsDefaultValue(const int* Ops, int NumOps, int Mod,
1047                                bool IsPacked, bool HasDstSel) {
1048   int DefaultValue = IsPacked && (Mod == SISrcMods::OP_SEL_1);
1049 
1050   for (int I = 0; I < NumOps; ++I) {
1051     if (!!(Ops[I] & Mod) != DefaultValue)
1052       return false;
1053   }
1054 
1055   if (HasDstSel && (Ops[0] & SISrcMods::DST_OP_SEL) != 0)
1056     return false;
1057 
1058   return true;
1059 }
1060 
1061 void AMDGPUInstPrinter::printPackedModifier(const MCInst *MI,
1062                                             StringRef Name,
1063                                             unsigned Mod,
1064                                             raw_ostream &O) {
1065   unsigned Opc = MI->getOpcode();
1066   int NumOps = 0;
1067   int Ops[3];
1068 
1069   for (int OpName : { AMDGPU::OpName::src0_modifiers,
1070                       AMDGPU::OpName::src1_modifiers,
1071                       AMDGPU::OpName::src2_modifiers }) {
1072     int Idx = AMDGPU::getNamedOperandIdx(Opc, OpName);
1073     if (Idx == -1)
1074       break;
1075 
1076     Ops[NumOps++] = MI->getOperand(Idx).getImm();
1077   }
1078 
1079   const bool HasDstSel =
1080     NumOps > 0 &&
1081     Mod == SISrcMods::OP_SEL_0 &&
1082     MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::VOP3_OPSEL;
1083 
1084   const bool IsPacked =
1085     MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::IsPacked;
1086 
1087   if (allOpsDefaultValue(Ops, NumOps, Mod, IsPacked, HasDstSel))
1088     return;
1089 
1090   O << Name;
1091   for (int I = 0; I < NumOps; ++I) {
1092     if (I != 0)
1093       O << ',';
1094 
1095     O << !!(Ops[I] & Mod);
1096   }
1097 
1098   if (HasDstSel) {
1099     O << ',' << !!(Ops[0] & SISrcMods::DST_OP_SEL);
1100   }
1101 
1102   O << ']';
1103 }
1104 
1105 void AMDGPUInstPrinter::printOpSel(const MCInst *MI, unsigned,
1106                                    const MCSubtargetInfo &STI,
1107                                    raw_ostream &O) {
1108   unsigned Opc = MI->getOpcode();
1109   if (Opc == AMDGPU::V_PERMLANE16_B32_gfx10 ||
1110       Opc == AMDGPU::V_PERMLANEX16_B32_gfx10) {
1111     auto FIN = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers);
1112     auto BCN = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers);
1113     unsigned FI = !!(MI->getOperand(FIN).getImm() & SISrcMods::OP_SEL_0);
1114     unsigned BC = !!(MI->getOperand(BCN).getImm() & SISrcMods::OP_SEL_0);
1115     if (FI || BC)
1116       O << " op_sel:[" << FI << ',' << BC << ']';
1117     return;
1118   }
1119 
1120   printPackedModifier(MI, " op_sel:[", SISrcMods::OP_SEL_0, O);
1121 }
1122 
1123 void AMDGPUInstPrinter::printOpSelHi(const MCInst *MI, unsigned OpNo,
1124                                      const MCSubtargetInfo &STI,
1125                                      raw_ostream &O) {
1126   printPackedModifier(MI, " op_sel_hi:[", SISrcMods::OP_SEL_1, O);
1127 }
1128 
1129 void AMDGPUInstPrinter::printNegLo(const MCInst *MI, unsigned OpNo,
1130                                    const MCSubtargetInfo &STI,
1131                                    raw_ostream &O) {
1132   printPackedModifier(MI, " neg_lo:[", SISrcMods::NEG, O);
1133 }
1134 
1135 void AMDGPUInstPrinter::printNegHi(const MCInst *MI, unsigned OpNo,
1136                                    const MCSubtargetInfo &STI,
1137                                    raw_ostream &O) {
1138   printPackedModifier(MI, " neg_hi:[", SISrcMods::NEG_HI, O);
1139 }
1140 
1141 void AMDGPUInstPrinter::printInterpSlot(const MCInst *MI, unsigned OpNum,
1142                                         const MCSubtargetInfo &STI,
1143                                         raw_ostream &O) {
1144   unsigned Imm = MI->getOperand(OpNum).getImm();
1145   switch (Imm) {
1146   case 0:
1147     O << "p10";
1148     break;
1149   case 1:
1150     O << "p20";
1151     break;
1152   case 2:
1153     O << "p0";
1154     break;
1155   default:
1156     O << "invalid_param_" << Imm;
1157   }
1158 }
1159 
1160 void AMDGPUInstPrinter::printInterpAttr(const MCInst *MI, unsigned OpNum,
1161                                         const MCSubtargetInfo &STI,
1162                                         raw_ostream &O) {
1163   unsigned Attr = MI->getOperand(OpNum).getImm();
1164   O << "attr" << Attr;
1165 }
1166 
1167 void AMDGPUInstPrinter::printInterpAttrChan(const MCInst *MI, unsigned OpNum,
1168                                         const MCSubtargetInfo &STI,
1169                                         raw_ostream &O) {
1170   unsigned Chan = MI->getOperand(OpNum).getImm();
1171   O << '.' << "xyzw"[Chan & 0x3];
1172 }
1173 
1174 void AMDGPUInstPrinter::printVGPRIndexMode(const MCInst *MI, unsigned OpNo,
1175                                            const MCSubtargetInfo &STI,
1176                                            raw_ostream &O) {
1177   using namespace llvm::AMDGPU::VGPRIndexMode;
1178   unsigned Val = MI->getOperand(OpNo).getImm();
1179 
1180   if ((Val & ~ENABLE_MASK) != 0) {
1181     O << formatHex(static_cast<uint64_t>(Val));
1182   } else {
1183     O << "gpr_idx(";
1184     bool NeedComma = false;
1185     for (unsigned ModeId = ID_MIN; ModeId <= ID_MAX; ++ModeId) {
1186       if (Val & (1 << ModeId)) {
1187         if (NeedComma)
1188           O << ',';
1189         O << IdSymbolic[ModeId];
1190         NeedComma = true;
1191       }
1192     }
1193     O << ')';
1194   }
1195 }
1196 
1197 void AMDGPUInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo,
1198                                         const MCSubtargetInfo &STI,
1199                                         raw_ostream &O) {
1200   printOperand(MI, OpNo, STI, O);
1201   O  << ", ";
1202   printOperand(MI, OpNo + 1, STI, O);
1203 }
1204 
1205 void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
1206                                    raw_ostream &O, StringRef Asm,
1207                                    StringRef Default) {
1208   const MCOperand &Op = MI->getOperand(OpNo);
1209   assert(Op.isImm());
1210   if (Op.getImm() == 1) {
1211     O << Asm;
1212   } else {
1213     O << Default;
1214   }
1215 }
1216 
1217 void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
1218                                    raw_ostream &O, char Asm) {
1219   const MCOperand &Op = MI->getOperand(OpNo);
1220   assert(Op.isImm());
1221   if (Op.getImm() == 1)
1222     O << Asm;
1223 }
1224 
1225 void AMDGPUInstPrinter::printHigh(const MCInst *MI, unsigned OpNo,
1226                                   const MCSubtargetInfo &STI,
1227                                   raw_ostream &O) {
1228   printNamedBit(MI, OpNo, O, "high");
1229 }
1230 
1231 void AMDGPUInstPrinter::printClampSI(const MCInst *MI, unsigned OpNo,
1232                                      const MCSubtargetInfo &STI,
1233                                      raw_ostream &O) {
1234   printNamedBit(MI, OpNo, O, "clamp");
1235 }
1236 
1237 void AMDGPUInstPrinter::printOModSI(const MCInst *MI, unsigned OpNo,
1238                                     const MCSubtargetInfo &STI,
1239                                     raw_ostream &O) {
1240   int Imm = MI->getOperand(OpNo).getImm();
1241   if (Imm == SIOutMods::MUL2)
1242     O << " mul:2";
1243   else if (Imm == SIOutMods::MUL4)
1244     O << " mul:4";
1245   else if (Imm == SIOutMods::DIV2)
1246     O << " div:2";
1247 }
1248 
1249 void AMDGPUInstPrinter::printSendMsg(const MCInst *MI, unsigned OpNo,
1250                                      const MCSubtargetInfo &STI,
1251                                      raw_ostream &O) {
1252   using namespace llvm::AMDGPU::SendMsg;
1253 
1254   const unsigned Imm16 = MI->getOperand(OpNo).getImm();
1255 
1256   uint16_t MsgId;
1257   uint16_t OpId;
1258   uint16_t StreamId;
1259   decodeMsg(Imm16, MsgId, OpId, StreamId);
1260 
1261   if (isValidMsgId(MsgId, STI) &&
1262       isValidMsgOp(MsgId, OpId, STI) &&
1263       isValidMsgStream(MsgId, OpId, StreamId, STI)) {
1264     O << "sendmsg(" << getMsgName(MsgId);
1265     if (msgRequiresOp(MsgId)) {
1266       O << ", " << getMsgOpName(MsgId, OpId);
1267       if (msgSupportsStream(MsgId, OpId)) {
1268         O << ", " << StreamId;
1269       }
1270     }
1271     O << ')';
1272   } else if (encodeMsg(MsgId, OpId, StreamId) == Imm16) {
1273     O << "sendmsg(" << MsgId << ", " << OpId << ", " << StreamId << ')';
1274   } else {
1275     O << Imm16; // Unknown imm16 code.
1276   }
1277 }
1278 
1279 static void printSwizzleBitmask(const uint16_t AndMask,
1280                                 const uint16_t OrMask,
1281                                 const uint16_t XorMask,
1282                                 raw_ostream &O) {
1283   using namespace llvm::AMDGPU::Swizzle;
1284 
1285   uint16_t Probe0 = ((0            & AndMask) | OrMask) ^ XorMask;
1286   uint16_t Probe1 = ((BITMASK_MASK & AndMask) | OrMask) ^ XorMask;
1287 
1288   O << "\"";
1289 
1290   for (unsigned Mask = 1 << (BITMASK_WIDTH - 1); Mask > 0; Mask >>= 1) {
1291     uint16_t p0 = Probe0 & Mask;
1292     uint16_t p1 = Probe1 & Mask;
1293 
1294     if (p0 == p1) {
1295       if (p0 == 0) {
1296         O << "0";
1297       } else {
1298         O << "1";
1299       }
1300     } else {
1301       if (p0 == 0) {
1302         O << "p";
1303       } else {
1304         O << "i";
1305       }
1306     }
1307   }
1308 
1309   O << "\"";
1310 }
1311 
1312 void AMDGPUInstPrinter::printSwizzle(const MCInst *MI, unsigned OpNo,
1313                                      const MCSubtargetInfo &STI,
1314                                      raw_ostream &O) {
1315   using namespace llvm::AMDGPU::Swizzle;
1316 
1317   uint16_t Imm = MI->getOperand(OpNo).getImm();
1318   if (Imm == 0) {
1319     return;
1320   }
1321 
1322   O << " offset:";
1323 
1324   if ((Imm & QUAD_PERM_ENC_MASK) == QUAD_PERM_ENC) {
1325 
1326     O << "swizzle(" << IdSymbolic[ID_QUAD_PERM];
1327     for (unsigned I = 0; I < LANE_NUM; ++I) {
1328       O << ",";
1329       O << formatDec(Imm & LANE_MASK);
1330       Imm >>= LANE_SHIFT;
1331     }
1332     O << ")";
1333 
1334   } else if ((Imm & BITMASK_PERM_ENC_MASK) == BITMASK_PERM_ENC) {
1335 
1336     uint16_t AndMask = (Imm >> BITMASK_AND_SHIFT) & BITMASK_MASK;
1337     uint16_t OrMask  = (Imm >> BITMASK_OR_SHIFT)  & BITMASK_MASK;
1338     uint16_t XorMask = (Imm >> BITMASK_XOR_SHIFT) & BITMASK_MASK;
1339 
1340     if (AndMask == BITMASK_MAX &&
1341         OrMask == 0 &&
1342         countPopulation(XorMask) == 1) {
1343 
1344       O << "swizzle(" << IdSymbolic[ID_SWAP];
1345       O << ",";
1346       O << formatDec(XorMask);
1347       O << ")";
1348 
1349     } else if (AndMask == BITMASK_MAX &&
1350                OrMask == 0 && XorMask > 0 &&
1351                isPowerOf2_64(XorMask + 1)) {
1352 
1353       O << "swizzle(" << IdSymbolic[ID_REVERSE];
1354       O << ",";
1355       O << formatDec(XorMask + 1);
1356       O << ")";
1357 
1358     } else {
1359 
1360       uint16_t GroupSize = BITMASK_MAX - AndMask + 1;
1361       if (GroupSize > 1 &&
1362           isPowerOf2_64(GroupSize) &&
1363           OrMask < GroupSize &&
1364           XorMask == 0) {
1365 
1366         O << "swizzle(" << IdSymbolic[ID_BROADCAST];
1367         O << ",";
1368         O << formatDec(GroupSize);
1369         O << ",";
1370         O << formatDec(OrMask);
1371         O << ")";
1372 
1373       } else {
1374         O << "swizzle(" << IdSymbolic[ID_BITMASK_PERM];
1375         O << ",";
1376         printSwizzleBitmask(AndMask, OrMask, XorMask, O);
1377         O << ")";
1378       }
1379     }
1380   } else {
1381     printU16ImmDecOperand(MI, OpNo, O);
1382   }
1383 }
1384 
1385 void AMDGPUInstPrinter::printWaitFlag(const MCInst *MI, unsigned OpNo,
1386                                       const MCSubtargetInfo &STI,
1387                                       raw_ostream &O) {
1388   AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(STI.getCPU());
1389 
1390   unsigned SImm16 = MI->getOperand(OpNo).getImm();
1391   unsigned Vmcnt, Expcnt, Lgkmcnt;
1392   decodeWaitcnt(ISA, SImm16, Vmcnt, Expcnt, Lgkmcnt);
1393 
1394   bool NeedSpace = false;
1395 
1396   if (Vmcnt != getVmcntBitMask(ISA)) {
1397     O << "vmcnt(" << Vmcnt << ')';
1398     NeedSpace = true;
1399   }
1400 
1401   if (Expcnt != getExpcntBitMask(ISA)) {
1402     if (NeedSpace)
1403       O << ' ';
1404     O << "expcnt(" << Expcnt << ')';
1405     NeedSpace = true;
1406   }
1407 
1408   if (Lgkmcnt != getLgkmcntBitMask(ISA)) {
1409     if (NeedSpace)
1410       O << ' ';
1411     O << "lgkmcnt(" << Lgkmcnt << ')';
1412   }
1413 }
1414 
1415 void AMDGPUInstPrinter::printHwreg(const MCInst *MI, unsigned OpNo,
1416                                    const MCSubtargetInfo &STI, raw_ostream &O) {
1417   unsigned Id;
1418   unsigned Offset;
1419   unsigned Width;
1420 
1421   using namespace llvm::AMDGPU::Hwreg;
1422   unsigned Val = MI->getOperand(OpNo).getImm();
1423   decodeHwreg(Val, Id, Offset, Width);
1424   StringRef HwRegName = getHwreg(Id, STI);
1425 
1426   O << "hwreg(";
1427   if (!HwRegName.empty()) {
1428     O << HwRegName;
1429   } else {
1430     O << Id;
1431   }
1432   if (Width != WIDTH_DEFAULT_ || Offset != OFFSET_DEFAULT_) {
1433     O << ", " << Offset << ", " << Width;
1434   }
1435   O << ')';
1436 }
1437 
1438 void AMDGPUInstPrinter::printEndpgm(const MCInst *MI, unsigned OpNo,
1439                                     const MCSubtargetInfo &STI,
1440                                     raw_ostream &O) {
1441   uint16_t Imm = MI->getOperand(OpNo).getImm();
1442   if (Imm == 0) {
1443     return;
1444   }
1445 
1446   O << ' ' << formatDec(Imm);
1447 }
1448 
1449 #include "AMDGPUGenAsmWriter.inc"
1450 
1451 void R600InstPrinter::printInst(const MCInst *MI, uint64_t Address,
1452                                 StringRef Annot, const MCSubtargetInfo &STI,
1453                                 raw_ostream &O) {
1454   O.flush();
1455   printInstruction(MI, Address, O);
1456   printAnnotation(O, Annot);
1457 }
1458 
1459 void R600InstPrinter::printAbs(const MCInst *MI, unsigned OpNo,
1460                                raw_ostream &O) {
1461   AMDGPUInstPrinter::printIfSet(MI, OpNo, O, '|');
1462 }
1463 
1464 void R600InstPrinter::printBankSwizzle(const MCInst *MI, unsigned OpNo,
1465                                        raw_ostream &O) {
1466   int BankSwizzle = MI->getOperand(OpNo).getImm();
1467   switch (BankSwizzle) {
1468   case 1:
1469     O << "BS:VEC_021/SCL_122";
1470     break;
1471   case 2:
1472     O << "BS:VEC_120/SCL_212";
1473     break;
1474   case 3:
1475     O << "BS:VEC_102/SCL_221";
1476     break;
1477   case 4:
1478     O << "BS:VEC_201";
1479     break;
1480   case 5:
1481     O << "BS:VEC_210";
1482     break;
1483   default:
1484     break;
1485   }
1486 }
1487 
1488 void R600InstPrinter::printClamp(const MCInst *MI, unsigned OpNo,
1489                                  raw_ostream &O) {
1490   AMDGPUInstPrinter::printIfSet(MI, OpNo, O, "_SAT");
1491 }
1492 
1493 void R600InstPrinter::printCT(const MCInst *MI, unsigned OpNo,
1494                                 raw_ostream &O) {
1495   unsigned CT = MI->getOperand(OpNo).getImm();
1496   switch (CT) {
1497   case 0:
1498     O << 'U';
1499     break;
1500   case 1:
1501     O << 'N';
1502     break;
1503   default:
1504     break;
1505   }
1506 }
1507 
1508 void R600InstPrinter::printKCache(const MCInst *MI, unsigned OpNo,
1509                                   raw_ostream &O) {
1510   int KCacheMode = MI->getOperand(OpNo).getImm();
1511   if (KCacheMode > 0) {
1512     int KCacheBank = MI->getOperand(OpNo - 2).getImm();
1513     O << "CB" << KCacheBank << ':';
1514     int KCacheAddr = MI->getOperand(OpNo + 2).getImm();
1515     int LineSize = (KCacheMode == 1) ? 16 : 32;
1516     O << KCacheAddr * 16 << '-' << KCacheAddr * 16 + LineSize;
1517   }
1518 }
1519 
1520 void R600InstPrinter::printLast(const MCInst *MI, unsigned OpNo,
1521                                 raw_ostream &O) {
1522   AMDGPUInstPrinter::printIfSet(MI, OpNo, O, "*", " ");
1523 }
1524 
1525 void R600InstPrinter::printLiteral(const MCInst *MI, unsigned OpNo,
1526                                    raw_ostream &O) {
1527   const MCOperand &Op = MI->getOperand(OpNo);
1528   assert(Op.isImm() || Op.isExpr());
1529   if (Op.isImm()) {
1530     int64_t Imm = Op.getImm();
1531     O << Imm << '(' << BitsToFloat(Imm) << ')';
1532   }
1533   if (Op.isExpr()) {
1534     Op.getExpr()->print(O << '@', &MAI);
1535   }
1536 }
1537 
1538 void R600InstPrinter::printNeg(const MCInst *MI, unsigned OpNo,
1539                                raw_ostream &O) {
1540   AMDGPUInstPrinter::printIfSet(MI, OpNo, O, '-');
1541 }
1542 
1543 void R600InstPrinter::printOMOD(const MCInst *MI, unsigned OpNo,
1544                                 raw_ostream &O) {
1545   switch (MI->getOperand(OpNo).getImm()) {
1546   default: break;
1547   case 1:
1548     O << " * 2.0";
1549     break;
1550   case 2:
1551     O << " * 4.0";
1552     break;
1553   case 3:
1554     O << " / 2.0";
1555     break;
1556   }
1557 }
1558 
1559 void R600InstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo,
1560                                       raw_ostream &O) {
1561   printOperand(MI, OpNo, O);
1562   O  << ", ";
1563   printOperand(MI, OpNo + 1, O);
1564 }
1565 
1566 void R600InstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
1567                                    raw_ostream &O) {
1568   if (OpNo >= MI->getNumOperands()) {
1569     O << "/*Missing OP" << OpNo << "*/";
1570     return;
1571   }
1572 
1573   const MCOperand &Op = MI->getOperand(OpNo);
1574   if (Op.isReg()) {
1575     switch (Op.getReg()) {
1576     // This is the default predicate state, so we don't need to print it.
1577     case R600::PRED_SEL_OFF:
1578       break;
1579 
1580     default:
1581       O << getRegisterName(Op.getReg());
1582       break;
1583     }
1584   } else if (Op.isImm()) {
1585       O << Op.getImm();
1586   } else if (Op.isDFPImm()) {
1587     // We special case 0.0 because otherwise it will be printed as an integer.
1588     if (Op.getDFPImm() == 0.0)
1589       O << "0.0";
1590     else {
1591       O << bit_cast<double>(Op.getDFPImm());
1592     }
1593   } else if (Op.isExpr()) {
1594     const MCExpr *Exp = Op.getExpr();
1595     Exp->print(O, &MAI);
1596   } else {
1597     O << "/*INV_OP*/";
1598   }
1599 }
1600 
1601 void R600InstPrinter::printRel(const MCInst *MI, unsigned OpNo,
1602                                raw_ostream &O) {
1603   AMDGPUInstPrinter::printIfSet(MI, OpNo, O, '+');
1604 }
1605 
1606 void R600InstPrinter::printRSel(const MCInst *MI, unsigned OpNo,
1607                                   raw_ostream &O) {
1608   unsigned Sel = MI->getOperand(OpNo).getImm();
1609   switch (Sel) {
1610   case 0:
1611     O << 'X';
1612     break;
1613   case 1:
1614     O << 'Y';
1615     break;
1616   case 2:
1617     O << 'Z';
1618     break;
1619   case 3:
1620     O << 'W';
1621     break;
1622   case 4:
1623     O << '0';
1624     break;
1625   case 5:
1626     O << '1';
1627     break;
1628   case 7:
1629     O << '_';
1630     break;
1631   default:
1632     break;
1633   }
1634 }
1635 
1636 void R600InstPrinter::printUpdateExecMask(const MCInst *MI, unsigned OpNo,
1637                                           raw_ostream &O) {
1638   AMDGPUInstPrinter::printIfSet(MI, OpNo, O, "ExecMask,");
1639 }
1640 
1641 void R600InstPrinter::printUpdatePred(const MCInst *MI, unsigned OpNo,
1642                                       raw_ostream &O) {
1643   AMDGPUInstPrinter::printIfSet(MI, OpNo, O, "Pred,");
1644 }
1645 
1646 void R600InstPrinter::printWrite(const MCInst *MI, unsigned OpNo,
1647                                  raw_ostream &O) {
1648   const MCOperand &Op = MI->getOperand(OpNo);
1649   if (Op.getImm() == 0) {
1650     O << " (MASKED)";
1651   }
1652 }
1653 
1654 #include "R600GenAsmWriter.inc"
1655