1 //===-- AMDGPUInstPrinter.cpp - AMDGPU MC Inst -> ASM ---------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 // \file
8 //===----------------------------------------------------------------------===//
9 
10 #include "AMDGPUInstPrinter.h"
11 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
12 #include "SIDefines.h"
13 #include "SIRegisterInfo.h"
14 #include "Utils/AMDGPUAsmUtils.h"
15 #include "Utils/AMDGPUBaseInfo.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCInstrDesc.h"
19 #include "llvm/MC/MCInstrInfo.h"
20 #include "llvm/MC/MCSubtargetInfo.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/TargetParser.h"
23 
24 using namespace llvm;
25 using namespace llvm::AMDGPU;
26 
27 static cl::opt<bool> Keep16BitSuffixes(
28   "amdgpu-keep-16-bit-reg-suffixes",
29   cl::desc("Keep .l and .h suffixes in asm for debugging purposes"),
30   cl::init(false),
31   cl::ReallyHidden);
32 
33 void AMDGPUInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
34   // FIXME: The current implementation of
35   // AsmParser::parseRegisterOrRegisterNumber in MC implies we either emit this
36   // as an integer or we provide a name which represents a physical register.
37   // For CFI instructions we really want to emit a name for the DWARF register
38   // instead, because there may be multiple DWARF registers corresponding to a
39   // single physical register. One case where this problem manifests is with
40   // wave32/wave64 where using the physical register name is ambiguous: if we
41   // write e.g. `.cfi_undefined v0` we lose information about the wavefront
42   // size which we need to encode the register in the final DWARF. Ideally we
43   // would extend MC to support parsing DWARF register names so we could do
44   // something like `.cfi_undefined dwarf_wave32_v0`. For now we just live with
45   // non-pretty DWARF register names in assembly text.
46   OS << RegNo;
47 }
48 
49 void AMDGPUInstPrinter::printInst(const MCInst *MI, uint64_t Address,
50                                   StringRef Annot, const MCSubtargetInfo &STI,
51                                   raw_ostream &OS) {
52   OS.flush();
53   printInstruction(MI, Address, STI, OS);
54   printAnnotation(OS, Annot);
55 }
56 
57 void AMDGPUInstPrinter::printU4ImmOperand(const MCInst *MI, unsigned OpNo,
58                                           const MCSubtargetInfo &STI,
59                                           raw_ostream &O) {
60   O << formatHex(MI->getOperand(OpNo).getImm() & 0xf);
61 }
62 
63 void AMDGPUInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo,
64                                           raw_ostream &O) {
65   O << formatHex(MI->getOperand(OpNo).getImm() & 0xff);
66 }
67 
68 void AMDGPUInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
69                                            const MCSubtargetInfo &STI,
70                                            raw_ostream &O) {
71   // It's possible to end up with a 32-bit literal used with a 16-bit operand
72   // with ignored high bits. Print as 32-bit anyway in that case.
73   int64_t Imm = MI->getOperand(OpNo).getImm();
74   if (isInt<16>(Imm) || isUInt<16>(Imm))
75     O << formatHex(static_cast<uint64_t>(Imm & 0xffff));
76   else
77     printU32ImmOperand(MI, OpNo, STI, O);
78 }
79 
80 void AMDGPUInstPrinter::printU4ImmDecOperand(const MCInst *MI, unsigned OpNo,
81                                              raw_ostream &O) {
82   O << formatDec(MI->getOperand(OpNo).getImm() & 0xf);
83 }
84 
85 void AMDGPUInstPrinter::printU8ImmDecOperand(const MCInst *MI, unsigned OpNo,
86                                              raw_ostream &O) {
87   O << formatDec(MI->getOperand(OpNo).getImm() & 0xff);
88 }
89 
90 void AMDGPUInstPrinter::printU16ImmDecOperand(const MCInst *MI, unsigned OpNo,
91                                               raw_ostream &O) {
92   O << formatDec(MI->getOperand(OpNo).getImm() & 0xffff);
93 }
94 
95 void AMDGPUInstPrinter::printU32ImmOperand(const MCInst *MI, unsigned OpNo,
96                                            const MCSubtargetInfo &STI,
97                                            raw_ostream &O) {
98   O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff);
99 }
100 
101 void AMDGPUInstPrinter::printNamedBit(const MCInst *MI, unsigned OpNo,
102                                       raw_ostream &O, StringRef BitName) {
103   if (MI->getOperand(OpNo).getImm()) {
104     O << ' ' << BitName;
105   }
106 }
107 
108 void AMDGPUInstPrinter::printOffen(const MCInst *MI, unsigned OpNo,
109                                    raw_ostream &O) {
110   printNamedBit(MI, OpNo, O, "offen");
111 }
112 
113 void AMDGPUInstPrinter::printIdxen(const MCInst *MI, unsigned OpNo,
114                                    raw_ostream &O) {
115   printNamedBit(MI, OpNo, O, "idxen");
116 }
117 
118 void AMDGPUInstPrinter::printAddr64(const MCInst *MI, unsigned OpNo,
119                                     raw_ostream &O) {
120   printNamedBit(MI, OpNo, O, "addr64");
121 }
122 
123 void AMDGPUInstPrinter::printMBUFOffset(const MCInst *MI, unsigned OpNo,
124                                         raw_ostream &O) {
125   if (MI->getOperand(OpNo).getImm()) {
126     O << " offset:";
127     printU16ImmDecOperand(MI, OpNo, O);
128   }
129 }
130 
131 void AMDGPUInstPrinter::printOffset(const MCInst *MI, unsigned OpNo,
132                                     const MCSubtargetInfo &STI,
133                                     raw_ostream &O) {
134   uint16_t Imm = MI->getOperand(OpNo).getImm();
135   if (Imm != 0) {
136     O << " offset:";
137     printU16ImmDecOperand(MI, OpNo, O);
138   }
139 }
140 
141 void AMDGPUInstPrinter::printFlatOffset(const MCInst *MI, unsigned OpNo,
142                                         const MCSubtargetInfo &STI,
143                                         raw_ostream &O) {
144   uint16_t Imm = MI->getOperand(OpNo).getImm();
145   if (Imm != 0) {
146     O << " offset:";
147 
148     const MCInstrDesc &Desc = MII.get(MI->getOpcode());
149     bool IsFlatSeg = !(Desc.TSFlags &
150                        (SIInstrFlags::FlatGlobal | SIInstrFlags::FlatScratch));
151 
152     if (IsFlatSeg) { // Unsigned offset
153       printU16ImmDecOperand(MI, OpNo, O);
154     } else {         // Signed offset
155       if (AMDGPU::isGFX10Plus(STI)) {
156         O << formatDec(SignExtend32<12>(MI->getOperand(OpNo).getImm()));
157       } else {
158         O << formatDec(SignExtend32<13>(MI->getOperand(OpNo).getImm()));
159       }
160     }
161   }
162 }
163 
164 void AMDGPUInstPrinter::printOffset0(const MCInst *MI, unsigned OpNo,
165                                      const MCSubtargetInfo &STI,
166                                      raw_ostream &O) {
167   if (MI->getOperand(OpNo).getImm()) {
168     O << " offset0:";
169     printU8ImmDecOperand(MI, OpNo, O);
170   }
171 }
172 
173 void AMDGPUInstPrinter::printOffset1(const MCInst *MI, unsigned OpNo,
174                                      const MCSubtargetInfo &STI,
175                                      raw_ostream &O) {
176   if (MI->getOperand(OpNo).getImm()) {
177     O << " offset1:";
178     printU8ImmDecOperand(MI, OpNo, O);
179   }
180 }
181 
182 void AMDGPUInstPrinter::printSMRDOffset8(const MCInst *MI, unsigned OpNo,
183                                         const MCSubtargetInfo &STI,
184                                         raw_ostream &O) {
185   printU32ImmOperand(MI, OpNo, STI, O);
186 }
187 
188 void AMDGPUInstPrinter::printSMEMOffset(const MCInst *MI, unsigned OpNo,
189                                         const MCSubtargetInfo &STI,
190                                         raw_ostream &O) {
191   O << formatHex(MI->getOperand(OpNo).getImm());
192 }
193 
194 void AMDGPUInstPrinter::printSMRDLiteralOffset(const MCInst *MI, unsigned OpNo,
195                                                const MCSubtargetInfo &STI,
196                                                raw_ostream &O) {
197   printU32ImmOperand(MI, OpNo, STI, O);
198 }
199 
200 void AMDGPUInstPrinter::printGDS(const MCInst *MI, unsigned OpNo,
201                                  const MCSubtargetInfo &STI, raw_ostream &O) {
202   printNamedBit(MI, OpNo, O, "gds");
203 }
204 
205 void AMDGPUInstPrinter::printCPol(const MCInst *MI, unsigned OpNo,
206                                   const MCSubtargetInfo &STI, raw_ostream &O) {
207   auto Imm = MI->getOperand(OpNo).getImm();
208   if (Imm & CPol::GLC)
209     O << ((AMDGPU::isGFX940(STI) &&
210            !(MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::SMRD)) ? " sc0"
211                                                                      : " glc");
212   if (Imm & CPol::SLC)
213     O << (AMDGPU::isGFX940(STI) ? " nt" : " slc");
214   if ((Imm & CPol::DLC) && AMDGPU::isGFX10Plus(STI))
215     O << " dlc";
216   if ((Imm & CPol::SCC) && AMDGPU::isGFX90A(STI))
217     O << (AMDGPU::isGFX940(STI) ? " sc1" : " scc");
218   if (Imm & ~CPol::ALL)
219     O << " /* unexpected cache policy bit */";
220 }
221 
222 void AMDGPUInstPrinter::printSWZ(const MCInst *MI, unsigned OpNo,
223                                  const MCSubtargetInfo &STI, raw_ostream &O) {
224 }
225 
226 void AMDGPUInstPrinter::printTFE(const MCInst *MI, unsigned OpNo,
227                                  const MCSubtargetInfo &STI, raw_ostream &O) {
228   printNamedBit(MI, OpNo, O, "tfe");
229 }
230 
231 void AMDGPUInstPrinter::printDMask(const MCInst *MI, unsigned OpNo,
232                                    const MCSubtargetInfo &STI, raw_ostream &O) {
233   if (MI->getOperand(OpNo).getImm()) {
234     O << " dmask:";
235     printU16ImmOperand(MI, OpNo, STI, O);
236   }
237 }
238 
239 void AMDGPUInstPrinter::printDim(const MCInst *MI, unsigned OpNo,
240                                  const MCSubtargetInfo &STI, raw_ostream &O) {
241   unsigned Dim = MI->getOperand(OpNo).getImm();
242   O << " dim:SQ_RSRC_IMG_";
243 
244   const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfoByEncoding(Dim);
245   if (DimInfo)
246     O << DimInfo->AsmSuffix;
247   else
248     O << Dim;
249 }
250 
251 void AMDGPUInstPrinter::printUNorm(const MCInst *MI, unsigned OpNo,
252                                    const MCSubtargetInfo &STI, raw_ostream &O) {
253   printNamedBit(MI, OpNo, O, "unorm");
254 }
255 
256 void AMDGPUInstPrinter::printDA(const MCInst *MI, unsigned OpNo,
257                                 const MCSubtargetInfo &STI, raw_ostream &O) {
258   printNamedBit(MI, OpNo, O, "da");
259 }
260 
261 void AMDGPUInstPrinter::printR128A16(const MCInst *MI, unsigned OpNo,
262                                   const MCSubtargetInfo &STI, raw_ostream &O) {
263   if (STI.hasFeature(AMDGPU::FeatureR128A16))
264     printNamedBit(MI, OpNo, O, "a16");
265   else
266     printNamedBit(MI, OpNo, O, "r128");
267 }
268 
269 void AMDGPUInstPrinter::printGFX10A16(const MCInst *MI, unsigned OpNo,
270                                   const MCSubtargetInfo &STI, raw_ostream &O) {
271   printNamedBit(MI, OpNo, O, "a16");
272 }
273 
274 void AMDGPUInstPrinter::printLWE(const MCInst *MI, unsigned OpNo,
275                                  const MCSubtargetInfo &STI, raw_ostream &O) {
276   printNamedBit(MI, OpNo, O, "lwe");
277 }
278 
279 void AMDGPUInstPrinter::printD16(const MCInst *MI, unsigned OpNo,
280                                  const MCSubtargetInfo &STI, raw_ostream &O) {
281   printNamedBit(MI, OpNo, O, "d16");
282 }
283 
284 void AMDGPUInstPrinter::printExpCompr(const MCInst *MI, unsigned OpNo,
285                                       const MCSubtargetInfo &STI,
286                                       raw_ostream &O) {
287   printNamedBit(MI, OpNo, O, "compr");
288 }
289 
290 void AMDGPUInstPrinter::printExpVM(const MCInst *MI, unsigned OpNo,
291                                    const MCSubtargetInfo &STI,
292                                    raw_ostream &O) {
293   printNamedBit(MI, OpNo, O, "vm");
294 }
295 
296 void AMDGPUInstPrinter::printFORMAT(const MCInst *MI, unsigned OpNo,
297                                     const MCSubtargetInfo &STI,
298                                     raw_ostream &O) {
299 }
300 
301 void AMDGPUInstPrinter::printSymbolicFormat(const MCInst *MI,
302                                             const MCSubtargetInfo &STI,
303                                             raw_ostream &O) {
304   using namespace llvm::AMDGPU::MTBUFFormat;
305 
306   int OpNo =
307     AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::format);
308   assert(OpNo != -1);
309 
310   unsigned Val = MI->getOperand(OpNo).getImm();
311   if (AMDGPU::isGFX10Plus(STI)) {
312     if (Val == UFMT_DEFAULT)
313       return;
314     if (isValidUnifiedFormat(Val)) {
315       O << " format:[" << getUnifiedFormatName(Val) << ']';
316     } else {
317       O << " format:" << Val;
318     }
319   } else {
320     if (Val == DFMT_NFMT_DEFAULT)
321       return;
322     if (isValidDfmtNfmt(Val, STI)) {
323       unsigned Dfmt;
324       unsigned Nfmt;
325       decodeDfmtNfmt(Val, Dfmt, Nfmt);
326       O << " format:[";
327       if (Dfmt != DFMT_DEFAULT) {
328         O << getDfmtName(Dfmt);
329         if (Nfmt != NFMT_DEFAULT) {
330           O << ',';
331         }
332       }
333       if (Nfmt != NFMT_DEFAULT) {
334         O << getNfmtName(Nfmt, STI);
335       }
336       O << ']';
337     } else {
338       O << " format:" << Val;
339     }
340   }
341 }
342 
343 void AMDGPUInstPrinter::printRegOperand(unsigned RegNo, raw_ostream &O,
344                                         const MCRegisterInfo &MRI) {
345 #if !defined(NDEBUG)
346   switch (RegNo) {
347   case AMDGPU::FP_REG:
348   case AMDGPU::SP_REG:
349   case AMDGPU::PRIVATE_RSRC_REG:
350     llvm_unreachable("pseudo-register should not ever be emitted");
351   case AMDGPU::SCC:
352     llvm_unreachable("pseudo scc should not ever be emitted");
353   default:
354     break;
355   }
356 #endif
357 
358   StringRef RegName(getRegisterName(RegNo));
359   if (!Keep16BitSuffixes)
360     if (!RegName.consume_back(".l"))
361       RegName.consume_back(".h");
362 
363   O << RegName;
364 }
365 
366 void AMDGPUInstPrinter::printVOPDst(const MCInst *MI, unsigned OpNo,
367                                     const MCSubtargetInfo &STI,
368                                     raw_ostream &O) {
369   auto Opcode = MI->getOpcode();
370   auto Flags = MII.get(Opcode).TSFlags;
371 
372   if (OpNo == 0) {
373     if (Flags & SIInstrFlags::VOP3) {
374       if (!getVOP3IsSingle(Opcode))
375         O << "_e64";
376     } else if (Flags & SIInstrFlags::DPP) {
377       O << "_dpp";
378     } else if (Flags & SIInstrFlags::SDWA) {
379       O << "_sdwa";
380     } else if (((Flags & SIInstrFlags::VOP1) && !getVOP1IsSingle(Opcode)) ||
381                ((Flags & SIInstrFlags::VOP2) && !getVOP2IsSingle(Opcode))) {
382       O << "_e32";
383     }
384     O << " ";
385   }
386 
387   printOperand(MI, OpNo, STI, O);
388 
389   // Print default vcc/vcc_lo operand.
390   switch (Opcode) {
391   default: break;
392 
393   case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10:
394   case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10:
395   case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10:
396   case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10:
397   case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10:
398   case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10:
399   case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10:
400   case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10:
401   case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10:
402   case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10:
403   case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10:
404   case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10:
405     printDefaultVccOperand(1, STI, O);
406     break;
407   }
408 }
409 
410 void AMDGPUInstPrinter::printVINTRPDst(const MCInst *MI, unsigned OpNo,
411                                        const MCSubtargetInfo &STI, raw_ostream &O) {
412   if (AMDGPU::isSI(STI) || AMDGPU::isCI(STI))
413     O << " ";
414   else
415     O << "_e32 ";
416 
417   printOperand(MI, OpNo, STI, O);
418 }
419 
420 void AMDGPUInstPrinter::printImmediateInt16(uint32_t Imm,
421                                             const MCSubtargetInfo &STI,
422                                             raw_ostream &O) {
423   int16_t SImm = static_cast<int16_t>(Imm);
424   if (isInlinableIntLiteral(SImm)) {
425     O << SImm;
426   } else {
427     uint64_t Imm16 = static_cast<uint16_t>(Imm);
428     O << formatHex(Imm16);
429   }
430 }
431 
432 void AMDGPUInstPrinter::printImmediate16(uint32_t Imm,
433                                          const MCSubtargetInfo &STI,
434                                          raw_ostream &O) {
435   int16_t SImm = static_cast<int16_t>(Imm);
436   if (isInlinableIntLiteral(SImm)) {
437     O << SImm;
438     return;
439   }
440 
441   if (Imm == 0x3C00)
442     O<< "1.0";
443   else if (Imm == 0xBC00)
444     O<< "-1.0";
445   else if (Imm == 0x3800)
446     O<< "0.5";
447   else if (Imm == 0xB800)
448     O<< "-0.5";
449   else if (Imm == 0x4000)
450     O<< "2.0";
451   else if (Imm == 0xC000)
452     O<< "-2.0";
453   else if (Imm == 0x4400)
454     O<< "4.0";
455   else if (Imm == 0xC400)
456     O<< "-4.0";
457   else if (Imm == 0x3118 &&
458            STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]) {
459     O << "0.15915494";
460   } else {
461     uint64_t Imm16 = static_cast<uint16_t>(Imm);
462     O << formatHex(Imm16);
463   }
464 }
465 
466 void AMDGPUInstPrinter::printImmediateV216(uint32_t Imm,
467                                            const MCSubtargetInfo &STI,
468                                            raw_ostream &O) {
469   uint16_t Lo16 = static_cast<uint16_t>(Imm);
470   printImmediate16(Lo16, STI, O);
471 }
472 
473 void AMDGPUInstPrinter::printImmediate32(uint32_t Imm,
474                                          const MCSubtargetInfo &STI,
475                                          raw_ostream &O) {
476   int32_t SImm = static_cast<int32_t>(Imm);
477   if (SImm >= -16 && SImm <= 64) {
478     O << SImm;
479     return;
480   }
481 
482   if (Imm == FloatToBits(0.0f))
483     O << "0.0";
484   else if (Imm == FloatToBits(1.0f))
485     O << "1.0";
486   else if (Imm == FloatToBits(-1.0f))
487     O << "-1.0";
488   else if (Imm == FloatToBits(0.5f))
489     O << "0.5";
490   else if (Imm == FloatToBits(-0.5f))
491     O << "-0.5";
492   else if (Imm == FloatToBits(2.0f))
493     O << "2.0";
494   else if (Imm == FloatToBits(-2.0f))
495     O << "-2.0";
496   else if (Imm == FloatToBits(4.0f))
497     O << "4.0";
498   else if (Imm == FloatToBits(-4.0f))
499     O << "-4.0";
500   else if (Imm == 0x3e22f983 &&
501            STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
502     O << "0.15915494";
503   else
504     O << formatHex(static_cast<uint64_t>(Imm));
505 }
506 
507 void AMDGPUInstPrinter::printImmediate64(uint64_t Imm,
508                                          const MCSubtargetInfo &STI,
509                                          raw_ostream &O) {
510   int64_t SImm = static_cast<int64_t>(Imm);
511   if (SImm >= -16 && SImm <= 64) {
512     O << SImm;
513     return;
514   }
515 
516   if (Imm == DoubleToBits(0.0))
517     O << "0.0";
518   else if (Imm == DoubleToBits(1.0))
519     O << "1.0";
520   else if (Imm == DoubleToBits(-1.0))
521     O << "-1.0";
522   else if (Imm == DoubleToBits(0.5))
523     O << "0.5";
524   else if (Imm == DoubleToBits(-0.5))
525     O << "-0.5";
526   else if (Imm == DoubleToBits(2.0))
527     O << "2.0";
528   else if (Imm == DoubleToBits(-2.0))
529     O << "-2.0";
530   else if (Imm == DoubleToBits(4.0))
531     O << "4.0";
532   else if (Imm == DoubleToBits(-4.0))
533     O << "-4.0";
534   else if (Imm == 0x3fc45f306dc9c882 &&
535            STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
536     O << "0.15915494309189532";
537   else {
538     assert(isUInt<32>(Imm) || Imm == 0x3fc45f306dc9c882);
539 
540     // In rare situations, we will have a 32-bit literal in a 64-bit
541     // operand. This is technically allowed for the encoding of s_mov_b64.
542     O << formatHex(static_cast<uint64_t>(Imm));
543   }
544 }
545 
546 void AMDGPUInstPrinter::printBLGP(const MCInst *MI, unsigned OpNo,
547                                   const MCSubtargetInfo &STI,
548                                   raw_ostream &O) {
549   unsigned Imm = MI->getOperand(OpNo).getImm();
550   if (!Imm)
551     return;
552 
553   O << " blgp:" << Imm;
554 }
555 
556 void AMDGPUInstPrinter::printCBSZ(const MCInst *MI, unsigned OpNo,
557                                   const MCSubtargetInfo &STI,
558                                   raw_ostream &O) {
559   unsigned Imm = MI->getOperand(OpNo).getImm();
560   if (!Imm)
561     return;
562 
563   O << " cbsz:" << Imm;
564 }
565 
566 void AMDGPUInstPrinter::printABID(const MCInst *MI, unsigned OpNo,
567                                   const MCSubtargetInfo &STI,
568                                   raw_ostream &O) {
569   unsigned Imm = MI->getOperand(OpNo).getImm();
570   if (!Imm)
571     return;
572 
573   O << " abid:" << Imm;
574 }
575 
576 void AMDGPUInstPrinter::printDefaultVccOperand(unsigned OpNo,
577                                                const MCSubtargetInfo &STI,
578                                                raw_ostream &O) {
579   if (OpNo > 0)
580     O << ", ";
581   printRegOperand(STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ?
582                   AMDGPU::VCC : AMDGPU::VCC_LO, O, MRI);
583   if (OpNo == 0)
584     O << ", ";
585 }
586 
587 void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
588                                      const MCSubtargetInfo &STI,
589                                      raw_ostream &O) {
590   // Print default vcc/vcc_lo operand of VOPC.
591   const MCInstrDesc &Desc = MII.get(MI->getOpcode());
592   if (OpNo == 0 && (Desc.TSFlags & SIInstrFlags::VOPC) &&
593       (Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC) ||
594        Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC_LO)))
595     printDefaultVccOperand(OpNo, STI, O);
596 
597   if (OpNo >= MI->getNumOperands()) {
598     O << "/*Missing OP" << OpNo << "*/";
599     return;
600   }
601 
602   const MCOperand &Op = MI->getOperand(OpNo);
603   if (Op.isReg()) {
604     printRegOperand(Op.getReg(), O, MRI);
605   } else if (Op.isImm()) {
606     const uint8_t OpTy = Desc.OpInfo[OpNo].OperandType;
607     switch (OpTy) {
608     case AMDGPU::OPERAND_REG_IMM_INT32:
609     case AMDGPU::OPERAND_REG_IMM_FP32:
610     case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED:
611     case AMDGPU::OPERAND_REG_INLINE_C_INT32:
612     case AMDGPU::OPERAND_REG_INLINE_C_FP32:
613     case AMDGPU::OPERAND_REG_INLINE_AC_INT32:
614     case AMDGPU::OPERAND_REG_INLINE_AC_FP32:
615     case AMDGPU::OPERAND_REG_IMM_V2INT32:
616     case AMDGPU::OPERAND_REG_IMM_V2FP32:
617     case AMDGPU::OPERAND_REG_INLINE_C_V2INT32:
618     case AMDGPU::OPERAND_REG_INLINE_C_V2FP32:
619     case MCOI::OPERAND_IMMEDIATE:
620       printImmediate32(Op.getImm(), STI, O);
621       break;
622     case AMDGPU::OPERAND_REG_IMM_INT64:
623     case AMDGPU::OPERAND_REG_IMM_FP64:
624     case AMDGPU::OPERAND_REG_INLINE_C_INT64:
625     case AMDGPU::OPERAND_REG_INLINE_C_FP64:
626     case AMDGPU::OPERAND_REG_INLINE_AC_FP64:
627       printImmediate64(Op.getImm(), STI, O);
628       break;
629     case AMDGPU::OPERAND_REG_INLINE_C_INT16:
630     case AMDGPU::OPERAND_REG_INLINE_AC_INT16:
631     case AMDGPU::OPERAND_REG_IMM_INT16:
632       printImmediateInt16(Op.getImm(), STI, O);
633       break;
634     case AMDGPU::OPERAND_REG_INLINE_C_FP16:
635     case AMDGPU::OPERAND_REG_INLINE_AC_FP16:
636     case AMDGPU::OPERAND_REG_IMM_FP16:
637     case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED:
638       printImmediate16(Op.getImm(), STI, O);
639       break;
640     case AMDGPU::OPERAND_REG_IMM_V2INT16:
641     case AMDGPU::OPERAND_REG_IMM_V2FP16:
642       if (!isUInt<16>(Op.getImm()) &&
643           STI.getFeatureBits()[AMDGPU::FeatureVOP3Literal]) {
644         printImmediate32(Op.getImm(), STI, O);
645         break;
646       }
647 
648       //  Deal with 16-bit FP inline immediates not working.
649       if (OpTy == AMDGPU::OPERAND_REG_IMM_V2FP16) {
650         printImmediate16(static_cast<uint16_t>(Op.getImm()), STI, O);
651         break;
652       }
653       LLVM_FALLTHROUGH;
654     case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
655     case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:
656       printImmediateInt16(static_cast<uint16_t>(Op.getImm()), STI, O);
657       break;
658     case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
659     case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16:
660       printImmediateV216(Op.getImm(), STI, O);
661       break;
662     case MCOI::OPERAND_UNKNOWN:
663     case MCOI::OPERAND_PCREL:
664       O << formatDec(Op.getImm());
665       break;
666     case MCOI::OPERAND_REGISTER:
667       // FIXME: This should be removed and handled somewhere else. Seems to come
668       // from a disassembler bug.
669       O << "/*invalid immediate*/";
670       break;
671     default:
672       // We hit this for the immediate instruction bits that don't yet have a
673       // custom printer.
674       llvm_unreachable("unexpected immediate operand type");
675     }
676   } else if (Op.isDFPImm()) {
677     double Value = bit_cast<double>(Op.getDFPImm());
678     // We special case 0.0 because otherwise it will be printed as an integer.
679     if (Value == 0.0)
680       O << "0.0";
681     else {
682       const MCInstrDesc &Desc = MII.get(MI->getOpcode());
683       int RCID = Desc.OpInfo[OpNo].RegClass;
684       unsigned RCBits = AMDGPU::getRegBitWidth(MRI.getRegClass(RCID));
685       if (RCBits == 32)
686         printImmediate32(FloatToBits(Value), STI, O);
687       else if (RCBits == 64)
688         printImmediate64(DoubleToBits(Value), STI, O);
689       else
690         llvm_unreachable("Invalid register class size");
691     }
692   } else if (Op.isExpr()) {
693     const MCExpr *Exp = Op.getExpr();
694     Exp->print(O, &MAI);
695   } else {
696     O << "/*INV_OP*/";
697   }
698 
699   // Print default vcc/vcc_lo operand of v_cndmask_b32_e32.
700   switch (MI->getOpcode()) {
701   default: break;
702 
703   case AMDGPU::V_CNDMASK_B32_e32_gfx10:
704   case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10:
705   case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10:
706   case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10:
707   case AMDGPU::V_CNDMASK_B32_dpp_gfx10:
708   case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10:
709   case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10:
710   case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10:
711   case AMDGPU::V_CNDMASK_B32_dpp8_gfx10:
712   case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10:
713   case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10:
714   case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10:
715 
716   case AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7:
717   case AMDGPU::V_CNDMASK_B32_e32_vi:
718     if ((int)OpNo == AMDGPU::getNamedOperandIdx(MI->getOpcode(),
719                                                 AMDGPU::OpName::src1))
720       printDefaultVccOperand(OpNo, STI, O);
721     break;
722   }
723 
724   if (Desc.TSFlags & SIInstrFlags::MTBUF) {
725     int SOffsetIdx =
726       AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::soffset);
727     assert(SOffsetIdx != -1);
728     if ((int)OpNo == SOffsetIdx)
729       printSymbolicFormat(MI, STI, O);
730   }
731 }
732 
733 void AMDGPUInstPrinter::printOperandAndFPInputMods(const MCInst *MI,
734                                                    unsigned OpNo,
735                                                    const MCSubtargetInfo &STI,
736                                                    raw_ostream &O) {
737   unsigned InputModifiers = MI->getOperand(OpNo).getImm();
738 
739   // Use 'neg(...)' instead of '-' to avoid ambiguity.
740   // This is important for integer literals because
741   // -1 is not the same value as neg(1).
742   bool NegMnemo = false;
743 
744   if (InputModifiers & SISrcMods::NEG) {
745     if (OpNo + 1 < MI->getNumOperands() &&
746         (InputModifiers & SISrcMods::ABS) == 0) {
747       const MCOperand &Op = MI->getOperand(OpNo + 1);
748       NegMnemo = Op.isImm() || Op.isDFPImm();
749     }
750     if (NegMnemo) {
751       O << "neg(";
752     } else {
753       O << '-';
754     }
755   }
756 
757   if (InputModifiers & SISrcMods::ABS)
758     O << '|';
759   printOperand(MI, OpNo + 1, STI, O);
760   if (InputModifiers & SISrcMods::ABS)
761     O << '|';
762 
763   if (NegMnemo) {
764     O << ')';
765   }
766 }
767 
768 void AMDGPUInstPrinter::printOperandAndIntInputMods(const MCInst *MI,
769                                                     unsigned OpNo,
770                                                     const MCSubtargetInfo &STI,
771                                                     raw_ostream &O) {
772   unsigned InputModifiers = MI->getOperand(OpNo).getImm();
773   if (InputModifiers & SISrcMods::SEXT)
774     O << "sext(";
775   printOperand(MI, OpNo + 1, STI, O);
776   if (InputModifiers & SISrcMods::SEXT)
777     O << ')';
778 
779   // Print default vcc/vcc_lo operand of VOP2b.
780   switch (MI->getOpcode()) {
781   default: break;
782 
783   case AMDGPU::V_CNDMASK_B32_sdwa_gfx10:
784   case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10:
785   case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10:
786   case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10:
787     if ((int)OpNo + 1 == AMDGPU::getNamedOperandIdx(MI->getOpcode(),
788                                                     AMDGPU::OpName::src1))
789       printDefaultVccOperand(OpNo, STI, O);
790     break;
791   }
792 }
793 
794 void AMDGPUInstPrinter::printDPP8(const MCInst *MI, unsigned OpNo,
795                                   const MCSubtargetInfo &STI,
796                                   raw_ostream &O) {
797   if (!AMDGPU::isGFX10Plus(STI))
798     llvm_unreachable("dpp8 is not supported on ASICs earlier than GFX10");
799 
800   unsigned Imm = MI->getOperand(OpNo).getImm();
801   O << "dpp8:[" << formatDec(Imm & 0x7);
802   for (size_t i = 1; i < 8; ++i) {
803     O << ',' << formatDec((Imm >> (3 * i)) & 0x7);
804   }
805   O << ']';
806 }
807 
808 void AMDGPUInstPrinter::printDPPCtrl(const MCInst *MI, unsigned OpNo,
809                                      const MCSubtargetInfo &STI,
810                                      raw_ostream &O) {
811   using namespace AMDGPU::DPP;
812 
813   unsigned Imm = MI->getOperand(OpNo).getImm();
814   const MCInstrDesc &Desc = MII.get(MI->getOpcode());
815   int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
816                                            AMDGPU::OpName::src0);
817 
818   if (Src0Idx >= 0 &&
819       Desc.OpInfo[Src0Idx].RegClass == AMDGPU::VReg_64RegClassID &&
820       !AMDGPU::isLegal64BitDPPControl(Imm)) {
821     O << " /* 64 bit dpp only supports row_newbcast */";
822     return;
823   } else if (Imm <= DppCtrl::QUAD_PERM_LAST) {
824     O << "quad_perm:[";
825     O << formatDec(Imm & 0x3)         << ',';
826     O << formatDec((Imm & 0xc)  >> 2) << ',';
827     O << formatDec((Imm & 0x30) >> 4) << ',';
828     O << formatDec((Imm & 0xc0) >> 6) << ']';
829   } else if ((Imm >= DppCtrl::ROW_SHL_FIRST) &&
830              (Imm <= DppCtrl::ROW_SHL_LAST)) {
831     O << "row_shl:";
832     printU4ImmDecOperand(MI, OpNo, O);
833   } else if ((Imm >= DppCtrl::ROW_SHR_FIRST) &&
834              (Imm <= DppCtrl::ROW_SHR_LAST)) {
835     O << "row_shr:";
836     printU4ImmDecOperand(MI, OpNo, O);
837   } else if ((Imm >= DppCtrl::ROW_ROR_FIRST) &&
838              (Imm <= DppCtrl::ROW_ROR_LAST)) {
839     O << "row_ror:";
840     printU4ImmDecOperand(MI, OpNo, O);
841   } else if (Imm == DppCtrl::WAVE_SHL1) {
842     if (AMDGPU::isGFX10Plus(STI)) {
843       O << "/* wave_shl is not supported starting from GFX10 */";
844       return;
845     }
846     O << "wave_shl:1";
847   } else if (Imm == DppCtrl::WAVE_ROL1) {
848     if (AMDGPU::isGFX10Plus(STI)) {
849       O << "/* wave_rol is not supported starting from GFX10 */";
850       return;
851     }
852     O << "wave_rol:1";
853   } else if (Imm == DppCtrl::WAVE_SHR1) {
854     if (AMDGPU::isGFX10Plus(STI)) {
855       O << "/* wave_shr is not supported starting from GFX10 */";
856       return;
857     }
858     O << "wave_shr:1";
859   } else if (Imm == DppCtrl::WAVE_ROR1) {
860     if (AMDGPU::isGFX10Plus(STI)) {
861       O << "/* wave_ror is not supported starting from GFX10 */";
862       return;
863     }
864     O << "wave_ror:1";
865   } else if (Imm == DppCtrl::ROW_MIRROR) {
866     O << "row_mirror";
867   } else if (Imm == DppCtrl::ROW_HALF_MIRROR) {
868     O << "row_half_mirror";
869   } else if (Imm == DppCtrl::BCAST15) {
870     if (AMDGPU::isGFX10Plus(STI)) {
871       O << "/* row_bcast is not supported starting from GFX10 */";
872       return;
873     }
874     O << "row_bcast:15";
875   } else if (Imm == DppCtrl::BCAST31) {
876     if (AMDGPU::isGFX10Plus(STI)) {
877       O << "/* row_bcast is not supported starting from GFX10 */";
878       return;
879     }
880     O << "row_bcast:31";
881   } else if ((Imm >= DppCtrl::ROW_SHARE_FIRST) &&
882              (Imm <= DppCtrl::ROW_SHARE_LAST)) {
883     if (AMDGPU::isGFX90A(STI)) {
884       O << "row_newbcast:";
885     } else if (AMDGPU::isGFX10Plus(STI)) {
886       O << "row_share:";
887     } else {
888       O << " /* row_newbcast/row_share is not supported on ASICs earlier "
889            "than GFX90A/GFX10 */";
890       return;
891     }
892     printU4ImmDecOperand(MI, OpNo, O);
893   } else if ((Imm >= DppCtrl::ROW_XMASK_FIRST) &&
894              (Imm <= DppCtrl::ROW_XMASK_LAST)) {
895     if (!AMDGPU::isGFX10Plus(STI)) {
896       O << "/* row_xmask is not supported on ASICs earlier than GFX10 */";
897       return;
898     }
899     O << "row_xmask:";
900     printU4ImmDecOperand(MI, OpNo, O);
901   } else {
902     O << "/* Invalid dpp_ctrl value */";
903   }
904 }
905 
906 void AMDGPUInstPrinter::printRowMask(const MCInst *MI, unsigned OpNo,
907                                      const MCSubtargetInfo &STI,
908                                      raw_ostream &O) {
909   O << " row_mask:";
910   printU4ImmOperand(MI, OpNo, STI, O);
911 }
912 
913 void AMDGPUInstPrinter::printBankMask(const MCInst *MI, unsigned OpNo,
914                                       const MCSubtargetInfo &STI,
915                                       raw_ostream &O) {
916   O << " bank_mask:";
917   printU4ImmOperand(MI, OpNo, STI, O);
918 }
919 
920 void AMDGPUInstPrinter::printBoundCtrl(const MCInst *MI, unsigned OpNo,
921                                        const MCSubtargetInfo &STI,
922                                        raw_ostream &O) {
923   unsigned Imm = MI->getOperand(OpNo).getImm();
924   if (Imm) {
925     O << " bound_ctrl:1";
926   }
927 }
928 
929 void AMDGPUInstPrinter::printFI(const MCInst *MI, unsigned OpNo,
930                                 const MCSubtargetInfo &STI,
931                                 raw_ostream &O) {
932   using namespace llvm::AMDGPU::DPP;
933   unsigned Imm = MI->getOperand(OpNo).getImm();
934   if (Imm == DPP_FI_1 || Imm == DPP8_FI_1) {
935     O << " fi:1";
936   }
937 }
938 
939 void AMDGPUInstPrinter::printSDWASel(const MCInst *MI, unsigned OpNo,
940                                      raw_ostream &O) {
941   using namespace llvm::AMDGPU::SDWA;
942 
943   unsigned Imm = MI->getOperand(OpNo).getImm();
944   switch (Imm) {
945   case SdwaSel::BYTE_0: O << "BYTE_0"; break;
946   case SdwaSel::BYTE_1: O << "BYTE_1"; break;
947   case SdwaSel::BYTE_2: O << "BYTE_2"; break;
948   case SdwaSel::BYTE_3: O << "BYTE_3"; break;
949   case SdwaSel::WORD_0: O << "WORD_0"; break;
950   case SdwaSel::WORD_1: O << "WORD_1"; break;
951   case SdwaSel::DWORD: O << "DWORD"; break;
952   default: llvm_unreachable("Invalid SDWA data select operand");
953   }
954 }
955 
956 void AMDGPUInstPrinter::printSDWADstSel(const MCInst *MI, unsigned OpNo,
957                                         const MCSubtargetInfo &STI,
958                                         raw_ostream &O) {
959   O << "dst_sel:";
960   printSDWASel(MI, OpNo, O);
961 }
962 
963 void AMDGPUInstPrinter::printSDWASrc0Sel(const MCInst *MI, unsigned OpNo,
964                                          const MCSubtargetInfo &STI,
965                                          raw_ostream &O) {
966   O << "src0_sel:";
967   printSDWASel(MI, OpNo, O);
968 }
969 
970 void AMDGPUInstPrinter::printSDWASrc1Sel(const MCInst *MI, unsigned OpNo,
971                                          const MCSubtargetInfo &STI,
972                                          raw_ostream &O) {
973   O << "src1_sel:";
974   printSDWASel(MI, OpNo, O);
975 }
976 
977 void AMDGPUInstPrinter::printSDWADstUnused(const MCInst *MI, unsigned OpNo,
978                                            const MCSubtargetInfo &STI,
979                                            raw_ostream &O) {
980   using namespace llvm::AMDGPU::SDWA;
981 
982   O << "dst_unused:";
983   unsigned Imm = MI->getOperand(OpNo).getImm();
984   switch (Imm) {
985   case DstUnused::UNUSED_PAD: O << "UNUSED_PAD"; break;
986   case DstUnused::UNUSED_SEXT: O << "UNUSED_SEXT"; break;
987   case DstUnused::UNUSED_PRESERVE: O << "UNUSED_PRESERVE"; break;
988   default: llvm_unreachable("Invalid SDWA dest_unused operand");
989   }
990 }
991 
992 void AMDGPUInstPrinter::printExpSrcN(const MCInst *MI, unsigned OpNo,
993                                      const MCSubtargetInfo &STI, raw_ostream &O,
994                                      unsigned N) {
995   unsigned Opc = MI->getOpcode();
996   int EnIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::en);
997   unsigned En = MI->getOperand(EnIdx).getImm();
998 
999   int ComprIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::compr);
1000 
1001   // If compr is set, print as src0, src0, src1, src1
1002   if (MI->getOperand(ComprIdx).getImm())
1003     OpNo = OpNo - N + N / 2;
1004 
1005   if (En & (1 << N))
1006     printRegOperand(MI->getOperand(OpNo).getReg(), O, MRI);
1007   else
1008     O << "off";
1009 }
1010 
1011 void AMDGPUInstPrinter::printExpSrc0(const MCInst *MI, unsigned OpNo,
1012                                      const MCSubtargetInfo &STI,
1013                                      raw_ostream &O) {
1014   printExpSrcN(MI, OpNo, STI, O, 0);
1015 }
1016 
1017 void AMDGPUInstPrinter::printExpSrc1(const MCInst *MI, unsigned OpNo,
1018                                      const MCSubtargetInfo &STI,
1019                                      raw_ostream &O) {
1020   printExpSrcN(MI, OpNo, STI, O, 1);
1021 }
1022 
1023 void AMDGPUInstPrinter::printExpSrc2(const MCInst *MI, unsigned OpNo,
1024                                      const MCSubtargetInfo &STI,
1025                                      raw_ostream &O) {
1026   printExpSrcN(MI, OpNo, STI, O, 2);
1027 }
1028 
1029 void AMDGPUInstPrinter::printExpSrc3(const MCInst *MI, unsigned OpNo,
1030                                      const MCSubtargetInfo &STI,
1031                                      raw_ostream &O) {
1032   printExpSrcN(MI, OpNo, STI, O, 3);
1033 }
1034 
1035 void AMDGPUInstPrinter::printExpTgt(const MCInst *MI, unsigned OpNo,
1036                                     const MCSubtargetInfo &STI,
1037                                     raw_ostream &O) {
1038   using namespace llvm::AMDGPU::Exp;
1039 
1040   // This is really a 6 bit field.
1041   unsigned Id = MI->getOperand(OpNo).getImm() & ((1 << 6) - 1);
1042 
1043   int Index;
1044   StringRef TgtName;
1045   if (getTgtName(Id, TgtName, Index) && isSupportedTgtId(Id, STI)) {
1046     O << ' ' << TgtName;
1047     if (Index >= 0)
1048       O << Index;
1049   } else {
1050     O << " invalid_target_" << Id;
1051   }
1052 }
1053 
1054 static bool allOpsDefaultValue(const int* Ops, int NumOps, int Mod,
1055                                bool IsPacked, bool HasDstSel) {
1056   int DefaultValue = IsPacked && (Mod == SISrcMods::OP_SEL_1);
1057 
1058   for (int I = 0; I < NumOps; ++I) {
1059     if (!!(Ops[I] & Mod) != DefaultValue)
1060       return false;
1061   }
1062 
1063   if (HasDstSel && (Ops[0] & SISrcMods::DST_OP_SEL) != 0)
1064     return false;
1065 
1066   return true;
1067 }
1068 
1069 void AMDGPUInstPrinter::printPackedModifier(const MCInst *MI,
1070                                             StringRef Name,
1071                                             unsigned Mod,
1072                                             raw_ostream &O) {
1073   unsigned Opc = MI->getOpcode();
1074   int NumOps = 0;
1075   int Ops[3];
1076 
1077   for (int OpName : { AMDGPU::OpName::src0_modifiers,
1078                       AMDGPU::OpName::src1_modifiers,
1079                       AMDGPU::OpName::src2_modifiers }) {
1080     int Idx = AMDGPU::getNamedOperandIdx(Opc, OpName);
1081     if (Idx == -1)
1082       break;
1083 
1084     Ops[NumOps++] = MI->getOperand(Idx).getImm();
1085   }
1086 
1087   const bool HasDstSel =
1088     NumOps > 0 &&
1089     Mod == SISrcMods::OP_SEL_0 &&
1090     MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::VOP3_OPSEL;
1091 
1092   const bool IsPacked =
1093     MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::IsPacked;
1094 
1095   if (allOpsDefaultValue(Ops, NumOps, Mod, IsPacked, HasDstSel))
1096     return;
1097 
1098   O << Name;
1099   for (int I = 0; I < NumOps; ++I) {
1100     if (I != 0)
1101       O << ',';
1102 
1103     O << !!(Ops[I] & Mod);
1104   }
1105 
1106   if (HasDstSel) {
1107     O << ',' << !!(Ops[0] & SISrcMods::DST_OP_SEL);
1108   }
1109 
1110   O << ']';
1111 }
1112 
1113 void AMDGPUInstPrinter::printOpSel(const MCInst *MI, unsigned,
1114                                    const MCSubtargetInfo &STI,
1115                                    raw_ostream &O) {
1116   unsigned Opc = MI->getOpcode();
1117   if (Opc == AMDGPU::V_PERMLANE16_B32_gfx10 ||
1118       Opc == AMDGPU::V_PERMLANEX16_B32_gfx10) {
1119     auto FIN = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers);
1120     auto BCN = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers);
1121     unsigned FI = !!(MI->getOperand(FIN).getImm() & SISrcMods::OP_SEL_0);
1122     unsigned BC = !!(MI->getOperand(BCN).getImm() & SISrcMods::OP_SEL_0);
1123     if (FI || BC)
1124       O << " op_sel:[" << FI << ',' << BC << ']';
1125     return;
1126   }
1127 
1128   printPackedModifier(MI, " op_sel:[", SISrcMods::OP_SEL_0, O);
1129 }
1130 
1131 void AMDGPUInstPrinter::printOpSelHi(const MCInst *MI, unsigned OpNo,
1132                                      const MCSubtargetInfo &STI,
1133                                      raw_ostream &O) {
1134   printPackedModifier(MI, " op_sel_hi:[", SISrcMods::OP_SEL_1, O);
1135 }
1136 
1137 void AMDGPUInstPrinter::printNegLo(const MCInst *MI, unsigned OpNo,
1138                                    const MCSubtargetInfo &STI,
1139                                    raw_ostream &O) {
1140   printPackedModifier(MI, " neg_lo:[", SISrcMods::NEG, O);
1141 }
1142 
1143 void AMDGPUInstPrinter::printNegHi(const MCInst *MI, unsigned OpNo,
1144                                    const MCSubtargetInfo &STI,
1145                                    raw_ostream &O) {
1146   printPackedModifier(MI, " neg_hi:[", SISrcMods::NEG_HI, O);
1147 }
1148 
1149 void AMDGPUInstPrinter::printInterpSlot(const MCInst *MI, unsigned OpNum,
1150                                         const MCSubtargetInfo &STI,
1151                                         raw_ostream &O) {
1152   unsigned Imm = MI->getOperand(OpNum).getImm();
1153   switch (Imm) {
1154   case 0:
1155     O << "p10";
1156     break;
1157   case 1:
1158     O << "p20";
1159     break;
1160   case 2:
1161     O << "p0";
1162     break;
1163   default:
1164     O << "invalid_param_" << Imm;
1165   }
1166 }
1167 
1168 void AMDGPUInstPrinter::printInterpAttr(const MCInst *MI, unsigned OpNum,
1169                                         const MCSubtargetInfo &STI,
1170                                         raw_ostream &O) {
1171   unsigned Attr = MI->getOperand(OpNum).getImm();
1172   O << "attr" << Attr;
1173 }
1174 
1175 void AMDGPUInstPrinter::printInterpAttrChan(const MCInst *MI, unsigned OpNum,
1176                                         const MCSubtargetInfo &STI,
1177                                         raw_ostream &O) {
1178   unsigned Chan = MI->getOperand(OpNum).getImm();
1179   O << '.' << "xyzw"[Chan & 0x3];
1180 }
1181 
1182 void AMDGPUInstPrinter::printVGPRIndexMode(const MCInst *MI, unsigned OpNo,
1183                                            const MCSubtargetInfo &STI,
1184                                            raw_ostream &O) {
1185   using namespace llvm::AMDGPU::VGPRIndexMode;
1186   unsigned Val = MI->getOperand(OpNo).getImm();
1187 
1188   if ((Val & ~ENABLE_MASK) != 0) {
1189     O << formatHex(static_cast<uint64_t>(Val));
1190   } else {
1191     O << "gpr_idx(";
1192     bool NeedComma = false;
1193     for (unsigned ModeId = ID_MIN; ModeId <= ID_MAX; ++ModeId) {
1194       if (Val & (1 << ModeId)) {
1195         if (NeedComma)
1196           O << ',';
1197         O << IdSymbolic[ModeId];
1198         NeedComma = true;
1199       }
1200     }
1201     O << ')';
1202   }
1203 }
1204 
1205 void AMDGPUInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo,
1206                                         const MCSubtargetInfo &STI,
1207                                         raw_ostream &O) {
1208   printOperand(MI, OpNo, STI, O);
1209   O  << ", ";
1210   printOperand(MI, OpNo + 1, STI, O);
1211 }
1212 
1213 void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
1214                                    raw_ostream &O, StringRef Asm,
1215                                    StringRef Default) {
1216   const MCOperand &Op = MI->getOperand(OpNo);
1217   assert(Op.isImm());
1218   if (Op.getImm() == 1) {
1219     O << Asm;
1220   } else {
1221     O << Default;
1222   }
1223 }
1224 
1225 void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
1226                                    raw_ostream &O, char Asm) {
1227   const MCOperand &Op = MI->getOperand(OpNo);
1228   assert(Op.isImm());
1229   if (Op.getImm() == 1)
1230     O << Asm;
1231 }
1232 
1233 void AMDGPUInstPrinter::printHigh(const MCInst *MI, unsigned OpNo,
1234                                   const MCSubtargetInfo &STI,
1235                                   raw_ostream &O) {
1236   printNamedBit(MI, OpNo, O, "high");
1237 }
1238 
1239 void AMDGPUInstPrinter::printClampSI(const MCInst *MI, unsigned OpNo,
1240                                      const MCSubtargetInfo &STI,
1241                                      raw_ostream &O) {
1242   printNamedBit(MI, OpNo, O, "clamp");
1243 }
1244 
1245 void AMDGPUInstPrinter::printOModSI(const MCInst *MI, unsigned OpNo,
1246                                     const MCSubtargetInfo &STI,
1247                                     raw_ostream &O) {
1248   int Imm = MI->getOperand(OpNo).getImm();
1249   if (Imm == SIOutMods::MUL2)
1250     O << " mul:2";
1251   else if (Imm == SIOutMods::MUL4)
1252     O << " mul:4";
1253   else if (Imm == SIOutMods::DIV2)
1254     O << " div:2";
1255 }
1256 
1257 void AMDGPUInstPrinter::printSendMsg(const MCInst *MI, unsigned OpNo,
1258                                      const MCSubtargetInfo &STI,
1259                                      raw_ostream &O) {
1260   using namespace llvm::AMDGPU::SendMsg;
1261 
1262   const unsigned Imm16 = MI->getOperand(OpNo).getImm();
1263 
1264   uint16_t MsgId;
1265   uint16_t OpId;
1266   uint16_t StreamId;
1267   decodeMsg(Imm16, MsgId, OpId, StreamId);
1268 
1269   if (isValidMsgId(MsgId, STI) &&
1270       isValidMsgOp(MsgId, OpId, STI) &&
1271       isValidMsgStream(MsgId, OpId, StreamId, STI)) {
1272     O << "sendmsg(" << getMsgName(MsgId);
1273     if (msgRequiresOp(MsgId)) {
1274       O << ", " << getMsgOpName(MsgId, OpId);
1275       if (msgSupportsStream(MsgId, OpId)) {
1276         O << ", " << StreamId;
1277       }
1278     }
1279     O << ')';
1280   } else if (encodeMsg(MsgId, OpId, StreamId) == Imm16) {
1281     O << "sendmsg(" << MsgId << ", " << OpId << ", " << StreamId << ')';
1282   } else {
1283     O << Imm16; // Unknown imm16 code.
1284   }
1285 }
1286 
1287 static void printSwizzleBitmask(const uint16_t AndMask,
1288                                 const uint16_t OrMask,
1289                                 const uint16_t XorMask,
1290                                 raw_ostream &O) {
1291   using namespace llvm::AMDGPU::Swizzle;
1292 
1293   uint16_t Probe0 = ((0            & AndMask) | OrMask) ^ XorMask;
1294   uint16_t Probe1 = ((BITMASK_MASK & AndMask) | OrMask) ^ XorMask;
1295 
1296   O << "\"";
1297 
1298   for (unsigned Mask = 1 << (BITMASK_WIDTH - 1); Mask > 0; Mask >>= 1) {
1299     uint16_t p0 = Probe0 & Mask;
1300     uint16_t p1 = Probe1 & Mask;
1301 
1302     if (p0 == p1) {
1303       if (p0 == 0) {
1304         O << "0";
1305       } else {
1306         O << "1";
1307       }
1308     } else {
1309       if (p0 == 0) {
1310         O << "p";
1311       } else {
1312         O << "i";
1313       }
1314     }
1315   }
1316 
1317   O << "\"";
1318 }
1319 
1320 void AMDGPUInstPrinter::printSwizzle(const MCInst *MI, unsigned OpNo,
1321                                      const MCSubtargetInfo &STI,
1322                                      raw_ostream &O) {
1323   using namespace llvm::AMDGPU::Swizzle;
1324 
1325   uint16_t Imm = MI->getOperand(OpNo).getImm();
1326   if (Imm == 0) {
1327     return;
1328   }
1329 
1330   O << " offset:";
1331 
1332   if ((Imm & QUAD_PERM_ENC_MASK) == QUAD_PERM_ENC) {
1333 
1334     O << "swizzle(" << IdSymbolic[ID_QUAD_PERM];
1335     for (unsigned I = 0; I < LANE_NUM; ++I) {
1336       O << ",";
1337       O << formatDec(Imm & LANE_MASK);
1338       Imm >>= LANE_SHIFT;
1339     }
1340     O << ")";
1341 
1342   } else if ((Imm & BITMASK_PERM_ENC_MASK) == BITMASK_PERM_ENC) {
1343 
1344     uint16_t AndMask = (Imm >> BITMASK_AND_SHIFT) & BITMASK_MASK;
1345     uint16_t OrMask  = (Imm >> BITMASK_OR_SHIFT)  & BITMASK_MASK;
1346     uint16_t XorMask = (Imm >> BITMASK_XOR_SHIFT) & BITMASK_MASK;
1347 
1348     if (AndMask == BITMASK_MAX &&
1349         OrMask == 0 &&
1350         countPopulation(XorMask) == 1) {
1351 
1352       O << "swizzle(" << IdSymbolic[ID_SWAP];
1353       O << ",";
1354       O << formatDec(XorMask);
1355       O << ")";
1356 
1357     } else if (AndMask == BITMASK_MAX &&
1358                OrMask == 0 && XorMask > 0 &&
1359                isPowerOf2_64(XorMask + 1)) {
1360 
1361       O << "swizzle(" << IdSymbolic[ID_REVERSE];
1362       O << ",";
1363       O << formatDec(XorMask + 1);
1364       O << ")";
1365 
1366     } else {
1367 
1368       uint16_t GroupSize = BITMASK_MAX - AndMask + 1;
1369       if (GroupSize > 1 &&
1370           isPowerOf2_64(GroupSize) &&
1371           OrMask < GroupSize &&
1372           XorMask == 0) {
1373 
1374         O << "swizzle(" << IdSymbolic[ID_BROADCAST];
1375         O << ",";
1376         O << formatDec(GroupSize);
1377         O << ",";
1378         O << formatDec(OrMask);
1379         O << ")";
1380 
1381       } else {
1382         O << "swizzle(" << IdSymbolic[ID_BITMASK_PERM];
1383         O << ",";
1384         printSwizzleBitmask(AndMask, OrMask, XorMask, O);
1385         O << ")";
1386       }
1387     }
1388   } else {
1389     printU16ImmDecOperand(MI, OpNo, O);
1390   }
1391 }
1392 
1393 void AMDGPUInstPrinter::printWaitFlag(const MCInst *MI, unsigned OpNo,
1394                                       const MCSubtargetInfo &STI,
1395                                       raw_ostream &O) {
1396   AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(STI.getCPU());
1397 
1398   unsigned SImm16 = MI->getOperand(OpNo).getImm();
1399   unsigned Vmcnt, Expcnt, Lgkmcnt;
1400   decodeWaitcnt(ISA, SImm16, Vmcnt, Expcnt, Lgkmcnt);
1401 
1402   bool IsDefaultVmcnt = Vmcnt == getVmcntBitMask(ISA);
1403   bool IsDefaultExpcnt = Expcnt == getExpcntBitMask(ISA);
1404   bool IsDefaultLgkmcnt = Lgkmcnt == getLgkmcntBitMask(ISA);
1405   bool PrintAll = IsDefaultVmcnt && IsDefaultExpcnt && IsDefaultLgkmcnt;
1406 
1407   bool NeedSpace = false;
1408 
1409   if (!IsDefaultVmcnt || PrintAll) {
1410     O << "vmcnt(" << Vmcnt << ')';
1411     NeedSpace = true;
1412   }
1413 
1414   if (!IsDefaultExpcnt || PrintAll) {
1415     if (NeedSpace)
1416       O << ' ';
1417     O << "expcnt(" << Expcnt << ')';
1418     NeedSpace = true;
1419   }
1420 
1421   if (!IsDefaultLgkmcnt || PrintAll) {
1422     if (NeedSpace)
1423       O << ' ';
1424     O << "lgkmcnt(" << Lgkmcnt << ')';
1425   }
1426 }
1427 
1428 void AMDGPUInstPrinter::printHwreg(const MCInst *MI, unsigned OpNo,
1429                                    const MCSubtargetInfo &STI, raw_ostream &O) {
1430   unsigned Id;
1431   unsigned Offset;
1432   unsigned Width;
1433 
1434   using namespace llvm::AMDGPU::Hwreg;
1435   unsigned Val = MI->getOperand(OpNo).getImm();
1436   decodeHwreg(Val, Id, Offset, Width);
1437   StringRef HwRegName = getHwreg(Id, STI);
1438 
1439   O << "hwreg(";
1440   if (!HwRegName.empty()) {
1441     O << HwRegName;
1442   } else {
1443     O << Id;
1444   }
1445   if (Width != WIDTH_DEFAULT_ || Offset != OFFSET_DEFAULT_) {
1446     O << ", " << Offset << ", " << Width;
1447   }
1448   O << ')';
1449 }
1450 
1451 void AMDGPUInstPrinter::printEndpgm(const MCInst *MI, unsigned OpNo,
1452                                     const MCSubtargetInfo &STI,
1453                                     raw_ostream &O) {
1454   uint16_t Imm = MI->getOperand(OpNo).getImm();
1455   if (Imm == 0) {
1456     return;
1457   }
1458 
1459   O << ' ' << formatDec(Imm);
1460 }
1461 
1462 #include "AMDGPUGenAsmWriter.inc"
1463