1 //===-- AMDGPUInstPrinter.cpp - AMDGPU MC Inst -> ASM ---------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 // \file
8 //===----------------------------------------------------------------------===//
9 
10 #include "AMDGPUInstPrinter.h"
11 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
12 #include "SIDefines.h"
13 #include "SIRegisterInfo.h"
14 #include "Utils/AMDGPUAsmUtils.h"
15 #include "Utils/AMDGPUBaseInfo.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCInstrDesc.h"
19 #include "llvm/MC/MCInstrInfo.h"
20 #include "llvm/MC/MCSubtargetInfo.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/TargetParser.h"
23 
24 using namespace llvm;
25 using namespace llvm::AMDGPU;
26 
27 static cl::opt<bool> Keep16BitSuffixes(
28   "amdgpu-keep-16-bit-reg-suffixes",
29   cl::desc("Keep .l and .h suffixes in asm for debugging purposes"),
30   cl::init(false),
31   cl::ReallyHidden);
32 
33 void AMDGPUInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
34   // FIXME: The current implementation of
35   // AsmParser::parseRegisterOrRegisterNumber in MC implies we either emit this
36   // as an integer or we provide a name which represents a physical register.
37   // For CFI instructions we really want to emit a name for the DWARF register
38   // instead, because there may be multiple DWARF registers corresponding to a
39   // single physical register. One case where this problem manifests is with
40   // wave32/wave64 where using the physical register name is ambiguous: if we
41   // write e.g. `.cfi_undefined v0` we lose information about the wavefront
42   // size which we need to encode the register in the final DWARF. Ideally we
43   // would extend MC to support parsing DWARF register names so we could do
44   // something like `.cfi_undefined dwarf_wave32_v0`. For now we just live with
45   // non-pretty DWARF register names in assembly text.
46   OS << RegNo;
47 }
48 
49 void AMDGPUInstPrinter::printInst(const MCInst *MI, uint64_t Address,
50                                   StringRef Annot, const MCSubtargetInfo &STI,
51                                   raw_ostream &OS) {
52   OS.flush();
53   printInstruction(MI, Address, STI, OS);
54   printAnnotation(OS, Annot);
55 }
56 
57 void AMDGPUInstPrinter::printU4ImmOperand(const MCInst *MI, unsigned OpNo,
58                                           const MCSubtargetInfo &STI,
59                                           raw_ostream &O) {
60   O << formatHex(MI->getOperand(OpNo).getImm() & 0xf);
61 }
62 
63 void AMDGPUInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo,
64                                           raw_ostream &O) {
65   O << formatHex(MI->getOperand(OpNo).getImm() & 0xff);
66 }
67 
68 void AMDGPUInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
69                                            const MCSubtargetInfo &STI,
70                                            raw_ostream &O) {
71   // It's possible to end up with a 32-bit literal used with a 16-bit operand
72   // with ignored high bits. Print as 32-bit anyway in that case.
73   int64_t Imm = MI->getOperand(OpNo).getImm();
74   if (isInt<16>(Imm) || isUInt<16>(Imm))
75     O << formatHex(static_cast<uint64_t>(Imm & 0xffff));
76   else
77     printU32ImmOperand(MI, OpNo, STI, O);
78 }
79 
80 void AMDGPUInstPrinter::printU4ImmDecOperand(const MCInst *MI, unsigned OpNo,
81                                              raw_ostream &O) {
82   O << formatDec(MI->getOperand(OpNo).getImm() & 0xf);
83 }
84 
85 void AMDGPUInstPrinter::printU8ImmDecOperand(const MCInst *MI, unsigned OpNo,
86                                              raw_ostream &O) {
87   O << formatDec(MI->getOperand(OpNo).getImm() & 0xff);
88 }
89 
90 void AMDGPUInstPrinter::printU16ImmDecOperand(const MCInst *MI, unsigned OpNo,
91                                               raw_ostream &O) {
92   O << formatDec(MI->getOperand(OpNo).getImm() & 0xffff);
93 }
94 
95 void AMDGPUInstPrinter::printU32ImmOperand(const MCInst *MI, unsigned OpNo,
96                                            const MCSubtargetInfo &STI,
97                                            raw_ostream &O) {
98   O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff);
99 }
100 
101 void AMDGPUInstPrinter::printNamedBit(const MCInst *MI, unsigned OpNo,
102                                       raw_ostream &O, StringRef BitName) {
103   if (MI->getOperand(OpNo).getImm()) {
104     O << ' ' << BitName;
105   }
106 }
107 
108 void AMDGPUInstPrinter::printOffen(const MCInst *MI, unsigned OpNo,
109                                    raw_ostream &O) {
110   printNamedBit(MI, OpNo, O, "offen");
111 }
112 
113 void AMDGPUInstPrinter::printIdxen(const MCInst *MI, unsigned OpNo,
114                                    raw_ostream &O) {
115   printNamedBit(MI, OpNo, O, "idxen");
116 }
117 
118 void AMDGPUInstPrinter::printAddr64(const MCInst *MI, unsigned OpNo,
119                                     raw_ostream &O) {
120   printNamedBit(MI, OpNo, O, "addr64");
121 }
122 
123 void AMDGPUInstPrinter::printOffset(const MCInst *MI, unsigned OpNo,
124                                     const MCSubtargetInfo &STI,
125                                     raw_ostream &O) {
126   uint16_t Imm = MI->getOperand(OpNo).getImm();
127   if (Imm != 0) {
128     O << " offset:";
129     printU16ImmDecOperand(MI, OpNo, O);
130   }
131 }
132 
133 void AMDGPUInstPrinter::printFlatOffset(const MCInst *MI, unsigned OpNo,
134                                         const MCSubtargetInfo &STI,
135                                         raw_ostream &O) {
136   uint16_t Imm = MI->getOperand(OpNo).getImm();
137   if (Imm != 0) {
138     O << " offset:";
139 
140     const MCInstrDesc &Desc = MII.get(MI->getOpcode());
141     bool IsFlatSeg = !(Desc.TSFlags &
142                        (SIInstrFlags::FlatGlobal | SIInstrFlags::FlatScratch));
143 
144     if (IsFlatSeg) { // Unsigned offset
145       printU16ImmDecOperand(MI, OpNo, O);
146     } else {         // Signed offset
147       if (AMDGPU::isGFX10Plus(STI)) {
148         O << formatDec(SignExtend32<12>(MI->getOperand(OpNo).getImm()));
149       } else {
150         O << formatDec(SignExtend32<13>(MI->getOperand(OpNo).getImm()));
151       }
152     }
153   }
154 }
155 
156 void AMDGPUInstPrinter::printOffset0(const MCInst *MI, unsigned OpNo,
157                                      const MCSubtargetInfo &STI,
158                                      raw_ostream &O) {
159   if (MI->getOperand(OpNo).getImm()) {
160     O << " offset0:";
161     printU8ImmDecOperand(MI, OpNo, O);
162   }
163 }
164 
165 void AMDGPUInstPrinter::printOffset1(const MCInst *MI, unsigned OpNo,
166                                      const MCSubtargetInfo &STI,
167                                      raw_ostream &O) {
168   if (MI->getOperand(OpNo).getImm()) {
169     O << " offset1:";
170     printU8ImmDecOperand(MI, OpNo, O);
171   }
172 }
173 
174 void AMDGPUInstPrinter::printSMRDOffset8(const MCInst *MI, unsigned OpNo,
175                                         const MCSubtargetInfo &STI,
176                                         raw_ostream &O) {
177   printU32ImmOperand(MI, OpNo, STI, O);
178 }
179 
180 void AMDGPUInstPrinter::printSMEMOffset(const MCInst *MI, unsigned OpNo,
181                                         const MCSubtargetInfo &STI,
182                                         raw_ostream &O) {
183   O << formatHex(MI->getOperand(OpNo).getImm());
184 }
185 
186 void AMDGPUInstPrinter::printSMEMOffsetMod(const MCInst *MI, unsigned OpNo,
187                                            const MCSubtargetInfo &STI,
188                                            raw_ostream &O) {
189   O << " offset:";
190   printSMEMOffset(MI, OpNo, STI, O);
191 }
192 
193 void AMDGPUInstPrinter::printSMRDLiteralOffset(const MCInst *MI, unsigned OpNo,
194                                                const MCSubtargetInfo &STI,
195                                                raw_ostream &O) {
196   printU32ImmOperand(MI, OpNo, STI, O);
197 }
198 
199 void AMDGPUInstPrinter::printGDS(const MCInst *MI, unsigned OpNo,
200                                  const MCSubtargetInfo &STI, raw_ostream &O) {
201   printNamedBit(MI, OpNo, O, "gds");
202 }
203 
204 void AMDGPUInstPrinter::printCPol(const MCInst *MI, unsigned OpNo,
205                                   const MCSubtargetInfo &STI, raw_ostream &O) {
206   auto Imm = MI->getOperand(OpNo).getImm();
207   if (Imm & CPol::GLC)
208     O << ((AMDGPU::isGFX940(STI) &&
209            !(MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::SMRD)) ? " sc0"
210                                                                      : " glc");
211   if (Imm & CPol::SLC)
212     O << (AMDGPU::isGFX940(STI) ? " nt" : " slc");
213   if ((Imm & CPol::DLC) && AMDGPU::isGFX10Plus(STI))
214     O << " dlc";
215   if ((Imm & CPol::SCC) && AMDGPU::isGFX90A(STI))
216     O << (AMDGPU::isGFX940(STI) ? " sc1" : " scc");
217   if (Imm & ~CPol::ALL)
218     O << " /* unexpected cache policy bit */";
219 }
220 
221 void AMDGPUInstPrinter::printSWZ(const MCInst *MI, unsigned OpNo,
222                                  const MCSubtargetInfo &STI, raw_ostream &O) {
223 }
224 
225 void AMDGPUInstPrinter::printTFE(const MCInst *MI, unsigned OpNo,
226                                  const MCSubtargetInfo &STI, raw_ostream &O) {
227   printNamedBit(MI, OpNo, O, "tfe");
228 }
229 
230 void AMDGPUInstPrinter::printDMask(const MCInst *MI, unsigned OpNo,
231                                    const MCSubtargetInfo &STI, raw_ostream &O) {
232   if (MI->getOperand(OpNo).getImm()) {
233     O << " dmask:";
234     printU16ImmOperand(MI, OpNo, STI, O);
235   }
236 }
237 
238 void AMDGPUInstPrinter::printDim(const MCInst *MI, unsigned OpNo,
239                                  const MCSubtargetInfo &STI, raw_ostream &O) {
240   unsigned Dim = MI->getOperand(OpNo).getImm();
241   O << " dim:SQ_RSRC_IMG_";
242 
243   const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfoByEncoding(Dim);
244   if (DimInfo)
245     O << DimInfo->AsmSuffix;
246   else
247     O << Dim;
248 }
249 
250 void AMDGPUInstPrinter::printUNorm(const MCInst *MI, unsigned OpNo,
251                                    const MCSubtargetInfo &STI, raw_ostream &O) {
252   printNamedBit(MI, OpNo, O, "unorm");
253 }
254 
255 void AMDGPUInstPrinter::printDA(const MCInst *MI, unsigned OpNo,
256                                 const MCSubtargetInfo &STI, raw_ostream &O) {
257   printNamedBit(MI, OpNo, O, "da");
258 }
259 
260 void AMDGPUInstPrinter::printR128A16(const MCInst *MI, unsigned OpNo,
261                                   const MCSubtargetInfo &STI, raw_ostream &O) {
262   if (STI.hasFeature(AMDGPU::FeatureR128A16))
263     printNamedBit(MI, OpNo, O, "a16");
264   else
265     printNamedBit(MI, OpNo, O, "r128");
266 }
267 
268 void AMDGPUInstPrinter::printGFX10A16(const MCInst *MI, unsigned OpNo,
269                                   const MCSubtargetInfo &STI, raw_ostream &O) {
270   printNamedBit(MI, OpNo, O, "a16");
271 }
272 
273 void AMDGPUInstPrinter::printLWE(const MCInst *MI, unsigned OpNo,
274                                  const MCSubtargetInfo &STI, raw_ostream &O) {
275   printNamedBit(MI, OpNo, O, "lwe");
276 }
277 
278 void AMDGPUInstPrinter::printD16(const MCInst *MI, unsigned OpNo,
279                                  const MCSubtargetInfo &STI, raw_ostream &O) {
280   printNamedBit(MI, OpNo, O, "d16");
281 }
282 
283 void AMDGPUInstPrinter::printExpCompr(const MCInst *MI, unsigned OpNo,
284                                       const MCSubtargetInfo &STI,
285                                       raw_ostream &O) {
286   printNamedBit(MI, OpNo, O, "compr");
287 }
288 
289 void AMDGPUInstPrinter::printExpVM(const MCInst *MI, unsigned OpNo,
290                                    const MCSubtargetInfo &STI,
291                                    raw_ostream &O) {
292   printNamedBit(MI, OpNo, O, "vm");
293 }
294 
295 void AMDGPUInstPrinter::printFORMAT(const MCInst *MI, unsigned OpNo,
296                                     const MCSubtargetInfo &STI,
297                                     raw_ostream &O) {
298 }
299 
300 void AMDGPUInstPrinter::printSymbolicFormat(const MCInst *MI,
301                                             const MCSubtargetInfo &STI,
302                                             raw_ostream &O) {
303   using namespace llvm::AMDGPU::MTBUFFormat;
304 
305   int OpNo =
306     AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::format);
307   assert(OpNo != -1);
308 
309   unsigned Val = MI->getOperand(OpNo).getImm();
310   if (AMDGPU::isGFX10Plus(STI)) {
311     if (Val == UFMT_DEFAULT)
312       return;
313     if (isValidUnifiedFormat(Val, STI)) {
314       O << " format:[" << getUnifiedFormatName(Val, STI) << ']';
315     } else {
316       O << " format:" << Val;
317     }
318   } else {
319     if (Val == DFMT_NFMT_DEFAULT)
320       return;
321     if (isValidDfmtNfmt(Val, STI)) {
322       unsigned Dfmt;
323       unsigned Nfmt;
324       decodeDfmtNfmt(Val, Dfmt, Nfmt);
325       O << " format:[";
326       if (Dfmt != DFMT_DEFAULT) {
327         O << getDfmtName(Dfmt);
328         if (Nfmt != NFMT_DEFAULT) {
329           O << ',';
330         }
331       }
332       if (Nfmt != NFMT_DEFAULT) {
333         O << getNfmtName(Nfmt, STI);
334       }
335       O << ']';
336     } else {
337       O << " format:" << Val;
338     }
339   }
340 }
341 
342 void AMDGPUInstPrinter::printRegOperand(unsigned RegNo, raw_ostream &O,
343                                         const MCRegisterInfo &MRI) {
344 #if !defined(NDEBUG)
345   switch (RegNo) {
346   case AMDGPU::FP_REG:
347   case AMDGPU::SP_REG:
348   case AMDGPU::PRIVATE_RSRC_REG:
349     llvm_unreachable("pseudo-register should not ever be emitted");
350   case AMDGPU::SCC:
351     llvm_unreachable("pseudo scc should not ever be emitted");
352   default:
353     break;
354   }
355 #endif
356 
357   StringRef RegName(getRegisterName(RegNo));
358   if (!Keep16BitSuffixes)
359     if (!RegName.consume_back(".l"))
360       RegName.consume_back(".h");
361 
362   O << RegName;
363 }
364 
365 void AMDGPUInstPrinter::printVOPDst(const MCInst *MI, unsigned OpNo,
366                                     const MCSubtargetInfo &STI,
367                                     raw_ostream &O) {
368   auto Opcode = MI->getOpcode();
369   auto Flags = MII.get(Opcode).TSFlags;
370 
371   if (OpNo == 0) {
372     if (Flags & SIInstrFlags::VOP3) {
373       if (!getVOP3IsSingle(Opcode))
374         O << "_e64";
375     } else if (Flags & SIInstrFlags::DPP) {
376       O << "_dpp";
377     } else if (Flags & SIInstrFlags::SDWA) {
378       O << "_sdwa";
379     } else if (((Flags & SIInstrFlags::VOP1) && !getVOP1IsSingle(Opcode)) ||
380                ((Flags & SIInstrFlags::VOP2) && !getVOP2IsSingle(Opcode))) {
381       O << "_e32";
382     }
383     O << " ";
384   }
385 
386   printOperand(MI, OpNo, STI, O);
387 
388   // Print default vcc/vcc_lo operand.
389   switch (Opcode) {
390   default: break;
391 
392   case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10:
393   case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10:
394   case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10:
395   case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10:
396   case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10:
397   case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10:
398   case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10:
399   case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10:
400   case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10:
401   case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10:
402   case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10:
403   case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10:
404     printDefaultVccOperand(1, STI, O);
405     break;
406   }
407 }
408 
409 void AMDGPUInstPrinter::printVINTRPDst(const MCInst *MI, unsigned OpNo,
410                                        const MCSubtargetInfo &STI, raw_ostream &O) {
411   if (AMDGPU::isSI(STI) || AMDGPU::isCI(STI))
412     O << " ";
413   else
414     O << "_e32 ";
415 
416   printOperand(MI, OpNo, STI, O);
417 }
418 
419 void AMDGPUInstPrinter::printImmediateInt16(uint32_t Imm,
420                                             const MCSubtargetInfo &STI,
421                                             raw_ostream &O) {
422   int16_t SImm = static_cast<int16_t>(Imm);
423   if (isInlinableIntLiteral(SImm)) {
424     O << SImm;
425   } else {
426     uint64_t Imm16 = static_cast<uint16_t>(Imm);
427     O << formatHex(Imm16);
428   }
429 }
430 
431 void AMDGPUInstPrinter::printImmediate16(uint32_t Imm,
432                                          const MCSubtargetInfo &STI,
433                                          raw_ostream &O) {
434   int16_t SImm = static_cast<int16_t>(Imm);
435   if (isInlinableIntLiteral(SImm)) {
436     O << SImm;
437     return;
438   }
439 
440   if (Imm == 0x3C00)
441     O<< "1.0";
442   else if (Imm == 0xBC00)
443     O<< "-1.0";
444   else if (Imm == 0x3800)
445     O<< "0.5";
446   else if (Imm == 0xB800)
447     O<< "-0.5";
448   else if (Imm == 0x4000)
449     O<< "2.0";
450   else if (Imm == 0xC000)
451     O<< "-2.0";
452   else if (Imm == 0x4400)
453     O<< "4.0";
454   else if (Imm == 0xC400)
455     O<< "-4.0";
456   else if (Imm == 0x3118 &&
457            STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]) {
458     O << "0.15915494";
459   } else {
460     uint64_t Imm16 = static_cast<uint16_t>(Imm);
461     O << formatHex(Imm16);
462   }
463 }
464 
465 void AMDGPUInstPrinter::printImmediateV216(uint32_t Imm,
466                                            const MCSubtargetInfo &STI,
467                                            raw_ostream &O) {
468   uint16_t Lo16 = static_cast<uint16_t>(Imm);
469   printImmediate16(Lo16, STI, O);
470 }
471 
472 void AMDGPUInstPrinter::printImmediate32(uint32_t Imm,
473                                          const MCSubtargetInfo &STI,
474                                          raw_ostream &O) {
475   int32_t SImm = static_cast<int32_t>(Imm);
476   if (SImm >= -16 && SImm <= 64) {
477     O << SImm;
478     return;
479   }
480 
481   if (Imm == FloatToBits(0.0f))
482     O << "0.0";
483   else if (Imm == FloatToBits(1.0f))
484     O << "1.0";
485   else if (Imm == FloatToBits(-1.0f))
486     O << "-1.0";
487   else if (Imm == FloatToBits(0.5f))
488     O << "0.5";
489   else if (Imm == FloatToBits(-0.5f))
490     O << "-0.5";
491   else if (Imm == FloatToBits(2.0f))
492     O << "2.0";
493   else if (Imm == FloatToBits(-2.0f))
494     O << "-2.0";
495   else if (Imm == FloatToBits(4.0f))
496     O << "4.0";
497   else if (Imm == FloatToBits(-4.0f))
498     O << "-4.0";
499   else if (Imm == 0x3e22f983 &&
500            STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
501     O << "0.15915494";
502   else
503     O << formatHex(static_cast<uint64_t>(Imm));
504 }
505 
506 void AMDGPUInstPrinter::printImmediate64(uint64_t Imm,
507                                          const MCSubtargetInfo &STI,
508                                          raw_ostream &O) {
509   int64_t SImm = static_cast<int64_t>(Imm);
510   if (SImm >= -16 && SImm <= 64) {
511     O << SImm;
512     return;
513   }
514 
515   if (Imm == DoubleToBits(0.0))
516     O << "0.0";
517   else if (Imm == DoubleToBits(1.0))
518     O << "1.0";
519   else if (Imm == DoubleToBits(-1.0))
520     O << "-1.0";
521   else if (Imm == DoubleToBits(0.5))
522     O << "0.5";
523   else if (Imm == DoubleToBits(-0.5))
524     O << "-0.5";
525   else if (Imm == DoubleToBits(2.0))
526     O << "2.0";
527   else if (Imm == DoubleToBits(-2.0))
528     O << "-2.0";
529   else if (Imm == DoubleToBits(4.0))
530     O << "4.0";
531   else if (Imm == DoubleToBits(-4.0))
532     O << "-4.0";
533   else if (Imm == 0x3fc45f306dc9c882 &&
534            STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
535     O << "0.15915494309189532";
536   else {
537     assert(isUInt<32>(Imm) || Imm == 0x3fc45f306dc9c882);
538 
539     // In rare situations, we will have a 32-bit literal in a 64-bit
540     // operand. This is technically allowed for the encoding of s_mov_b64.
541     O << formatHex(static_cast<uint64_t>(Imm));
542   }
543 }
544 
545 void AMDGPUInstPrinter::printBLGP(const MCInst *MI, unsigned OpNo,
546                                   const MCSubtargetInfo &STI,
547                                   raw_ostream &O) {
548   unsigned Imm = MI->getOperand(OpNo).getImm();
549   if (!Imm)
550     return;
551 
552   if (AMDGPU::isGFX940(STI)) {
553     switch (MI->getOpcode()) {
554     case AMDGPU::V_MFMA_F64_16X16X4F64_gfx940_acd:
555     case AMDGPU::V_MFMA_F64_16X16X4F64_gfx940_vcd:
556     case AMDGPU::V_MFMA_F64_4X4X4F64_gfx940_acd:
557     case AMDGPU::V_MFMA_F64_4X4X4F64_gfx940_vcd:
558       O << " neg:[" << (Imm & 1) << ',' << ((Imm >> 1) & 1) << ','
559         << ((Imm >> 2) & 1) << ']';
560       return;
561     }
562   }
563 
564   O << " blgp:" << Imm;
565 }
566 
567 void AMDGPUInstPrinter::printCBSZ(const MCInst *MI, unsigned OpNo,
568                                   const MCSubtargetInfo &STI,
569                                   raw_ostream &O) {
570   unsigned Imm = MI->getOperand(OpNo).getImm();
571   if (!Imm)
572     return;
573 
574   O << " cbsz:" << Imm;
575 }
576 
577 void AMDGPUInstPrinter::printABID(const MCInst *MI, unsigned OpNo,
578                                   const MCSubtargetInfo &STI,
579                                   raw_ostream &O) {
580   unsigned Imm = MI->getOperand(OpNo).getImm();
581   if (!Imm)
582     return;
583 
584   O << " abid:" << Imm;
585 }
586 
587 void AMDGPUInstPrinter::printDefaultVccOperand(unsigned OpNo,
588                                                const MCSubtargetInfo &STI,
589                                                raw_ostream &O) {
590   if (OpNo > 0)
591     O << ", ";
592   printRegOperand(STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ?
593                   AMDGPU::VCC : AMDGPU::VCC_LO, O, MRI);
594   if (OpNo == 0)
595     O << ", ";
596 }
597 
598 void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
599                                      const MCSubtargetInfo &STI,
600                                      raw_ostream &O) {
601   // Print default vcc/vcc_lo operand of VOPC.
602   const MCInstrDesc &Desc = MII.get(MI->getOpcode());
603   if (OpNo == 0 && (Desc.TSFlags & SIInstrFlags::VOPC) &&
604       (Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC) ||
605        Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC_LO)))
606     printDefaultVccOperand(OpNo, STI, O);
607 
608   if (OpNo >= MI->getNumOperands()) {
609     O << "/*Missing OP" << OpNo << "*/";
610     return;
611   }
612 
613   const MCOperand &Op = MI->getOperand(OpNo);
614   if (Op.isReg()) {
615     printRegOperand(Op.getReg(), O, MRI);
616   } else if (Op.isImm()) {
617     const uint8_t OpTy = Desc.OpInfo[OpNo].OperandType;
618     switch (OpTy) {
619     case AMDGPU::OPERAND_REG_IMM_INT32:
620     case AMDGPU::OPERAND_REG_IMM_FP32:
621     case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED:
622     case AMDGPU::OPERAND_REG_INLINE_C_INT32:
623     case AMDGPU::OPERAND_REG_INLINE_C_FP32:
624     case AMDGPU::OPERAND_REG_INLINE_AC_INT32:
625     case AMDGPU::OPERAND_REG_INLINE_AC_FP32:
626     case AMDGPU::OPERAND_REG_IMM_V2INT32:
627     case AMDGPU::OPERAND_REG_IMM_V2FP32:
628     case AMDGPU::OPERAND_REG_INLINE_C_V2INT32:
629     case AMDGPU::OPERAND_REG_INLINE_C_V2FP32:
630     case MCOI::OPERAND_IMMEDIATE:
631       printImmediate32(Op.getImm(), STI, O);
632       break;
633     case AMDGPU::OPERAND_REG_IMM_INT64:
634     case AMDGPU::OPERAND_REG_IMM_FP64:
635     case AMDGPU::OPERAND_REG_INLINE_C_INT64:
636     case AMDGPU::OPERAND_REG_INLINE_C_FP64:
637     case AMDGPU::OPERAND_REG_INLINE_AC_FP64:
638       printImmediate64(Op.getImm(), STI, O);
639       break;
640     case AMDGPU::OPERAND_REG_INLINE_C_INT16:
641     case AMDGPU::OPERAND_REG_INLINE_AC_INT16:
642     case AMDGPU::OPERAND_REG_IMM_INT16:
643       printImmediateInt16(Op.getImm(), STI, O);
644       break;
645     case AMDGPU::OPERAND_REG_INLINE_C_FP16:
646     case AMDGPU::OPERAND_REG_INLINE_AC_FP16:
647     case AMDGPU::OPERAND_REG_IMM_FP16:
648     case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED:
649       printImmediate16(Op.getImm(), STI, O);
650       break;
651     case AMDGPU::OPERAND_REG_IMM_V2INT16:
652     case AMDGPU::OPERAND_REG_IMM_V2FP16:
653       if (!isUInt<16>(Op.getImm()) &&
654           STI.getFeatureBits()[AMDGPU::FeatureVOP3Literal]) {
655         printImmediate32(Op.getImm(), STI, O);
656         break;
657       }
658 
659       //  Deal with 16-bit FP inline immediates not working.
660       if (OpTy == AMDGPU::OPERAND_REG_IMM_V2FP16) {
661         printImmediate16(static_cast<uint16_t>(Op.getImm()), STI, O);
662         break;
663       }
664       LLVM_FALLTHROUGH;
665     case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
666     case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:
667       printImmediateInt16(static_cast<uint16_t>(Op.getImm()), STI, O);
668       break;
669     case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
670     case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16:
671       printImmediateV216(Op.getImm(), STI, O);
672       break;
673     case MCOI::OPERAND_UNKNOWN:
674     case MCOI::OPERAND_PCREL:
675       O << formatDec(Op.getImm());
676       break;
677     case MCOI::OPERAND_REGISTER:
678       // FIXME: This should be removed and handled somewhere else. Seems to come
679       // from a disassembler bug.
680       O << "/*invalid immediate*/";
681       break;
682     default:
683       // We hit this for the immediate instruction bits that don't yet have a
684       // custom printer.
685       llvm_unreachable("unexpected immediate operand type");
686     }
687   } else if (Op.isDFPImm()) {
688     double Value = bit_cast<double>(Op.getDFPImm());
689     // We special case 0.0 because otherwise it will be printed as an integer.
690     if (Value == 0.0)
691       O << "0.0";
692     else {
693       const MCInstrDesc &Desc = MII.get(MI->getOpcode());
694       int RCID = Desc.OpInfo[OpNo].RegClass;
695       unsigned RCBits = AMDGPU::getRegBitWidth(MRI.getRegClass(RCID));
696       if (RCBits == 32)
697         printImmediate32(FloatToBits(Value), STI, O);
698       else if (RCBits == 64)
699         printImmediate64(DoubleToBits(Value), STI, O);
700       else
701         llvm_unreachable("Invalid register class size");
702     }
703   } else if (Op.isExpr()) {
704     const MCExpr *Exp = Op.getExpr();
705     Exp->print(O, &MAI);
706   } else {
707     O << "/*INV_OP*/";
708   }
709 
710   // Print default vcc/vcc_lo operand of v_cndmask_b32_e32.
711   switch (MI->getOpcode()) {
712   default: break;
713 
714   case AMDGPU::V_CNDMASK_B32_e32_gfx10:
715   case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10:
716   case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10:
717   case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10:
718   case AMDGPU::V_CNDMASK_B32_dpp_gfx10:
719   case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10:
720   case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10:
721   case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10:
722   case AMDGPU::V_CNDMASK_B32_dpp8_gfx10:
723   case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10:
724   case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10:
725   case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10:
726 
727   case AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7:
728   case AMDGPU::V_CNDMASK_B32_e32_vi:
729     if ((int)OpNo == AMDGPU::getNamedOperandIdx(MI->getOpcode(),
730                                                 AMDGPU::OpName::src1))
731       printDefaultVccOperand(OpNo, STI, O);
732     break;
733   }
734 
735   if (Desc.TSFlags & SIInstrFlags::MTBUF) {
736     int SOffsetIdx =
737       AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::soffset);
738     assert(SOffsetIdx != -1);
739     if ((int)OpNo == SOffsetIdx)
740       printSymbolicFormat(MI, STI, O);
741   }
742 }
743 
744 void AMDGPUInstPrinter::printOperandAndFPInputMods(const MCInst *MI,
745                                                    unsigned OpNo,
746                                                    const MCSubtargetInfo &STI,
747                                                    raw_ostream &O) {
748   unsigned InputModifiers = MI->getOperand(OpNo).getImm();
749 
750   // Use 'neg(...)' instead of '-' to avoid ambiguity.
751   // This is important for integer literals because
752   // -1 is not the same value as neg(1).
753   bool NegMnemo = false;
754 
755   if (InputModifiers & SISrcMods::NEG) {
756     if (OpNo + 1 < MI->getNumOperands() &&
757         (InputModifiers & SISrcMods::ABS) == 0) {
758       const MCOperand &Op = MI->getOperand(OpNo + 1);
759       NegMnemo = Op.isImm() || Op.isDFPImm();
760     }
761     if (NegMnemo) {
762       O << "neg(";
763     } else {
764       O << '-';
765     }
766   }
767 
768   if (InputModifiers & SISrcMods::ABS)
769     O << '|';
770   printOperand(MI, OpNo + 1, STI, O);
771   if (InputModifiers & SISrcMods::ABS)
772     O << '|';
773 
774   if (NegMnemo) {
775     O << ')';
776   }
777 }
778 
779 void AMDGPUInstPrinter::printOperandAndIntInputMods(const MCInst *MI,
780                                                     unsigned OpNo,
781                                                     const MCSubtargetInfo &STI,
782                                                     raw_ostream &O) {
783   unsigned InputModifiers = MI->getOperand(OpNo).getImm();
784   if (InputModifiers & SISrcMods::SEXT)
785     O << "sext(";
786   printOperand(MI, OpNo + 1, STI, O);
787   if (InputModifiers & SISrcMods::SEXT)
788     O << ')';
789 
790   // Print default vcc/vcc_lo operand of VOP2b.
791   switch (MI->getOpcode()) {
792   default: break;
793 
794   case AMDGPU::V_CNDMASK_B32_sdwa_gfx10:
795   case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10:
796   case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10:
797   case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10:
798     if ((int)OpNo + 1 == AMDGPU::getNamedOperandIdx(MI->getOpcode(),
799                                                     AMDGPU::OpName::src1))
800       printDefaultVccOperand(OpNo, STI, O);
801     break;
802   }
803 }
804 
805 void AMDGPUInstPrinter::printDPP8(const MCInst *MI, unsigned OpNo,
806                                   const MCSubtargetInfo &STI,
807                                   raw_ostream &O) {
808   if (!AMDGPU::isGFX10Plus(STI))
809     llvm_unreachable("dpp8 is not supported on ASICs earlier than GFX10");
810 
811   unsigned Imm = MI->getOperand(OpNo).getImm();
812   O << "dpp8:[" << formatDec(Imm & 0x7);
813   for (size_t i = 1; i < 8; ++i) {
814     O << ',' << formatDec((Imm >> (3 * i)) & 0x7);
815   }
816   O << ']';
817 }
818 
819 void AMDGPUInstPrinter::printDPPCtrl(const MCInst *MI, unsigned OpNo,
820                                      const MCSubtargetInfo &STI,
821                                      raw_ostream &O) {
822   using namespace AMDGPU::DPP;
823 
824   unsigned Imm = MI->getOperand(OpNo).getImm();
825   const MCInstrDesc &Desc = MII.get(MI->getOpcode());
826   int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
827                                            AMDGPU::OpName::src0);
828 
829   if (Src0Idx >= 0 &&
830       Desc.OpInfo[Src0Idx].RegClass == AMDGPU::VReg_64RegClassID &&
831       !AMDGPU::isLegal64BitDPPControl(Imm)) {
832     O << " /* 64 bit dpp only supports row_newbcast */";
833     return;
834   } else if (Imm <= DppCtrl::QUAD_PERM_LAST) {
835     O << "quad_perm:[";
836     O << formatDec(Imm & 0x3)         << ',';
837     O << formatDec((Imm & 0xc)  >> 2) << ',';
838     O << formatDec((Imm & 0x30) >> 4) << ',';
839     O << formatDec((Imm & 0xc0) >> 6) << ']';
840   } else if ((Imm >= DppCtrl::ROW_SHL_FIRST) &&
841              (Imm <= DppCtrl::ROW_SHL_LAST)) {
842     O << "row_shl:";
843     printU4ImmDecOperand(MI, OpNo, O);
844   } else if ((Imm >= DppCtrl::ROW_SHR_FIRST) &&
845              (Imm <= DppCtrl::ROW_SHR_LAST)) {
846     O << "row_shr:";
847     printU4ImmDecOperand(MI, OpNo, O);
848   } else if ((Imm >= DppCtrl::ROW_ROR_FIRST) &&
849              (Imm <= DppCtrl::ROW_ROR_LAST)) {
850     O << "row_ror:";
851     printU4ImmDecOperand(MI, OpNo, O);
852   } else if (Imm == DppCtrl::WAVE_SHL1) {
853     if (AMDGPU::isGFX10Plus(STI)) {
854       O << "/* wave_shl is not supported starting from GFX10 */";
855       return;
856     }
857     O << "wave_shl:1";
858   } else if (Imm == DppCtrl::WAVE_ROL1) {
859     if (AMDGPU::isGFX10Plus(STI)) {
860       O << "/* wave_rol is not supported starting from GFX10 */";
861       return;
862     }
863     O << "wave_rol:1";
864   } else if (Imm == DppCtrl::WAVE_SHR1) {
865     if (AMDGPU::isGFX10Plus(STI)) {
866       O << "/* wave_shr is not supported starting from GFX10 */";
867       return;
868     }
869     O << "wave_shr:1";
870   } else if (Imm == DppCtrl::WAVE_ROR1) {
871     if (AMDGPU::isGFX10Plus(STI)) {
872       O << "/* wave_ror is not supported starting from GFX10 */";
873       return;
874     }
875     O << "wave_ror:1";
876   } else if (Imm == DppCtrl::ROW_MIRROR) {
877     O << "row_mirror";
878   } else if (Imm == DppCtrl::ROW_HALF_MIRROR) {
879     O << "row_half_mirror";
880   } else if (Imm == DppCtrl::BCAST15) {
881     if (AMDGPU::isGFX10Plus(STI)) {
882       O << "/* row_bcast is not supported starting from GFX10 */";
883       return;
884     }
885     O << "row_bcast:15";
886   } else if (Imm == DppCtrl::BCAST31) {
887     if (AMDGPU::isGFX10Plus(STI)) {
888       O << "/* row_bcast is not supported starting from GFX10 */";
889       return;
890     }
891     O << "row_bcast:31";
892   } else if ((Imm >= DppCtrl::ROW_SHARE_FIRST) &&
893              (Imm <= DppCtrl::ROW_SHARE_LAST)) {
894     if (AMDGPU::isGFX90A(STI)) {
895       O << "row_newbcast:";
896     } else if (AMDGPU::isGFX10Plus(STI)) {
897       O << "row_share:";
898     } else {
899       O << " /* row_newbcast/row_share is not supported on ASICs earlier "
900            "than GFX90A/GFX10 */";
901       return;
902     }
903     printU4ImmDecOperand(MI, OpNo, O);
904   } else if ((Imm >= DppCtrl::ROW_XMASK_FIRST) &&
905              (Imm <= DppCtrl::ROW_XMASK_LAST)) {
906     if (!AMDGPU::isGFX10Plus(STI)) {
907       O << "/* row_xmask is not supported on ASICs earlier than GFX10 */";
908       return;
909     }
910     O << "row_xmask:";
911     printU4ImmDecOperand(MI, OpNo, O);
912   } else {
913     O << "/* Invalid dpp_ctrl value */";
914   }
915 }
916 
917 void AMDGPUInstPrinter::printRowMask(const MCInst *MI, unsigned OpNo,
918                                      const MCSubtargetInfo &STI,
919                                      raw_ostream &O) {
920   O << " row_mask:";
921   printU4ImmOperand(MI, OpNo, STI, O);
922 }
923 
924 void AMDGPUInstPrinter::printBankMask(const MCInst *MI, unsigned OpNo,
925                                       const MCSubtargetInfo &STI,
926                                       raw_ostream &O) {
927   O << " bank_mask:";
928   printU4ImmOperand(MI, OpNo, STI, O);
929 }
930 
931 void AMDGPUInstPrinter::printBoundCtrl(const MCInst *MI, unsigned OpNo,
932                                        const MCSubtargetInfo &STI,
933                                        raw_ostream &O) {
934   unsigned Imm = MI->getOperand(OpNo).getImm();
935   if (Imm) {
936     O << " bound_ctrl:1";
937   }
938 }
939 
940 void AMDGPUInstPrinter::printFI(const MCInst *MI, unsigned OpNo,
941                                 const MCSubtargetInfo &STI,
942                                 raw_ostream &O) {
943   using namespace llvm::AMDGPU::DPP;
944   unsigned Imm = MI->getOperand(OpNo).getImm();
945   if (Imm == DPP_FI_1 || Imm == DPP8_FI_1) {
946     O << " fi:1";
947   }
948 }
949 
950 void AMDGPUInstPrinter::printSDWASel(const MCInst *MI, unsigned OpNo,
951                                      raw_ostream &O) {
952   using namespace llvm::AMDGPU::SDWA;
953 
954   unsigned Imm = MI->getOperand(OpNo).getImm();
955   switch (Imm) {
956   case SdwaSel::BYTE_0: O << "BYTE_0"; break;
957   case SdwaSel::BYTE_1: O << "BYTE_1"; break;
958   case SdwaSel::BYTE_2: O << "BYTE_2"; break;
959   case SdwaSel::BYTE_3: O << "BYTE_3"; break;
960   case SdwaSel::WORD_0: O << "WORD_0"; break;
961   case SdwaSel::WORD_1: O << "WORD_1"; break;
962   case SdwaSel::DWORD: O << "DWORD"; break;
963   default: llvm_unreachable("Invalid SDWA data select operand");
964   }
965 }
966 
967 void AMDGPUInstPrinter::printSDWADstSel(const MCInst *MI, unsigned OpNo,
968                                         const MCSubtargetInfo &STI,
969                                         raw_ostream &O) {
970   O << "dst_sel:";
971   printSDWASel(MI, OpNo, O);
972 }
973 
974 void AMDGPUInstPrinter::printSDWASrc0Sel(const MCInst *MI, unsigned OpNo,
975                                          const MCSubtargetInfo &STI,
976                                          raw_ostream &O) {
977   O << "src0_sel:";
978   printSDWASel(MI, OpNo, O);
979 }
980 
981 void AMDGPUInstPrinter::printSDWASrc1Sel(const MCInst *MI, unsigned OpNo,
982                                          const MCSubtargetInfo &STI,
983                                          raw_ostream &O) {
984   O << "src1_sel:";
985   printSDWASel(MI, OpNo, O);
986 }
987 
988 void AMDGPUInstPrinter::printSDWADstUnused(const MCInst *MI, unsigned OpNo,
989                                            const MCSubtargetInfo &STI,
990                                            raw_ostream &O) {
991   using namespace llvm::AMDGPU::SDWA;
992 
993   O << "dst_unused:";
994   unsigned Imm = MI->getOperand(OpNo).getImm();
995   switch (Imm) {
996   case DstUnused::UNUSED_PAD: O << "UNUSED_PAD"; break;
997   case DstUnused::UNUSED_SEXT: O << "UNUSED_SEXT"; break;
998   case DstUnused::UNUSED_PRESERVE: O << "UNUSED_PRESERVE"; break;
999   default: llvm_unreachable("Invalid SDWA dest_unused operand");
1000   }
1001 }
1002 
1003 void AMDGPUInstPrinter::printExpSrcN(const MCInst *MI, unsigned OpNo,
1004                                      const MCSubtargetInfo &STI, raw_ostream &O,
1005                                      unsigned N) {
1006   unsigned Opc = MI->getOpcode();
1007   int EnIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::en);
1008   unsigned En = MI->getOperand(EnIdx).getImm();
1009 
1010   int ComprIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::compr);
1011 
1012   // If compr is set, print as src0, src0, src1, src1
1013   if (MI->getOperand(ComprIdx).getImm())
1014     OpNo = OpNo - N + N / 2;
1015 
1016   if (En & (1 << N))
1017     printRegOperand(MI->getOperand(OpNo).getReg(), O, MRI);
1018   else
1019     O << "off";
1020 }
1021 
1022 void AMDGPUInstPrinter::printExpSrc0(const MCInst *MI, unsigned OpNo,
1023                                      const MCSubtargetInfo &STI,
1024                                      raw_ostream &O) {
1025   printExpSrcN(MI, OpNo, STI, O, 0);
1026 }
1027 
1028 void AMDGPUInstPrinter::printExpSrc1(const MCInst *MI, unsigned OpNo,
1029                                      const MCSubtargetInfo &STI,
1030                                      raw_ostream &O) {
1031   printExpSrcN(MI, OpNo, STI, O, 1);
1032 }
1033 
1034 void AMDGPUInstPrinter::printExpSrc2(const MCInst *MI, unsigned OpNo,
1035                                      const MCSubtargetInfo &STI,
1036                                      raw_ostream &O) {
1037   printExpSrcN(MI, OpNo, STI, O, 2);
1038 }
1039 
1040 void AMDGPUInstPrinter::printExpSrc3(const MCInst *MI, unsigned OpNo,
1041                                      const MCSubtargetInfo &STI,
1042                                      raw_ostream &O) {
1043   printExpSrcN(MI, OpNo, STI, O, 3);
1044 }
1045 
1046 void AMDGPUInstPrinter::printExpTgt(const MCInst *MI, unsigned OpNo,
1047                                     const MCSubtargetInfo &STI,
1048                                     raw_ostream &O) {
1049   using namespace llvm::AMDGPU::Exp;
1050 
1051   // This is really a 6 bit field.
1052   unsigned Id = MI->getOperand(OpNo).getImm() & ((1 << 6) - 1);
1053 
1054   int Index;
1055   StringRef TgtName;
1056   if (getTgtName(Id, TgtName, Index) && isSupportedTgtId(Id, STI)) {
1057     O << ' ' << TgtName;
1058     if (Index >= 0)
1059       O << Index;
1060   } else {
1061     O << " invalid_target_" << Id;
1062   }
1063 }
1064 
1065 static bool allOpsDefaultValue(const int* Ops, int NumOps, int Mod,
1066                                bool IsPacked, bool HasDstSel) {
1067   int DefaultValue = IsPacked && (Mod == SISrcMods::OP_SEL_1);
1068 
1069   for (int I = 0; I < NumOps; ++I) {
1070     if (!!(Ops[I] & Mod) != DefaultValue)
1071       return false;
1072   }
1073 
1074   if (HasDstSel && (Ops[0] & SISrcMods::DST_OP_SEL) != 0)
1075     return false;
1076 
1077   return true;
1078 }
1079 
1080 void AMDGPUInstPrinter::printPackedModifier(const MCInst *MI,
1081                                             StringRef Name,
1082                                             unsigned Mod,
1083                                             raw_ostream &O) {
1084   unsigned Opc = MI->getOpcode();
1085   int NumOps = 0;
1086   int Ops[3];
1087 
1088   for (int OpName : { AMDGPU::OpName::src0_modifiers,
1089                       AMDGPU::OpName::src1_modifiers,
1090                       AMDGPU::OpName::src2_modifiers }) {
1091     int Idx = AMDGPU::getNamedOperandIdx(Opc, OpName);
1092     if (Idx == -1)
1093       break;
1094 
1095     Ops[NumOps++] = MI->getOperand(Idx).getImm();
1096   }
1097 
1098   const bool HasDstSel =
1099     NumOps > 0 &&
1100     Mod == SISrcMods::OP_SEL_0 &&
1101     MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::VOP3_OPSEL;
1102 
1103   const bool IsPacked =
1104     MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::IsPacked;
1105 
1106   if (allOpsDefaultValue(Ops, NumOps, Mod, IsPacked, HasDstSel))
1107     return;
1108 
1109   O << Name;
1110   for (int I = 0; I < NumOps; ++I) {
1111     if (I != 0)
1112       O << ',';
1113 
1114     O << !!(Ops[I] & Mod);
1115   }
1116 
1117   if (HasDstSel) {
1118     O << ',' << !!(Ops[0] & SISrcMods::DST_OP_SEL);
1119   }
1120 
1121   O << ']';
1122 }
1123 
1124 void AMDGPUInstPrinter::printOpSel(const MCInst *MI, unsigned,
1125                                    const MCSubtargetInfo &STI,
1126                                    raw_ostream &O) {
1127   unsigned Opc = MI->getOpcode();
1128   if (Opc == AMDGPU::V_PERMLANE16_B32_gfx10 ||
1129       Opc == AMDGPU::V_PERMLANEX16_B32_gfx10) {
1130     auto FIN = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers);
1131     auto BCN = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers);
1132     unsigned FI = !!(MI->getOperand(FIN).getImm() & SISrcMods::OP_SEL_0);
1133     unsigned BC = !!(MI->getOperand(BCN).getImm() & SISrcMods::OP_SEL_0);
1134     if (FI || BC)
1135       O << " op_sel:[" << FI << ',' << BC << ']';
1136     return;
1137   }
1138 
1139   printPackedModifier(MI, " op_sel:[", SISrcMods::OP_SEL_0, O);
1140 }
1141 
1142 void AMDGPUInstPrinter::printOpSelHi(const MCInst *MI, unsigned OpNo,
1143                                      const MCSubtargetInfo &STI,
1144                                      raw_ostream &O) {
1145   printPackedModifier(MI, " op_sel_hi:[", SISrcMods::OP_SEL_1, O);
1146 }
1147 
1148 void AMDGPUInstPrinter::printNegLo(const MCInst *MI, unsigned OpNo,
1149                                    const MCSubtargetInfo &STI,
1150                                    raw_ostream &O) {
1151   printPackedModifier(MI, " neg_lo:[", SISrcMods::NEG, O);
1152 }
1153 
1154 void AMDGPUInstPrinter::printNegHi(const MCInst *MI, unsigned OpNo,
1155                                    const MCSubtargetInfo &STI,
1156                                    raw_ostream &O) {
1157   printPackedModifier(MI, " neg_hi:[", SISrcMods::NEG_HI, O);
1158 }
1159 
1160 void AMDGPUInstPrinter::printInterpSlot(const MCInst *MI, unsigned OpNum,
1161                                         const MCSubtargetInfo &STI,
1162                                         raw_ostream &O) {
1163   unsigned Imm = MI->getOperand(OpNum).getImm();
1164   switch (Imm) {
1165   case 0:
1166     O << "p10";
1167     break;
1168   case 1:
1169     O << "p20";
1170     break;
1171   case 2:
1172     O << "p0";
1173     break;
1174   default:
1175     O << "invalid_param_" << Imm;
1176   }
1177 }
1178 
1179 void AMDGPUInstPrinter::printInterpAttr(const MCInst *MI, unsigned OpNum,
1180                                         const MCSubtargetInfo &STI,
1181                                         raw_ostream &O) {
1182   unsigned Attr = MI->getOperand(OpNum).getImm();
1183   O << "attr" << Attr;
1184 }
1185 
1186 void AMDGPUInstPrinter::printInterpAttrChan(const MCInst *MI, unsigned OpNum,
1187                                         const MCSubtargetInfo &STI,
1188                                         raw_ostream &O) {
1189   unsigned Chan = MI->getOperand(OpNum).getImm();
1190   O << '.' << "xyzw"[Chan & 0x3];
1191 }
1192 
1193 void AMDGPUInstPrinter::printVGPRIndexMode(const MCInst *MI, unsigned OpNo,
1194                                            const MCSubtargetInfo &STI,
1195                                            raw_ostream &O) {
1196   using namespace llvm::AMDGPU::VGPRIndexMode;
1197   unsigned Val = MI->getOperand(OpNo).getImm();
1198 
1199   if ((Val & ~ENABLE_MASK) != 0) {
1200     O << formatHex(static_cast<uint64_t>(Val));
1201   } else {
1202     O << "gpr_idx(";
1203     bool NeedComma = false;
1204     for (unsigned ModeId = ID_MIN; ModeId <= ID_MAX; ++ModeId) {
1205       if (Val & (1 << ModeId)) {
1206         if (NeedComma)
1207           O << ',';
1208         O << IdSymbolic[ModeId];
1209         NeedComma = true;
1210       }
1211     }
1212     O << ')';
1213   }
1214 }
1215 
1216 void AMDGPUInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo,
1217                                         const MCSubtargetInfo &STI,
1218                                         raw_ostream &O) {
1219   printOperand(MI, OpNo, STI, O);
1220   O  << ", ";
1221   printOperand(MI, OpNo + 1, STI, O);
1222 }
1223 
1224 void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
1225                                    raw_ostream &O, StringRef Asm,
1226                                    StringRef Default) {
1227   const MCOperand &Op = MI->getOperand(OpNo);
1228   assert(Op.isImm());
1229   if (Op.getImm() == 1) {
1230     O << Asm;
1231   } else {
1232     O << Default;
1233   }
1234 }
1235 
1236 void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
1237                                    raw_ostream &O, char Asm) {
1238   const MCOperand &Op = MI->getOperand(OpNo);
1239   assert(Op.isImm());
1240   if (Op.getImm() == 1)
1241     O << Asm;
1242 }
1243 
1244 void AMDGPUInstPrinter::printHigh(const MCInst *MI, unsigned OpNo,
1245                                   const MCSubtargetInfo &STI,
1246                                   raw_ostream &O) {
1247   printNamedBit(MI, OpNo, O, "high");
1248 }
1249 
1250 void AMDGPUInstPrinter::printClampSI(const MCInst *MI, unsigned OpNo,
1251                                      const MCSubtargetInfo &STI,
1252                                      raw_ostream &O) {
1253   printNamedBit(MI, OpNo, O, "clamp");
1254 }
1255 
1256 void AMDGPUInstPrinter::printOModSI(const MCInst *MI, unsigned OpNo,
1257                                     const MCSubtargetInfo &STI,
1258                                     raw_ostream &O) {
1259   int Imm = MI->getOperand(OpNo).getImm();
1260   if (Imm == SIOutMods::MUL2)
1261     O << " mul:2";
1262   else if (Imm == SIOutMods::MUL4)
1263     O << " mul:4";
1264   else if (Imm == SIOutMods::DIV2)
1265     O << " div:2";
1266 }
1267 
1268 void AMDGPUInstPrinter::printSendMsg(const MCInst *MI, unsigned OpNo,
1269                                      const MCSubtargetInfo &STI,
1270                                      raw_ostream &O) {
1271   using namespace llvm::AMDGPU::SendMsg;
1272 
1273   const unsigned Imm16 = MI->getOperand(OpNo).getImm();
1274 
1275   uint16_t MsgId;
1276   uint16_t OpId;
1277   uint16_t StreamId;
1278   decodeMsg(Imm16, MsgId, OpId, StreamId);
1279 
1280   StringRef MsgName = getMsgName(MsgId, STI);
1281 
1282   if (!MsgName.empty() && isValidMsgOp(MsgId, OpId, STI) &&
1283       isValidMsgStream(MsgId, OpId, StreamId, STI)) {
1284     O << "sendmsg(" << MsgName;
1285     if (msgRequiresOp(MsgId)) {
1286       O << ", " << getMsgOpName(MsgId, OpId);
1287       if (msgSupportsStream(MsgId, OpId)) {
1288         O << ", " << StreamId;
1289       }
1290     }
1291     O << ')';
1292   } else if (encodeMsg(MsgId, OpId, StreamId) == Imm16) {
1293     O << "sendmsg(" << MsgId << ", " << OpId << ", " << StreamId << ')';
1294   } else {
1295     O << Imm16; // Unknown imm16 code.
1296   }
1297 }
1298 
1299 static void printSwizzleBitmask(const uint16_t AndMask,
1300                                 const uint16_t OrMask,
1301                                 const uint16_t XorMask,
1302                                 raw_ostream &O) {
1303   using namespace llvm::AMDGPU::Swizzle;
1304 
1305   uint16_t Probe0 = ((0            & AndMask) | OrMask) ^ XorMask;
1306   uint16_t Probe1 = ((BITMASK_MASK & AndMask) | OrMask) ^ XorMask;
1307 
1308   O << "\"";
1309 
1310   for (unsigned Mask = 1 << (BITMASK_WIDTH - 1); Mask > 0; Mask >>= 1) {
1311     uint16_t p0 = Probe0 & Mask;
1312     uint16_t p1 = Probe1 & Mask;
1313 
1314     if (p0 == p1) {
1315       if (p0 == 0) {
1316         O << "0";
1317       } else {
1318         O << "1";
1319       }
1320     } else {
1321       if (p0 == 0) {
1322         O << "p";
1323       } else {
1324         O << "i";
1325       }
1326     }
1327   }
1328 
1329   O << "\"";
1330 }
1331 
1332 void AMDGPUInstPrinter::printSwizzle(const MCInst *MI, unsigned OpNo,
1333                                      const MCSubtargetInfo &STI,
1334                                      raw_ostream &O) {
1335   using namespace llvm::AMDGPU::Swizzle;
1336 
1337   uint16_t Imm = MI->getOperand(OpNo).getImm();
1338   if (Imm == 0) {
1339     return;
1340   }
1341 
1342   O << " offset:";
1343 
1344   if ((Imm & QUAD_PERM_ENC_MASK) == QUAD_PERM_ENC) {
1345 
1346     O << "swizzle(" << IdSymbolic[ID_QUAD_PERM];
1347     for (unsigned I = 0; I < LANE_NUM; ++I) {
1348       O << ",";
1349       O << formatDec(Imm & LANE_MASK);
1350       Imm >>= LANE_SHIFT;
1351     }
1352     O << ")";
1353 
1354   } else if ((Imm & BITMASK_PERM_ENC_MASK) == BITMASK_PERM_ENC) {
1355 
1356     uint16_t AndMask = (Imm >> BITMASK_AND_SHIFT) & BITMASK_MASK;
1357     uint16_t OrMask  = (Imm >> BITMASK_OR_SHIFT)  & BITMASK_MASK;
1358     uint16_t XorMask = (Imm >> BITMASK_XOR_SHIFT) & BITMASK_MASK;
1359 
1360     if (AndMask == BITMASK_MAX &&
1361         OrMask == 0 &&
1362         countPopulation(XorMask) == 1) {
1363 
1364       O << "swizzle(" << IdSymbolic[ID_SWAP];
1365       O << ",";
1366       O << formatDec(XorMask);
1367       O << ")";
1368 
1369     } else if (AndMask == BITMASK_MAX &&
1370                OrMask == 0 && XorMask > 0 &&
1371                isPowerOf2_64(XorMask + 1)) {
1372 
1373       O << "swizzle(" << IdSymbolic[ID_REVERSE];
1374       O << ",";
1375       O << formatDec(XorMask + 1);
1376       O << ")";
1377 
1378     } else {
1379 
1380       uint16_t GroupSize = BITMASK_MAX - AndMask + 1;
1381       if (GroupSize > 1 &&
1382           isPowerOf2_64(GroupSize) &&
1383           OrMask < GroupSize &&
1384           XorMask == 0) {
1385 
1386         O << "swizzle(" << IdSymbolic[ID_BROADCAST];
1387         O << ",";
1388         O << formatDec(GroupSize);
1389         O << ",";
1390         O << formatDec(OrMask);
1391         O << ")";
1392 
1393       } else {
1394         O << "swizzle(" << IdSymbolic[ID_BITMASK_PERM];
1395         O << ",";
1396         printSwizzleBitmask(AndMask, OrMask, XorMask, O);
1397         O << ")";
1398       }
1399     }
1400   } else {
1401     printU16ImmDecOperand(MI, OpNo, O);
1402   }
1403 }
1404 
1405 void AMDGPUInstPrinter::printWaitFlag(const MCInst *MI, unsigned OpNo,
1406                                       const MCSubtargetInfo &STI,
1407                                       raw_ostream &O) {
1408   AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(STI.getCPU());
1409 
1410   unsigned SImm16 = MI->getOperand(OpNo).getImm();
1411   unsigned Vmcnt, Expcnt, Lgkmcnt;
1412   decodeWaitcnt(ISA, SImm16, Vmcnt, Expcnt, Lgkmcnt);
1413 
1414   bool IsDefaultVmcnt = Vmcnt == getVmcntBitMask(ISA);
1415   bool IsDefaultExpcnt = Expcnt == getExpcntBitMask(ISA);
1416   bool IsDefaultLgkmcnt = Lgkmcnt == getLgkmcntBitMask(ISA);
1417   bool PrintAll = IsDefaultVmcnt && IsDefaultExpcnt && IsDefaultLgkmcnt;
1418 
1419   bool NeedSpace = false;
1420 
1421   if (!IsDefaultVmcnt || PrintAll) {
1422     O << "vmcnt(" << Vmcnt << ')';
1423     NeedSpace = true;
1424   }
1425 
1426   if (!IsDefaultExpcnt || PrintAll) {
1427     if (NeedSpace)
1428       O << ' ';
1429     O << "expcnt(" << Expcnt << ')';
1430     NeedSpace = true;
1431   }
1432 
1433   if (!IsDefaultLgkmcnt || PrintAll) {
1434     if (NeedSpace)
1435       O << ' ';
1436     O << "lgkmcnt(" << Lgkmcnt << ')';
1437   }
1438 }
1439 
1440 void AMDGPUInstPrinter::printDepCtr(const MCInst *MI, unsigned OpNo,
1441                                     const MCSubtargetInfo &STI,
1442                                     raw_ostream &O) {
1443   using namespace llvm::AMDGPU::DepCtr;
1444 
1445   uint64_t Imm16 = MI->getOperand(OpNo).getImm() & 0xffff;
1446 
1447   bool HasNonDefaultVal = false;
1448   if (isSymbolicDepCtrEncoding(Imm16, HasNonDefaultVal, STI)) {
1449     int Id = 0;
1450     StringRef Name;
1451     unsigned Val;
1452     bool IsDefault;
1453     bool NeedSpace = false;
1454     while (decodeDepCtr(Imm16, Id, Name, Val, IsDefault, STI)) {
1455       if (!IsDefault || !HasNonDefaultVal) {
1456         if (NeedSpace)
1457           O << ' ';
1458         O << Name << '(' << Val << ')';
1459         NeedSpace = true;
1460       }
1461     }
1462   } else {
1463     O << formatHex(Imm16);
1464   }
1465 }
1466 
1467 void AMDGPUInstPrinter::printHwreg(const MCInst *MI, unsigned OpNo,
1468                                    const MCSubtargetInfo &STI, raw_ostream &O) {
1469   unsigned Id;
1470   unsigned Offset;
1471   unsigned Width;
1472 
1473   using namespace llvm::AMDGPU::Hwreg;
1474   unsigned Val = MI->getOperand(OpNo).getImm();
1475   decodeHwreg(Val, Id, Offset, Width);
1476   StringRef HwRegName = getHwreg(Id, STI);
1477 
1478   O << "hwreg(";
1479   if (!HwRegName.empty()) {
1480     O << HwRegName;
1481   } else {
1482     O << Id;
1483   }
1484   if (Width != WIDTH_DEFAULT_ || Offset != OFFSET_DEFAULT_) {
1485     O << ", " << Offset << ", " << Width;
1486   }
1487   O << ')';
1488 }
1489 
1490 void AMDGPUInstPrinter::printEndpgm(const MCInst *MI, unsigned OpNo,
1491                                     const MCSubtargetInfo &STI,
1492                                     raw_ostream &O) {
1493   uint16_t Imm = MI->getOperand(OpNo).getImm();
1494   if (Imm == 0) {
1495     return;
1496   }
1497 
1498   O << ' ' << formatDec(Imm);
1499 }
1500 
1501 #include "AMDGPUGenAsmWriter.inc"
1502