1 //===-- AMDGPUInstPrinter.cpp - AMDGPU MC Inst -> ASM ---------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 // \file
8 //===----------------------------------------------------------------------===//
9 
10 #include "AMDGPUInstPrinter.h"
11 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
12 #include "SIDefines.h"
13 #include "SIRegisterInfo.h"
14 #include "Utils/AMDGPUAsmUtils.h"
15 #include "Utils/AMDGPUBaseInfo.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCInstrDesc.h"
19 #include "llvm/MC/MCInstrInfo.h"
20 #include "llvm/MC/MCSubtargetInfo.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/TargetParser.h"
23 
24 using namespace llvm;
25 using namespace llvm::AMDGPU;
26 
27 static cl::opt<bool> Keep16BitSuffixes(
28   "amdgpu-keep-16-bit-reg-suffixes",
29   cl::desc("Keep .l and .h suffixes in asm for debugging purposes"),
30   cl::init(false),
31   cl::ReallyHidden);
32 
33 void AMDGPUInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
34   // FIXME: The current implementation of
35   // AsmParser::parseRegisterOrRegisterNumber in MC implies we either emit this
36   // as an integer or we provide a name which represents a physical register.
37   // For CFI instructions we really want to emit a name for the DWARF register
38   // instead, because there may be multiple DWARF registers corresponding to a
39   // single physical register. One case where this problem manifests is with
40   // wave32/wave64 where using the physical register name is ambiguous: if we
41   // write e.g. `.cfi_undefined v0` we lose information about the wavefront
42   // size which we need to encode the register in the final DWARF. Ideally we
43   // would extend MC to support parsing DWARF register names so we could do
44   // something like `.cfi_undefined dwarf_wave32_v0`. For now we just live with
45   // non-pretty DWARF register names in assembly text.
46   OS << RegNo;
47 }
48 
49 void AMDGPUInstPrinter::printInst(const MCInst *MI, uint64_t Address,
50                                   StringRef Annot, const MCSubtargetInfo &STI,
51                                   raw_ostream &OS) {
52   OS.flush();
53   printInstruction(MI, Address, STI, OS);
54   printAnnotation(OS, Annot);
55 }
56 
57 void AMDGPUInstPrinter::printU4ImmOperand(const MCInst *MI, unsigned OpNo,
58                                           const MCSubtargetInfo &STI,
59                                           raw_ostream &O) {
60   O << formatHex(MI->getOperand(OpNo).getImm() & 0xf);
61 }
62 
63 void AMDGPUInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo,
64                                           raw_ostream &O) {
65   O << formatHex(MI->getOperand(OpNo).getImm() & 0xff);
66 }
67 
68 void AMDGPUInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
69                                            const MCSubtargetInfo &STI,
70                                            raw_ostream &O) {
71   // It's possible to end up with a 32-bit literal used with a 16-bit operand
72   // with ignored high bits. Print as 32-bit anyway in that case.
73   int64_t Imm = MI->getOperand(OpNo).getImm();
74   if (isInt<16>(Imm) || isUInt<16>(Imm))
75     O << formatHex(static_cast<uint64_t>(Imm & 0xffff));
76   else
77     printU32ImmOperand(MI, OpNo, STI, O);
78 }
79 
80 void AMDGPUInstPrinter::printU4ImmDecOperand(const MCInst *MI, unsigned OpNo,
81                                              raw_ostream &O) {
82   O << formatDec(MI->getOperand(OpNo).getImm() & 0xf);
83 }
84 
85 void AMDGPUInstPrinter::printU8ImmDecOperand(const MCInst *MI, unsigned OpNo,
86                                              raw_ostream &O) {
87   O << formatDec(MI->getOperand(OpNo).getImm() & 0xff);
88 }
89 
90 void AMDGPUInstPrinter::printU16ImmDecOperand(const MCInst *MI, unsigned OpNo,
91                                               raw_ostream &O) {
92   O << formatDec(MI->getOperand(OpNo).getImm() & 0xffff);
93 }
94 
95 void AMDGPUInstPrinter::printU32ImmOperand(const MCInst *MI, unsigned OpNo,
96                                            const MCSubtargetInfo &STI,
97                                            raw_ostream &O) {
98   O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff);
99 }
100 
101 void AMDGPUInstPrinter::printNamedBit(const MCInst *MI, unsigned OpNo,
102                                       raw_ostream &O, StringRef BitName) {
103   if (MI->getOperand(OpNo).getImm()) {
104     O << ' ' << BitName;
105   }
106 }
107 
108 void AMDGPUInstPrinter::printOffen(const MCInst *MI, unsigned OpNo,
109                                    raw_ostream &O) {
110   printNamedBit(MI, OpNo, O, "offen");
111 }
112 
113 void AMDGPUInstPrinter::printIdxen(const MCInst *MI, unsigned OpNo,
114                                    raw_ostream &O) {
115   printNamedBit(MI, OpNo, O, "idxen");
116 }
117 
118 void AMDGPUInstPrinter::printAddr64(const MCInst *MI, unsigned OpNo,
119                                     raw_ostream &O) {
120   printNamedBit(MI, OpNo, O, "addr64");
121 }
122 
123 void AMDGPUInstPrinter::printOffset(const MCInst *MI, unsigned OpNo,
124                                     const MCSubtargetInfo &STI,
125                                     raw_ostream &O) {
126   uint16_t Imm = MI->getOperand(OpNo).getImm();
127   if (Imm != 0) {
128     O << " offset:";
129     printU16ImmDecOperand(MI, OpNo, O);
130   }
131 }
132 
133 void AMDGPUInstPrinter::printFlatOffset(const MCInst *MI, unsigned OpNo,
134                                         const MCSubtargetInfo &STI,
135                                         raw_ostream &O) {
136   uint16_t Imm = MI->getOperand(OpNo).getImm();
137   if (Imm != 0) {
138     O << " offset:";
139 
140     const MCInstrDesc &Desc = MII.get(MI->getOpcode());
141     bool IsFlatSeg = !(Desc.TSFlags &
142                        (SIInstrFlags::FlatGlobal | SIInstrFlags::FlatScratch));
143 
144     if (IsFlatSeg) { // Unsigned offset
145       printU16ImmDecOperand(MI, OpNo, O);
146     } else {         // Signed offset
147       if (AMDGPU::isGFX10(STI)) {
148         O << formatDec(SignExtend32<12>(MI->getOperand(OpNo).getImm()));
149       } else {
150         O << formatDec(SignExtend32<13>(MI->getOperand(OpNo).getImm()));
151       }
152     }
153   }
154 }
155 
156 void AMDGPUInstPrinter::printOffset0(const MCInst *MI, unsigned OpNo,
157                                      const MCSubtargetInfo &STI,
158                                      raw_ostream &O) {
159   if (MI->getOperand(OpNo).getImm()) {
160     O << " offset0:";
161     printU8ImmDecOperand(MI, OpNo, O);
162   }
163 }
164 
165 void AMDGPUInstPrinter::printOffset1(const MCInst *MI, unsigned OpNo,
166                                      const MCSubtargetInfo &STI,
167                                      raw_ostream &O) {
168   if (MI->getOperand(OpNo).getImm()) {
169     O << " offset1:";
170     printU8ImmDecOperand(MI, OpNo, O);
171   }
172 }
173 
174 void AMDGPUInstPrinter::printSMRDOffset8(const MCInst *MI, unsigned OpNo,
175                                         const MCSubtargetInfo &STI,
176                                         raw_ostream &O) {
177   printU32ImmOperand(MI, OpNo, STI, O);
178 }
179 
180 void AMDGPUInstPrinter::printSMEMOffset(const MCInst *MI, unsigned OpNo,
181                                         const MCSubtargetInfo &STI,
182                                         raw_ostream &O) {
183   O << formatHex(MI->getOperand(OpNo).getImm());
184 }
185 
186 void AMDGPUInstPrinter::printSMEMOffsetMod(const MCInst *MI, unsigned OpNo,
187                                            const MCSubtargetInfo &STI,
188                                            raw_ostream &O) {
189   O << " offset:";
190   printSMEMOffset(MI, OpNo, STI, O);
191 }
192 
193 void AMDGPUInstPrinter::printSMRDLiteralOffset(const MCInst *MI, unsigned OpNo,
194                                                const MCSubtargetInfo &STI,
195                                                raw_ostream &O) {
196   printU32ImmOperand(MI, OpNo, STI, O);
197 }
198 
199 void AMDGPUInstPrinter::printGDS(const MCInst *MI, unsigned OpNo,
200                                  const MCSubtargetInfo &STI, raw_ostream &O) {
201   printNamedBit(MI, OpNo, O, "gds");
202 }
203 
204 void AMDGPUInstPrinter::printCPol(const MCInst *MI, unsigned OpNo,
205                                   const MCSubtargetInfo &STI, raw_ostream &O) {
206   auto Imm = MI->getOperand(OpNo).getImm();
207   if (Imm & CPol::GLC)
208     O << ((AMDGPU::isGFX940(STI) &&
209            !(MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::SMRD)) ? " sc0"
210                                                                      : " glc");
211   if (Imm & CPol::SLC)
212     O << (AMDGPU::isGFX940(STI) ? " nt" : " slc");
213   if ((Imm & CPol::DLC) && AMDGPU::isGFX10Plus(STI))
214     O << " dlc";
215   if ((Imm & CPol::SCC) && AMDGPU::isGFX90A(STI))
216     O << (AMDGPU::isGFX940(STI) ? " sc1" : " scc");
217   if (Imm & ~CPol::ALL)
218     O << " /* unexpected cache policy bit */";
219 }
220 
221 void AMDGPUInstPrinter::printSWZ(const MCInst *MI, unsigned OpNo,
222                                  const MCSubtargetInfo &STI, raw_ostream &O) {
223 }
224 
225 void AMDGPUInstPrinter::printTFE(const MCInst *MI, unsigned OpNo,
226                                  const MCSubtargetInfo &STI, raw_ostream &O) {
227   printNamedBit(MI, OpNo, O, "tfe");
228 }
229 
230 void AMDGPUInstPrinter::printDMask(const MCInst *MI, unsigned OpNo,
231                                    const MCSubtargetInfo &STI, raw_ostream &O) {
232   if (MI->getOperand(OpNo).getImm()) {
233     O << " dmask:";
234     printU16ImmOperand(MI, OpNo, STI, O);
235   }
236 }
237 
238 void AMDGPUInstPrinter::printDim(const MCInst *MI, unsigned OpNo,
239                                  const MCSubtargetInfo &STI, raw_ostream &O) {
240   unsigned Dim = MI->getOperand(OpNo).getImm();
241   O << " dim:SQ_RSRC_IMG_";
242 
243   const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfoByEncoding(Dim);
244   if (DimInfo)
245     O << DimInfo->AsmSuffix;
246   else
247     O << Dim;
248 }
249 
250 void AMDGPUInstPrinter::printUNorm(const MCInst *MI, unsigned OpNo,
251                                    const MCSubtargetInfo &STI, raw_ostream &O) {
252   printNamedBit(MI, OpNo, O, "unorm");
253 }
254 
255 void AMDGPUInstPrinter::printDA(const MCInst *MI, unsigned OpNo,
256                                 const MCSubtargetInfo &STI, raw_ostream &O) {
257   printNamedBit(MI, OpNo, O, "da");
258 }
259 
260 void AMDGPUInstPrinter::printR128A16(const MCInst *MI, unsigned OpNo,
261                                   const MCSubtargetInfo &STI, raw_ostream &O) {
262   if (STI.hasFeature(AMDGPU::FeatureR128A16))
263     printNamedBit(MI, OpNo, O, "a16");
264   else
265     printNamedBit(MI, OpNo, O, "r128");
266 }
267 
268 void AMDGPUInstPrinter::printGFX10A16(const MCInst *MI, unsigned OpNo,
269                                   const MCSubtargetInfo &STI, raw_ostream &O) {
270   printNamedBit(MI, OpNo, O, "a16");
271 }
272 
273 void AMDGPUInstPrinter::printLWE(const MCInst *MI, unsigned OpNo,
274                                  const MCSubtargetInfo &STI, raw_ostream &O) {
275   printNamedBit(MI, OpNo, O, "lwe");
276 }
277 
278 void AMDGPUInstPrinter::printD16(const MCInst *MI, unsigned OpNo,
279                                  const MCSubtargetInfo &STI, raw_ostream &O) {
280   printNamedBit(MI, OpNo, O, "d16");
281 }
282 
283 void AMDGPUInstPrinter::printExpCompr(const MCInst *MI, unsigned OpNo,
284                                       const MCSubtargetInfo &STI,
285                                       raw_ostream &O) {
286   printNamedBit(MI, OpNo, O, "compr");
287 }
288 
289 void AMDGPUInstPrinter::printExpVM(const MCInst *MI, unsigned OpNo,
290                                    const MCSubtargetInfo &STI,
291                                    raw_ostream &O) {
292   printNamedBit(MI, OpNo, O, "vm");
293 }
294 
295 void AMDGPUInstPrinter::printFORMAT(const MCInst *MI, unsigned OpNo,
296                                     const MCSubtargetInfo &STI,
297                                     raw_ostream &O) {
298 }
299 
300 void AMDGPUInstPrinter::printSymbolicFormat(const MCInst *MI,
301                                             const MCSubtargetInfo &STI,
302                                             raw_ostream &O) {
303   using namespace llvm::AMDGPU::MTBUFFormat;
304 
305   int OpNo =
306     AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::format);
307   assert(OpNo != -1);
308 
309   unsigned Val = MI->getOperand(OpNo).getImm();
310   if (AMDGPU::isGFX10Plus(STI)) {
311     if (Val == UFMT_DEFAULT)
312       return;
313     if (isValidUnifiedFormat(Val, STI)) {
314       O << " format:[" << getUnifiedFormatName(Val, STI) << ']';
315     } else {
316       O << " format:" << Val;
317     }
318   } else {
319     if (Val == DFMT_NFMT_DEFAULT)
320       return;
321     if (isValidDfmtNfmt(Val, STI)) {
322       unsigned Dfmt;
323       unsigned Nfmt;
324       decodeDfmtNfmt(Val, Dfmt, Nfmt);
325       O << " format:[";
326       if (Dfmt != DFMT_DEFAULT) {
327         O << getDfmtName(Dfmt);
328         if (Nfmt != NFMT_DEFAULT) {
329           O << ',';
330         }
331       }
332       if (Nfmt != NFMT_DEFAULT) {
333         O << getNfmtName(Nfmt, STI);
334       }
335       O << ']';
336     } else {
337       O << " format:" << Val;
338     }
339   }
340 }
341 
342 void AMDGPUInstPrinter::printRegOperand(unsigned RegNo, raw_ostream &O,
343                                         const MCRegisterInfo &MRI) {
344 #if !defined(NDEBUG)
345   switch (RegNo) {
346   case AMDGPU::FP_REG:
347   case AMDGPU::SP_REG:
348   case AMDGPU::PRIVATE_RSRC_REG:
349     llvm_unreachable("pseudo-register should not ever be emitted");
350   case AMDGPU::SCC:
351     llvm_unreachable("pseudo scc should not ever be emitted");
352   default:
353     break;
354   }
355 #endif
356 
357   StringRef RegName(getRegisterName(RegNo));
358   if (!Keep16BitSuffixes)
359     if (!RegName.consume_back(".l"))
360       RegName.consume_back(".h");
361 
362   O << RegName;
363 }
364 
365 void AMDGPUInstPrinter::printVOPDst(const MCInst *MI, unsigned OpNo,
366                                     const MCSubtargetInfo &STI, raw_ostream &O) {
367   auto Opcode = MI->getOpcode();
368   auto Flags = MII.get(Opcode).TSFlags;
369   if (OpNo == 0) {
370     if (Flags & SIInstrFlags::VOP3 && Flags & SIInstrFlags::DPP)
371       O << "_e64_dpp";
372     else if (Flags & SIInstrFlags::VOP3) {
373       if (!getVOP3IsSingle(Opcode))
374         O << "_e64";
375     } else if (Flags & SIInstrFlags::DPP)
376       O << "_dpp";
377     else if (Flags & SIInstrFlags::SDWA)
378       O << "_sdwa";
379     else if (((Flags & SIInstrFlags::VOP1) && !getVOP1IsSingle(Opcode)) ||
380              ((Flags & SIInstrFlags::VOP2) && !getVOP2IsSingle(Opcode)))
381       O << "_e32";
382     O << " ";
383   }
384 
385   printRegularOperand(MI, OpNo, STI, O);
386 
387   // Print default vcc/vcc_lo operand.
388   switch (Opcode) {
389   default: break;
390 
391   case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10:
392   case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10:
393   case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10:
394   case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10:
395   case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10:
396   case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10:
397   case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10:
398   case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10:
399   case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10:
400   case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10:
401   case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10:
402   case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10:
403   case AMDGPU::V_ADD_CO_CI_U32_e32_gfx11:
404   case AMDGPU::V_SUB_CO_CI_U32_e32_gfx11:
405   case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx11:
406   case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx11:
407   case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx11:
408   case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx11:
409   case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx11:
410   case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx11:
411   case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx11:
412     printDefaultVccOperand(false, STI, O);
413     break;
414   }
415 }
416 
417 void AMDGPUInstPrinter::printVINTRPDst(const MCInst *MI, unsigned OpNo,
418                                        const MCSubtargetInfo &STI, raw_ostream &O) {
419   if (AMDGPU::isSI(STI) || AMDGPU::isCI(STI))
420     O << " ";
421   else
422     O << "_e32 ";
423 
424   printRegularOperand(MI, OpNo, STI, O);
425 }
426 
427 void AMDGPUInstPrinter::printImmediateInt16(uint32_t Imm,
428                                             const MCSubtargetInfo &STI,
429                                             raw_ostream &O) {
430   int16_t SImm = static_cast<int16_t>(Imm);
431   if (isInlinableIntLiteral(SImm)) {
432     O << SImm;
433   } else {
434     uint64_t Imm16 = static_cast<uint16_t>(Imm);
435     O << formatHex(Imm16);
436   }
437 }
438 
439 void AMDGPUInstPrinter::printImmediate16(uint32_t Imm,
440                                          const MCSubtargetInfo &STI,
441                                          raw_ostream &O) {
442   int16_t SImm = static_cast<int16_t>(Imm);
443   if (isInlinableIntLiteral(SImm)) {
444     O << SImm;
445     return;
446   }
447 
448   if (Imm == 0x3C00)
449     O<< "1.0";
450   else if (Imm == 0xBC00)
451     O<< "-1.0";
452   else if (Imm == 0x3800)
453     O<< "0.5";
454   else if (Imm == 0xB800)
455     O<< "-0.5";
456   else if (Imm == 0x4000)
457     O<< "2.0";
458   else if (Imm == 0xC000)
459     O<< "-2.0";
460   else if (Imm == 0x4400)
461     O<< "4.0";
462   else if (Imm == 0xC400)
463     O<< "-4.0";
464   else if (Imm == 0x3118 &&
465            STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]) {
466     O << "0.15915494";
467   } else {
468     uint64_t Imm16 = static_cast<uint16_t>(Imm);
469     O << formatHex(Imm16);
470   }
471 }
472 
473 void AMDGPUInstPrinter::printImmediateV216(uint32_t Imm,
474                                            const MCSubtargetInfo &STI,
475                                            raw_ostream &O) {
476   uint16_t Lo16 = static_cast<uint16_t>(Imm);
477   printImmediate16(Lo16, STI, O);
478 }
479 
480 void AMDGPUInstPrinter::printImmediate32(uint32_t Imm,
481                                          const MCSubtargetInfo &STI,
482                                          raw_ostream &O) {
483   int32_t SImm = static_cast<int32_t>(Imm);
484   if (SImm >= -16 && SImm <= 64) {
485     O << SImm;
486     return;
487   }
488 
489   if (Imm == FloatToBits(0.0f))
490     O << "0.0";
491   else if (Imm == FloatToBits(1.0f))
492     O << "1.0";
493   else if (Imm == FloatToBits(-1.0f))
494     O << "-1.0";
495   else if (Imm == FloatToBits(0.5f))
496     O << "0.5";
497   else if (Imm == FloatToBits(-0.5f))
498     O << "-0.5";
499   else if (Imm == FloatToBits(2.0f))
500     O << "2.0";
501   else if (Imm == FloatToBits(-2.0f))
502     O << "-2.0";
503   else if (Imm == FloatToBits(4.0f))
504     O << "4.0";
505   else if (Imm == FloatToBits(-4.0f))
506     O << "-4.0";
507   else if (Imm == 0x3e22f983 &&
508            STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
509     O << "0.15915494";
510   else
511     O << formatHex(static_cast<uint64_t>(Imm));
512 }
513 
514 void AMDGPUInstPrinter::printImmediate64(uint64_t Imm,
515                                          const MCSubtargetInfo &STI,
516                                          raw_ostream &O) {
517   int64_t SImm = static_cast<int64_t>(Imm);
518   if (SImm >= -16 && SImm <= 64) {
519     O << SImm;
520     return;
521   }
522 
523   if (Imm == DoubleToBits(0.0))
524     O << "0.0";
525   else if (Imm == DoubleToBits(1.0))
526     O << "1.0";
527   else if (Imm == DoubleToBits(-1.0))
528     O << "-1.0";
529   else if (Imm == DoubleToBits(0.5))
530     O << "0.5";
531   else if (Imm == DoubleToBits(-0.5))
532     O << "-0.5";
533   else if (Imm == DoubleToBits(2.0))
534     O << "2.0";
535   else if (Imm == DoubleToBits(-2.0))
536     O << "-2.0";
537   else if (Imm == DoubleToBits(4.0))
538     O << "4.0";
539   else if (Imm == DoubleToBits(-4.0))
540     O << "-4.0";
541   else if (Imm == 0x3fc45f306dc9c882 &&
542            STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
543     O << "0.15915494309189532";
544   else {
545     assert(isUInt<32>(Imm) || isInt<32>(Imm));
546 
547     // In rare situations, we will have a 32-bit literal in a 64-bit
548     // operand. This is technically allowed for the encoding of s_mov_b64.
549     O << formatHex(static_cast<uint64_t>(Imm));
550   }
551 }
552 
553 void AMDGPUInstPrinter::printBLGP(const MCInst *MI, unsigned OpNo,
554                                   const MCSubtargetInfo &STI,
555                                   raw_ostream &O) {
556   unsigned Imm = MI->getOperand(OpNo).getImm();
557   if (!Imm)
558     return;
559 
560   if (AMDGPU::isGFX940(STI)) {
561     switch (MI->getOpcode()) {
562     case AMDGPU::V_MFMA_F64_16X16X4F64_gfx940_acd:
563     case AMDGPU::V_MFMA_F64_16X16X4F64_gfx940_vcd:
564     case AMDGPU::V_MFMA_F64_4X4X4F64_gfx940_acd:
565     case AMDGPU::V_MFMA_F64_4X4X4F64_gfx940_vcd:
566       O << " neg:[" << (Imm & 1) << ',' << ((Imm >> 1) & 1) << ','
567         << ((Imm >> 2) & 1) << ']';
568       return;
569     }
570   }
571 
572   O << " blgp:" << Imm;
573 }
574 
575 void AMDGPUInstPrinter::printCBSZ(const MCInst *MI, unsigned OpNo,
576                                   const MCSubtargetInfo &STI,
577                                   raw_ostream &O) {
578   unsigned Imm = MI->getOperand(OpNo).getImm();
579   if (!Imm)
580     return;
581 
582   O << " cbsz:" << Imm;
583 }
584 
585 void AMDGPUInstPrinter::printABID(const MCInst *MI, unsigned OpNo,
586                                   const MCSubtargetInfo &STI,
587                                   raw_ostream &O) {
588   unsigned Imm = MI->getOperand(OpNo).getImm();
589   if (!Imm)
590     return;
591 
592   O << " abid:" << Imm;
593 }
594 
595 void AMDGPUInstPrinter::printDefaultVccOperand(bool FirstOperand,
596                                                const MCSubtargetInfo &STI,
597                                                raw_ostream &O) {
598   if (!FirstOperand)
599     O << ", ";
600   printRegOperand(STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64]
601                       ? AMDGPU::VCC
602                       : AMDGPU::VCC_LO,
603                   O, MRI);
604   if (FirstOperand)
605     O << ", ";
606 }
607 
608 void AMDGPUInstPrinter::printWaitVDST(const MCInst *MI, unsigned OpNo,
609                                       const MCSubtargetInfo &STI,
610                                       raw_ostream &O) {
611   uint8_t Imm = MI->getOperand(OpNo).getImm();
612   if (Imm != 0) {
613     O << " wait_vdst:";
614     printU4ImmDecOperand(MI, OpNo, O);
615   }
616 }
617 
618 void AMDGPUInstPrinter::printWaitEXP(const MCInst *MI, unsigned OpNo,
619                                     const MCSubtargetInfo &STI,
620                                     raw_ostream &O) {
621   uint8_t Imm = MI->getOperand(OpNo).getImm();
622   if (Imm != 0) {
623     O << " wait_exp:";
624     printU4ImmDecOperand(MI, OpNo, O);
625   }
626 }
627 
628 bool AMDGPUInstPrinter::needsImpliedVcc(const MCInstrDesc &Desc,
629                                         unsigned OpNo) const {
630   return OpNo == 1 && (Desc.TSFlags & SIInstrFlags::DPP) &&
631          (Desc.TSFlags & SIInstrFlags::VOPC) &&
632          (Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC) ||
633           Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC_LO));
634 }
635 
636 // Print default vcc/vcc_lo operand of VOPC.
637 void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
638                                      const MCSubtargetInfo &STI,
639                                      raw_ostream &O) {
640   unsigned Opc = MI->getOpcode();
641   const MCInstrDesc &Desc = MII.get(Opc);
642   int ModIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers);
643   // 0, 1 and 2 are the first printed operands in different cases
644   // If there are printed modifiers, printOperandAndFPInputMods or
645   // printOperandAndIntInputMods will be called instead
646   if ((OpNo == 0 ||
647        (OpNo == 1 && (Desc.TSFlags & SIInstrFlags::DPP)) ||
648        (OpNo == 2 && (Desc.TSFlags & SIInstrFlags::DPP) && ModIdx != -1)) &&
649       (Desc.TSFlags & SIInstrFlags::VOPC) &&
650       (Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC) ||
651        Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC_LO)))
652     printDefaultVccOperand(true, STI, O);
653 
654   printRegularOperand(MI, OpNo, STI, O);
655 }
656 
657 // Print operands after vcc or modifier handling.
658 void AMDGPUInstPrinter::printRegularOperand(const MCInst *MI, unsigned OpNo,
659                                             const MCSubtargetInfo &STI,
660                                             raw_ostream &O) {
661   const MCInstrDesc &Desc = MII.get(MI->getOpcode());
662 
663   if (OpNo >= MI->getNumOperands()) {
664     O << "/*Missing OP" << OpNo << "*/";
665     return;
666   }
667 
668   const MCOperand &Op = MI->getOperand(OpNo);
669   if (Op.isReg()) {
670     printRegOperand(Op.getReg(), O, MRI);
671   } else if (Op.isImm()) {
672     const uint8_t OpTy = Desc.OpInfo[OpNo].OperandType;
673     switch (OpTy) {
674     case AMDGPU::OPERAND_REG_IMM_INT32:
675     case AMDGPU::OPERAND_REG_IMM_FP32:
676     case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED:
677     case AMDGPU::OPERAND_REG_INLINE_C_INT32:
678     case AMDGPU::OPERAND_REG_INLINE_C_FP32:
679     case AMDGPU::OPERAND_REG_INLINE_AC_INT32:
680     case AMDGPU::OPERAND_REG_INLINE_AC_FP32:
681     case AMDGPU::OPERAND_REG_IMM_V2INT32:
682     case AMDGPU::OPERAND_REG_IMM_V2FP32:
683     case AMDGPU::OPERAND_REG_INLINE_C_V2INT32:
684     case AMDGPU::OPERAND_REG_INLINE_C_V2FP32:
685     case MCOI::OPERAND_IMMEDIATE:
686       printImmediate32(Op.getImm(), STI, O);
687       break;
688     case AMDGPU::OPERAND_REG_IMM_INT64:
689     case AMDGPU::OPERAND_REG_IMM_FP64:
690     case AMDGPU::OPERAND_REG_INLINE_C_INT64:
691     case AMDGPU::OPERAND_REG_INLINE_C_FP64:
692     case AMDGPU::OPERAND_REG_INLINE_AC_FP64:
693       printImmediate64(Op.getImm(), STI, O);
694       break;
695     case AMDGPU::OPERAND_REG_INLINE_C_INT16:
696     case AMDGPU::OPERAND_REG_INLINE_AC_INT16:
697     case AMDGPU::OPERAND_REG_IMM_INT16:
698       printImmediateInt16(Op.getImm(), STI, O);
699       break;
700     case AMDGPU::OPERAND_REG_INLINE_C_FP16:
701     case AMDGPU::OPERAND_REG_INLINE_AC_FP16:
702     case AMDGPU::OPERAND_REG_IMM_FP16:
703     case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED:
704       printImmediate16(Op.getImm(), STI, O);
705       break;
706     case AMDGPU::OPERAND_REG_IMM_V2INT16:
707     case AMDGPU::OPERAND_REG_IMM_V2FP16:
708       if (!isUInt<16>(Op.getImm()) &&
709           STI.getFeatureBits()[AMDGPU::FeatureVOP3Literal]) {
710         printImmediate32(Op.getImm(), STI, O);
711         break;
712       }
713 
714       //  Deal with 16-bit FP inline immediates not working.
715       if (OpTy == AMDGPU::OPERAND_REG_IMM_V2FP16) {
716         printImmediate16(static_cast<uint16_t>(Op.getImm()), STI, O);
717         break;
718       }
719       LLVM_FALLTHROUGH;
720     case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
721     case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:
722       printImmediateInt16(static_cast<uint16_t>(Op.getImm()), STI, O);
723       break;
724     case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
725     case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16:
726       printImmediateV216(Op.getImm(), STI, O);
727       break;
728     case MCOI::OPERAND_UNKNOWN:
729     case MCOI::OPERAND_PCREL:
730       O << formatDec(Op.getImm());
731       break;
732     case MCOI::OPERAND_REGISTER:
733       // FIXME: This should be removed and handled somewhere else. Seems to come
734       // from a disassembler bug.
735       O << "/*invalid immediate*/";
736       break;
737     default:
738       // We hit this for the immediate instruction bits that don't yet have a
739       // custom printer.
740       llvm_unreachable("unexpected immediate operand type");
741     }
742   } else if (Op.isDFPImm()) {
743     double Value = bit_cast<double>(Op.getDFPImm());
744     // We special case 0.0 because otherwise it will be printed as an integer.
745     if (Value == 0.0)
746       O << "0.0";
747     else {
748       const MCInstrDesc &Desc = MII.get(MI->getOpcode());
749       int RCID = Desc.OpInfo[OpNo].RegClass;
750       unsigned RCBits = AMDGPU::getRegBitWidth(MRI.getRegClass(RCID));
751       if (RCBits == 32)
752         printImmediate32(FloatToBits(Value), STI, O);
753       else if (RCBits == 64)
754         printImmediate64(DoubleToBits(Value), STI, O);
755       else
756         llvm_unreachable("Invalid register class size");
757     }
758   } else if (Op.isExpr()) {
759     const MCExpr *Exp = Op.getExpr();
760     Exp->print(O, &MAI);
761   } else {
762     O << "/*INV_OP*/";
763   }
764 
765   // Print default vcc/vcc_lo operand of v_cndmask_b32_e32.
766   switch (MI->getOpcode()) {
767   default: break;
768 
769   case AMDGPU::V_CNDMASK_B32_e32_gfx10:
770   case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10:
771   case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10:
772   case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10:
773   case AMDGPU::V_CNDMASK_B32_dpp_gfx10:
774   case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10:
775   case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10:
776   case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10:
777   case AMDGPU::V_CNDMASK_B32_dpp8_gfx10:
778   case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10:
779   case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10:
780   case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10:
781   case AMDGPU::V_CNDMASK_B32_e32_gfx11:
782   case AMDGPU::V_ADD_CO_CI_U32_e32_gfx11:
783   case AMDGPU::V_SUB_CO_CI_U32_e32_gfx11:
784   case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx11:
785   case AMDGPU::V_CNDMASK_B32_dpp_gfx11:
786   case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx11:
787   case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx11:
788   case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx11:
789   case AMDGPU::V_CNDMASK_B32_dpp8_gfx11:
790   case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx11:
791   case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx11:
792   case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx11:
793 
794   case AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7:
795   case AMDGPU::V_CNDMASK_B32_e32_vi:
796     if ((int)OpNo == AMDGPU::getNamedOperandIdx(MI->getOpcode(),
797                                                 AMDGPU::OpName::src1))
798       printDefaultVccOperand(OpNo == 0, STI, O);
799     break;
800   }
801 
802   if (Desc.TSFlags & SIInstrFlags::MTBUF) {
803     int SOffsetIdx =
804       AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::soffset);
805     assert(SOffsetIdx != -1);
806     if ((int)OpNo == SOffsetIdx)
807       printSymbolicFormat(MI, STI, O);
808   }
809 }
810 
811 void AMDGPUInstPrinter::printOperandAndFPInputMods(const MCInst *MI,
812                                                    unsigned OpNo,
813                                                    const MCSubtargetInfo &STI,
814                                                    raw_ostream &O) {
815   const MCInstrDesc &Desc = MII.get(MI->getOpcode());
816   if (needsImpliedVcc(Desc, OpNo))
817     printDefaultVccOperand(true, STI, O);
818 
819   unsigned InputModifiers = MI->getOperand(OpNo).getImm();
820 
821   // Use 'neg(...)' instead of '-' to avoid ambiguity.
822   // This is important for integer literals because
823   // -1 is not the same value as neg(1).
824   bool NegMnemo = false;
825 
826   if (InputModifiers & SISrcMods::NEG) {
827     if (OpNo + 1 < MI->getNumOperands() &&
828         (InputModifiers & SISrcMods::ABS) == 0) {
829       const MCOperand &Op = MI->getOperand(OpNo + 1);
830       NegMnemo = Op.isImm() || Op.isDFPImm();
831     }
832     if (NegMnemo) {
833       O << "neg(";
834     } else {
835       O << '-';
836     }
837   }
838 
839   if (InputModifiers & SISrcMods::ABS)
840     O << '|';
841   printRegularOperand(MI, OpNo + 1, STI, O);
842   if (InputModifiers & SISrcMods::ABS)
843     O << '|';
844 
845   if (NegMnemo) {
846     O << ')';
847   }
848 }
849 
850 void AMDGPUInstPrinter::printOperandAndIntInputMods(const MCInst *MI,
851                                                     unsigned OpNo,
852                                                     const MCSubtargetInfo &STI,
853                                                     raw_ostream &O) {
854   const MCInstrDesc &Desc = MII.get(MI->getOpcode());
855   if (needsImpliedVcc(Desc, OpNo))
856     printDefaultVccOperand(true, STI, O);
857 
858   unsigned InputModifiers = MI->getOperand(OpNo).getImm();
859   if (InputModifiers & SISrcMods::SEXT)
860     O << "sext(";
861   printRegularOperand(MI, OpNo + 1, STI, O);
862   if (InputModifiers & SISrcMods::SEXT)
863     O << ')';
864 
865   // Print default vcc/vcc_lo operand of VOP2b.
866   switch (MI->getOpcode()) {
867   default: break;
868 
869   case AMDGPU::V_CNDMASK_B32_sdwa_gfx10:
870   case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10:
871   case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10:
872   case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10:
873     if ((int)OpNo + 1 == AMDGPU::getNamedOperandIdx(MI->getOpcode(),
874                                                     AMDGPU::OpName::src1))
875       printDefaultVccOperand(OpNo == 0, STI, O);
876     break;
877   }
878 }
879 
880 void AMDGPUInstPrinter::printDPP8(const MCInst *MI, unsigned OpNo,
881                                   const MCSubtargetInfo &STI,
882                                   raw_ostream &O) {
883   if (!AMDGPU::isGFX10Plus(STI))
884     llvm_unreachable("dpp8 is not supported on ASICs earlier than GFX10");
885 
886   unsigned Imm = MI->getOperand(OpNo).getImm();
887   O << "dpp8:[" << formatDec(Imm & 0x7);
888   for (size_t i = 1; i < 8; ++i) {
889     O << ',' << formatDec((Imm >> (3 * i)) & 0x7);
890   }
891   O << ']';
892 }
893 
894 void AMDGPUInstPrinter::printDPPCtrl(const MCInst *MI, unsigned OpNo,
895                                      const MCSubtargetInfo &STI,
896                                      raw_ostream &O) {
897   using namespace AMDGPU::DPP;
898 
899   unsigned Imm = MI->getOperand(OpNo).getImm();
900   const MCInstrDesc &Desc = MII.get(MI->getOpcode());
901   int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
902                                            AMDGPU::OpName::src0);
903 
904   if (Src0Idx >= 0 &&
905       Desc.OpInfo[Src0Idx].RegClass == AMDGPU::VReg_64RegClassID &&
906       !AMDGPU::isLegal64BitDPPControl(Imm)) {
907     O << " /* 64 bit dpp only supports row_newbcast */";
908     return;
909   } else if (Imm <= DppCtrl::QUAD_PERM_LAST) {
910     O << "quad_perm:[";
911     O << formatDec(Imm & 0x3)         << ',';
912     O << formatDec((Imm & 0xc)  >> 2) << ',';
913     O << formatDec((Imm & 0x30) >> 4) << ',';
914     O << formatDec((Imm & 0xc0) >> 6) << ']';
915   } else if ((Imm >= DppCtrl::ROW_SHL_FIRST) &&
916              (Imm <= DppCtrl::ROW_SHL_LAST)) {
917     O << "row_shl:";
918     printU4ImmDecOperand(MI, OpNo, O);
919   } else if ((Imm >= DppCtrl::ROW_SHR_FIRST) &&
920              (Imm <= DppCtrl::ROW_SHR_LAST)) {
921     O << "row_shr:";
922     printU4ImmDecOperand(MI, OpNo, O);
923   } else if ((Imm >= DppCtrl::ROW_ROR_FIRST) &&
924              (Imm <= DppCtrl::ROW_ROR_LAST)) {
925     O << "row_ror:";
926     printU4ImmDecOperand(MI, OpNo, O);
927   } else if (Imm == DppCtrl::WAVE_SHL1) {
928     if (AMDGPU::isGFX10Plus(STI)) {
929       O << "/* wave_shl is not supported starting from GFX10 */";
930       return;
931     }
932     O << "wave_shl:1";
933   } else if (Imm == DppCtrl::WAVE_ROL1) {
934     if (AMDGPU::isGFX10Plus(STI)) {
935       O << "/* wave_rol is not supported starting from GFX10 */";
936       return;
937     }
938     O << "wave_rol:1";
939   } else if (Imm == DppCtrl::WAVE_SHR1) {
940     if (AMDGPU::isGFX10Plus(STI)) {
941       O << "/* wave_shr is not supported starting from GFX10 */";
942       return;
943     }
944     O << "wave_shr:1";
945   } else if (Imm == DppCtrl::WAVE_ROR1) {
946     if (AMDGPU::isGFX10Plus(STI)) {
947       O << "/* wave_ror is not supported starting from GFX10 */";
948       return;
949     }
950     O << "wave_ror:1";
951   } else if (Imm == DppCtrl::ROW_MIRROR) {
952     O << "row_mirror";
953   } else if (Imm == DppCtrl::ROW_HALF_MIRROR) {
954     O << "row_half_mirror";
955   } else if (Imm == DppCtrl::BCAST15) {
956     if (AMDGPU::isGFX10Plus(STI)) {
957       O << "/* row_bcast is not supported starting from GFX10 */";
958       return;
959     }
960     O << "row_bcast:15";
961   } else if (Imm == DppCtrl::BCAST31) {
962     if (AMDGPU::isGFX10Plus(STI)) {
963       O << "/* row_bcast is not supported starting from GFX10 */";
964       return;
965     }
966     O << "row_bcast:31";
967   } else if ((Imm >= DppCtrl::ROW_SHARE_FIRST) &&
968              (Imm <= DppCtrl::ROW_SHARE_LAST)) {
969     if (AMDGPU::isGFX90A(STI)) {
970       O << "row_newbcast:";
971     } else if (AMDGPU::isGFX10Plus(STI)) {
972       O << "row_share:";
973     } else {
974       O << " /* row_newbcast/row_share is not supported on ASICs earlier "
975            "than GFX90A/GFX10 */";
976       return;
977     }
978     printU4ImmDecOperand(MI, OpNo, O);
979   } else if ((Imm >= DppCtrl::ROW_XMASK_FIRST) &&
980              (Imm <= DppCtrl::ROW_XMASK_LAST)) {
981     if (!AMDGPU::isGFX10Plus(STI)) {
982       O << "/* row_xmask is not supported on ASICs earlier than GFX10 */";
983       return;
984     }
985     O << "row_xmask:";
986     printU4ImmDecOperand(MI, OpNo, O);
987   } else {
988     O << "/* Invalid dpp_ctrl value */";
989   }
990 }
991 
992 void AMDGPUInstPrinter::printRowMask(const MCInst *MI, unsigned OpNo,
993                                      const MCSubtargetInfo &STI,
994                                      raw_ostream &O) {
995   O << " row_mask:";
996   printU4ImmOperand(MI, OpNo, STI, O);
997 }
998 
999 void AMDGPUInstPrinter::printBankMask(const MCInst *MI, unsigned OpNo,
1000                                       const MCSubtargetInfo &STI,
1001                                       raw_ostream &O) {
1002   O << " bank_mask:";
1003   printU4ImmOperand(MI, OpNo, STI, O);
1004 }
1005 
1006 void AMDGPUInstPrinter::printBoundCtrl(const MCInst *MI, unsigned OpNo,
1007                                        const MCSubtargetInfo &STI,
1008                                        raw_ostream &O) {
1009   unsigned Imm = MI->getOperand(OpNo).getImm();
1010   if (Imm) {
1011     O << " bound_ctrl:1";
1012   }
1013 }
1014 
1015 void AMDGPUInstPrinter::printFI(const MCInst *MI, unsigned OpNo,
1016                                 const MCSubtargetInfo &STI,
1017                                 raw_ostream &O) {
1018   using namespace llvm::AMDGPU::DPP;
1019   unsigned Imm = MI->getOperand(OpNo).getImm();
1020   if (Imm == DPP_FI_1 || Imm == DPP8_FI_1) {
1021     O << " fi:1";
1022   }
1023 }
1024 
1025 void AMDGPUInstPrinter::printSDWASel(const MCInst *MI, unsigned OpNo,
1026                                      raw_ostream &O) {
1027   using namespace llvm::AMDGPU::SDWA;
1028 
1029   unsigned Imm = MI->getOperand(OpNo).getImm();
1030   switch (Imm) {
1031   case SdwaSel::BYTE_0: O << "BYTE_0"; break;
1032   case SdwaSel::BYTE_1: O << "BYTE_1"; break;
1033   case SdwaSel::BYTE_2: O << "BYTE_2"; break;
1034   case SdwaSel::BYTE_3: O << "BYTE_3"; break;
1035   case SdwaSel::WORD_0: O << "WORD_0"; break;
1036   case SdwaSel::WORD_1: O << "WORD_1"; break;
1037   case SdwaSel::DWORD: O << "DWORD"; break;
1038   default: llvm_unreachable("Invalid SDWA data select operand");
1039   }
1040 }
1041 
1042 void AMDGPUInstPrinter::printSDWADstSel(const MCInst *MI, unsigned OpNo,
1043                                         const MCSubtargetInfo &STI,
1044                                         raw_ostream &O) {
1045   O << "dst_sel:";
1046   printSDWASel(MI, OpNo, O);
1047 }
1048 
1049 void AMDGPUInstPrinter::printSDWASrc0Sel(const MCInst *MI, unsigned OpNo,
1050                                          const MCSubtargetInfo &STI,
1051                                          raw_ostream &O) {
1052   O << "src0_sel:";
1053   printSDWASel(MI, OpNo, O);
1054 }
1055 
1056 void AMDGPUInstPrinter::printSDWASrc1Sel(const MCInst *MI, unsigned OpNo,
1057                                          const MCSubtargetInfo &STI,
1058                                          raw_ostream &O) {
1059   O << "src1_sel:";
1060   printSDWASel(MI, OpNo, O);
1061 }
1062 
1063 void AMDGPUInstPrinter::printSDWADstUnused(const MCInst *MI, unsigned OpNo,
1064                                            const MCSubtargetInfo &STI,
1065                                            raw_ostream &O) {
1066   using namespace llvm::AMDGPU::SDWA;
1067 
1068   O << "dst_unused:";
1069   unsigned Imm = MI->getOperand(OpNo).getImm();
1070   switch (Imm) {
1071   case DstUnused::UNUSED_PAD: O << "UNUSED_PAD"; break;
1072   case DstUnused::UNUSED_SEXT: O << "UNUSED_SEXT"; break;
1073   case DstUnused::UNUSED_PRESERVE: O << "UNUSED_PRESERVE"; break;
1074   default: llvm_unreachable("Invalid SDWA dest_unused operand");
1075   }
1076 }
1077 
1078 void AMDGPUInstPrinter::printExpSrcN(const MCInst *MI, unsigned OpNo,
1079                                      const MCSubtargetInfo &STI, raw_ostream &O,
1080                                      unsigned N) {
1081   unsigned Opc = MI->getOpcode();
1082   int EnIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::en);
1083   unsigned En = MI->getOperand(EnIdx).getImm();
1084 
1085   int ComprIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::compr);
1086 
1087   // If compr is set, print as src0, src0, src1, src1
1088   if (MI->getOperand(ComprIdx).getImm())
1089     OpNo = OpNo - N + N / 2;
1090 
1091   if (En & (1 << N))
1092     printRegOperand(MI->getOperand(OpNo).getReg(), O, MRI);
1093   else
1094     O << "off";
1095 }
1096 
1097 void AMDGPUInstPrinter::printExpSrc0(const MCInst *MI, unsigned OpNo,
1098                                      const MCSubtargetInfo &STI,
1099                                      raw_ostream &O) {
1100   printExpSrcN(MI, OpNo, STI, O, 0);
1101 }
1102 
1103 void AMDGPUInstPrinter::printExpSrc1(const MCInst *MI, unsigned OpNo,
1104                                      const MCSubtargetInfo &STI,
1105                                      raw_ostream &O) {
1106   printExpSrcN(MI, OpNo, STI, O, 1);
1107 }
1108 
1109 void AMDGPUInstPrinter::printExpSrc2(const MCInst *MI, unsigned OpNo,
1110                                      const MCSubtargetInfo &STI,
1111                                      raw_ostream &O) {
1112   printExpSrcN(MI, OpNo, STI, O, 2);
1113 }
1114 
1115 void AMDGPUInstPrinter::printExpSrc3(const MCInst *MI, unsigned OpNo,
1116                                      const MCSubtargetInfo &STI,
1117                                      raw_ostream &O) {
1118   printExpSrcN(MI, OpNo, STI, O, 3);
1119 }
1120 
1121 void AMDGPUInstPrinter::printExpTgt(const MCInst *MI, unsigned OpNo,
1122                                     const MCSubtargetInfo &STI,
1123                                     raw_ostream &O) {
1124   using namespace llvm::AMDGPU::Exp;
1125 
1126   // This is really a 6 bit field.
1127   unsigned Id = MI->getOperand(OpNo).getImm() & ((1 << 6) - 1);
1128 
1129   int Index;
1130   StringRef TgtName;
1131   if (getTgtName(Id, TgtName, Index) && isSupportedTgtId(Id, STI)) {
1132     O << ' ' << TgtName;
1133     if (Index >= 0)
1134       O << Index;
1135   } else {
1136     O << " invalid_target_" << Id;
1137   }
1138 }
1139 
1140 static bool allOpsDefaultValue(const int* Ops, int NumOps, int Mod,
1141                                bool IsPacked, bool HasDstSel) {
1142   int DefaultValue = IsPacked && (Mod == SISrcMods::OP_SEL_1);
1143 
1144   for (int I = 0; I < NumOps; ++I) {
1145     if (!!(Ops[I] & Mod) != DefaultValue)
1146       return false;
1147   }
1148 
1149   if (HasDstSel && (Ops[0] & SISrcMods::DST_OP_SEL) != 0)
1150     return false;
1151 
1152   return true;
1153 }
1154 
1155 void AMDGPUInstPrinter::printPackedModifier(const MCInst *MI,
1156                                             StringRef Name,
1157                                             unsigned Mod,
1158                                             raw_ostream &O) {
1159   unsigned Opc = MI->getOpcode();
1160   int NumOps = 0;
1161   int Ops[3];
1162 
1163   for (int OpName : { AMDGPU::OpName::src0_modifiers,
1164                       AMDGPU::OpName::src1_modifiers,
1165                       AMDGPU::OpName::src2_modifiers }) {
1166     int Idx = AMDGPU::getNamedOperandIdx(Opc, OpName);
1167     if (Idx == -1)
1168       break;
1169 
1170     Ops[NumOps++] = MI->getOperand(Idx).getImm();
1171   }
1172 
1173   const bool HasDstSel =
1174     NumOps > 0 &&
1175     Mod == SISrcMods::OP_SEL_0 &&
1176     MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::VOP3_OPSEL;
1177 
1178   const bool IsPacked =
1179     MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::IsPacked;
1180 
1181   if (allOpsDefaultValue(Ops, NumOps, Mod, IsPacked, HasDstSel))
1182     return;
1183 
1184   O << Name;
1185   for (int I = 0; I < NumOps; ++I) {
1186     if (I != 0)
1187       O << ',';
1188 
1189     O << !!(Ops[I] & Mod);
1190   }
1191 
1192   if (HasDstSel) {
1193     O << ',' << !!(Ops[0] & SISrcMods::DST_OP_SEL);
1194   }
1195 
1196   O << ']';
1197 }
1198 
1199 void AMDGPUInstPrinter::printOpSel(const MCInst *MI, unsigned,
1200                                    const MCSubtargetInfo &STI,
1201                                    raw_ostream &O) {
1202   unsigned Opc = MI->getOpcode();
1203   if (Opc == AMDGPU::V_PERMLANE16_B32_gfx10 ||
1204       Opc == AMDGPU::V_PERMLANEX16_B32_gfx10) {
1205     auto FIN = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers);
1206     auto BCN = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers);
1207     unsigned FI = !!(MI->getOperand(FIN).getImm() & SISrcMods::OP_SEL_0);
1208     unsigned BC = !!(MI->getOperand(BCN).getImm() & SISrcMods::OP_SEL_0);
1209     if (FI || BC)
1210       O << " op_sel:[" << FI << ',' << BC << ']';
1211     return;
1212   }
1213 
1214   printPackedModifier(MI, " op_sel:[", SISrcMods::OP_SEL_0, O);
1215 }
1216 
1217 void AMDGPUInstPrinter::printOpSelHi(const MCInst *MI, unsigned OpNo,
1218                                      const MCSubtargetInfo &STI,
1219                                      raw_ostream &O) {
1220   printPackedModifier(MI, " op_sel_hi:[", SISrcMods::OP_SEL_1, O);
1221 }
1222 
1223 void AMDGPUInstPrinter::printNegLo(const MCInst *MI, unsigned OpNo,
1224                                    const MCSubtargetInfo &STI,
1225                                    raw_ostream &O) {
1226   printPackedModifier(MI, " neg_lo:[", SISrcMods::NEG, O);
1227 }
1228 
1229 void AMDGPUInstPrinter::printNegHi(const MCInst *MI, unsigned OpNo,
1230                                    const MCSubtargetInfo &STI,
1231                                    raw_ostream &O) {
1232   printPackedModifier(MI, " neg_hi:[", SISrcMods::NEG_HI, O);
1233 }
1234 
1235 void AMDGPUInstPrinter::printInterpSlot(const MCInst *MI, unsigned OpNum,
1236                                         const MCSubtargetInfo &STI,
1237                                         raw_ostream &O) {
1238   unsigned Imm = MI->getOperand(OpNum).getImm();
1239   switch (Imm) {
1240   case 0:
1241     O << "p10";
1242     break;
1243   case 1:
1244     O << "p20";
1245     break;
1246   case 2:
1247     O << "p0";
1248     break;
1249   default:
1250     O << "invalid_param_" << Imm;
1251   }
1252 }
1253 
1254 void AMDGPUInstPrinter::printInterpAttr(const MCInst *MI, unsigned OpNum,
1255                                         const MCSubtargetInfo &STI,
1256                                         raw_ostream &O) {
1257   unsigned Attr = MI->getOperand(OpNum).getImm();
1258   O << "attr" << Attr;
1259 }
1260 
1261 void AMDGPUInstPrinter::printInterpAttrChan(const MCInst *MI, unsigned OpNum,
1262                                         const MCSubtargetInfo &STI,
1263                                         raw_ostream &O) {
1264   unsigned Chan = MI->getOperand(OpNum).getImm();
1265   O << '.' << "xyzw"[Chan & 0x3];
1266 }
1267 
1268 void AMDGPUInstPrinter::printVGPRIndexMode(const MCInst *MI, unsigned OpNo,
1269                                            const MCSubtargetInfo &STI,
1270                                            raw_ostream &O) {
1271   using namespace llvm::AMDGPU::VGPRIndexMode;
1272   unsigned Val = MI->getOperand(OpNo).getImm();
1273 
1274   if ((Val & ~ENABLE_MASK) != 0) {
1275     O << formatHex(static_cast<uint64_t>(Val));
1276   } else {
1277     O << "gpr_idx(";
1278     bool NeedComma = false;
1279     for (unsigned ModeId = ID_MIN; ModeId <= ID_MAX; ++ModeId) {
1280       if (Val & (1 << ModeId)) {
1281         if (NeedComma)
1282           O << ',';
1283         O << IdSymbolic[ModeId];
1284         NeedComma = true;
1285       }
1286     }
1287     O << ')';
1288   }
1289 }
1290 
1291 void AMDGPUInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo,
1292                                         const MCSubtargetInfo &STI,
1293                                         raw_ostream &O) {
1294   printRegularOperand(MI, OpNo, STI, O);
1295   O  << ", ";
1296   printRegularOperand(MI, OpNo + 1, STI, O);
1297 }
1298 
1299 void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
1300                                    raw_ostream &O, StringRef Asm,
1301                                    StringRef Default) {
1302   const MCOperand &Op = MI->getOperand(OpNo);
1303   assert(Op.isImm());
1304   if (Op.getImm() == 1) {
1305     O << Asm;
1306   } else {
1307     O << Default;
1308   }
1309 }
1310 
1311 void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
1312                                    raw_ostream &O, char Asm) {
1313   const MCOperand &Op = MI->getOperand(OpNo);
1314   assert(Op.isImm());
1315   if (Op.getImm() == 1)
1316     O << Asm;
1317 }
1318 
1319 void AMDGPUInstPrinter::printHigh(const MCInst *MI, unsigned OpNo,
1320                                   const MCSubtargetInfo &STI,
1321                                   raw_ostream &O) {
1322   printNamedBit(MI, OpNo, O, "high");
1323 }
1324 
1325 void AMDGPUInstPrinter::printClampSI(const MCInst *MI, unsigned OpNo,
1326                                      const MCSubtargetInfo &STI,
1327                                      raw_ostream &O) {
1328   printNamedBit(MI, OpNo, O, "clamp");
1329 }
1330 
1331 void AMDGPUInstPrinter::printOModSI(const MCInst *MI, unsigned OpNo,
1332                                     const MCSubtargetInfo &STI,
1333                                     raw_ostream &O) {
1334   int Imm = MI->getOperand(OpNo).getImm();
1335   if (Imm == SIOutMods::MUL2)
1336     O << " mul:2";
1337   else if (Imm == SIOutMods::MUL4)
1338     O << " mul:4";
1339   else if (Imm == SIOutMods::DIV2)
1340     O << " div:2";
1341 }
1342 
1343 void AMDGPUInstPrinter::printSendMsg(const MCInst *MI, unsigned OpNo,
1344                                      const MCSubtargetInfo &STI,
1345                                      raw_ostream &O) {
1346   using namespace llvm::AMDGPU::SendMsg;
1347 
1348   const unsigned Imm16 = MI->getOperand(OpNo).getImm();
1349 
1350   uint16_t MsgId;
1351   uint16_t OpId;
1352   uint16_t StreamId;
1353   decodeMsg(Imm16, MsgId, OpId, StreamId, STI);
1354 
1355   StringRef MsgName = getMsgName(MsgId, STI);
1356 
1357   if (!MsgName.empty() && isValidMsgOp(MsgId, OpId, STI) &&
1358       isValidMsgStream(MsgId, OpId, StreamId, STI)) {
1359     O << "sendmsg(" << MsgName;
1360     if (msgRequiresOp(MsgId, STI)) {
1361       O << ", " << getMsgOpName(MsgId, OpId, STI);
1362       if (msgSupportsStream(MsgId, OpId, STI)) {
1363         O << ", " << StreamId;
1364       }
1365     }
1366     O << ')';
1367   } else if (encodeMsg(MsgId, OpId, StreamId) == Imm16) {
1368     O << "sendmsg(" << MsgId << ", " << OpId << ", " << StreamId << ')';
1369   } else {
1370     O << Imm16; // Unknown imm16 code.
1371   }
1372 }
1373 
1374 static void printSwizzleBitmask(const uint16_t AndMask,
1375                                 const uint16_t OrMask,
1376                                 const uint16_t XorMask,
1377                                 raw_ostream &O) {
1378   using namespace llvm::AMDGPU::Swizzle;
1379 
1380   uint16_t Probe0 = ((0            & AndMask) | OrMask) ^ XorMask;
1381   uint16_t Probe1 = ((BITMASK_MASK & AndMask) | OrMask) ^ XorMask;
1382 
1383   O << "\"";
1384 
1385   for (unsigned Mask = 1 << (BITMASK_WIDTH - 1); Mask > 0; Mask >>= 1) {
1386     uint16_t p0 = Probe0 & Mask;
1387     uint16_t p1 = Probe1 & Mask;
1388 
1389     if (p0 == p1) {
1390       if (p0 == 0) {
1391         O << "0";
1392       } else {
1393         O << "1";
1394       }
1395     } else {
1396       if (p0 == 0) {
1397         O << "p";
1398       } else {
1399         O << "i";
1400       }
1401     }
1402   }
1403 
1404   O << "\"";
1405 }
1406 
1407 void AMDGPUInstPrinter::printSwizzle(const MCInst *MI, unsigned OpNo,
1408                                      const MCSubtargetInfo &STI,
1409                                      raw_ostream &O) {
1410   using namespace llvm::AMDGPU::Swizzle;
1411 
1412   uint16_t Imm = MI->getOperand(OpNo).getImm();
1413   if (Imm == 0) {
1414     return;
1415   }
1416 
1417   O << " offset:";
1418 
1419   if ((Imm & QUAD_PERM_ENC_MASK) == QUAD_PERM_ENC) {
1420 
1421     O << "swizzle(" << IdSymbolic[ID_QUAD_PERM];
1422     for (unsigned I = 0; I < LANE_NUM; ++I) {
1423       O << ",";
1424       O << formatDec(Imm & LANE_MASK);
1425       Imm >>= LANE_SHIFT;
1426     }
1427     O << ")";
1428 
1429   } else if ((Imm & BITMASK_PERM_ENC_MASK) == BITMASK_PERM_ENC) {
1430 
1431     uint16_t AndMask = (Imm >> BITMASK_AND_SHIFT) & BITMASK_MASK;
1432     uint16_t OrMask  = (Imm >> BITMASK_OR_SHIFT)  & BITMASK_MASK;
1433     uint16_t XorMask = (Imm >> BITMASK_XOR_SHIFT) & BITMASK_MASK;
1434 
1435     if (AndMask == BITMASK_MAX &&
1436         OrMask == 0 &&
1437         countPopulation(XorMask) == 1) {
1438 
1439       O << "swizzle(" << IdSymbolic[ID_SWAP];
1440       O << ",";
1441       O << formatDec(XorMask);
1442       O << ")";
1443 
1444     } else if (AndMask == BITMASK_MAX &&
1445                OrMask == 0 && XorMask > 0 &&
1446                isPowerOf2_64(XorMask + 1)) {
1447 
1448       O << "swizzle(" << IdSymbolic[ID_REVERSE];
1449       O << ",";
1450       O << formatDec(XorMask + 1);
1451       O << ")";
1452 
1453     } else {
1454 
1455       uint16_t GroupSize = BITMASK_MAX - AndMask + 1;
1456       if (GroupSize > 1 &&
1457           isPowerOf2_64(GroupSize) &&
1458           OrMask < GroupSize &&
1459           XorMask == 0) {
1460 
1461         O << "swizzle(" << IdSymbolic[ID_BROADCAST];
1462         O << ",";
1463         O << formatDec(GroupSize);
1464         O << ",";
1465         O << formatDec(OrMask);
1466         O << ")";
1467 
1468       } else {
1469         O << "swizzle(" << IdSymbolic[ID_BITMASK_PERM];
1470         O << ",";
1471         printSwizzleBitmask(AndMask, OrMask, XorMask, O);
1472         O << ")";
1473       }
1474     }
1475   } else {
1476     printU16ImmDecOperand(MI, OpNo, O);
1477   }
1478 }
1479 
1480 void AMDGPUInstPrinter::printWaitFlag(const MCInst *MI, unsigned OpNo,
1481                                       const MCSubtargetInfo &STI,
1482                                       raw_ostream &O) {
1483   AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(STI.getCPU());
1484 
1485   unsigned SImm16 = MI->getOperand(OpNo).getImm();
1486   unsigned Vmcnt, Expcnt, Lgkmcnt;
1487   decodeWaitcnt(ISA, SImm16, Vmcnt, Expcnt, Lgkmcnt);
1488 
1489   bool IsDefaultVmcnt = Vmcnt == getVmcntBitMask(ISA);
1490   bool IsDefaultExpcnt = Expcnt == getExpcntBitMask(ISA);
1491   bool IsDefaultLgkmcnt = Lgkmcnt == getLgkmcntBitMask(ISA);
1492   bool PrintAll = IsDefaultVmcnt && IsDefaultExpcnt && IsDefaultLgkmcnt;
1493 
1494   bool NeedSpace = false;
1495 
1496   if (!IsDefaultVmcnt || PrintAll) {
1497     O << "vmcnt(" << Vmcnt << ')';
1498     NeedSpace = true;
1499   }
1500 
1501   if (!IsDefaultExpcnt || PrintAll) {
1502     if (NeedSpace)
1503       O << ' ';
1504     O << "expcnt(" << Expcnt << ')';
1505     NeedSpace = true;
1506   }
1507 
1508   if (!IsDefaultLgkmcnt || PrintAll) {
1509     if (NeedSpace)
1510       O << ' ';
1511     O << "lgkmcnt(" << Lgkmcnt << ')';
1512   }
1513 }
1514 
1515 void AMDGPUInstPrinter::printDepCtr(const MCInst *MI, unsigned OpNo,
1516                                     const MCSubtargetInfo &STI,
1517                                     raw_ostream &O) {
1518   using namespace llvm::AMDGPU::DepCtr;
1519 
1520   uint64_t Imm16 = MI->getOperand(OpNo).getImm() & 0xffff;
1521 
1522   bool HasNonDefaultVal = false;
1523   if (isSymbolicDepCtrEncoding(Imm16, HasNonDefaultVal, STI)) {
1524     int Id = 0;
1525     StringRef Name;
1526     unsigned Val;
1527     bool IsDefault;
1528     bool NeedSpace = false;
1529     while (decodeDepCtr(Imm16, Id, Name, Val, IsDefault, STI)) {
1530       if (!IsDefault || !HasNonDefaultVal) {
1531         if (NeedSpace)
1532           O << ' ';
1533         O << Name << '(' << Val << ')';
1534         NeedSpace = true;
1535       }
1536     }
1537   } else {
1538     O << formatHex(Imm16);
1539   }
1540 }
1541 
1542 void AMDGPUInstPrinter::printDelayFlag(const MCInst *MI, unsigned OpNo,
1543                                        const MCSubtargetInfo &STI,
1544                                        raw_ostream &O) {
1545   const char *BadInstId = "/* invalid instid value */";
1546   static const std::array<const char *, 12> InstIds = {
1547       "NO_DEP",        "VALU_DEP_1",    "VALU_DEP_2",
1548       "VALU_DEP_3",    "VALU_DEP_4",    "TRANS32_DEP_1",
1549       "TRANS32_DEP_2", "TRANS32_DEP_3", "FMA_ACCUM_CYCLE_1",
1550       "SALU_CYCLE_1",  "SALU_CYCLE_2",  "SALU_CYCLE_3"};
1551 
1552   const char *BadInstSkip = "/* invalid instskip value */";
1553   static const std::array<const char *, 6> InstSkips = {
1554       "SAME", "NEXT", "SKIP_1", "SKIP_2", "SKIP_3", "SKIP_4"};
1555 
1556   unsigned SImm16 = MI->getOperand(OpNo).getImm();
1557   const char *Prefix = "";
1558 
1559   unsigned Value = SImm16 & 0xF;
1560   if (Value) {
1561     const char *Name = Value < InstIds.size() ? InstIds[Value] : BadInstId;
1562     O << Prefix << "instid0(" << Name << ')';
1563     Prefix = " | ";
1564   }
1565 
1566   Value = (SImm16 >> 4) & 7;
1567   if (Value) {
1568     const char *Name =
1569         Value < InstSkips.size() ? InstSkips[Value] : BadInstSkip;
1570     O << Prefix << "instskip(" << Name << ')';
1571     Prefix = " | ";
1572   }
1573 
1574   Value = (SImm16 >> 7) & 0xF;
1575   if (Value) {
1576     const char *Name = Value < InstIds.size() ? InstIds[Value] : BadInstId;
1577     O << Prefix << "instid1(" << Name << ')';
1578     Prefix = " | ";
1579   }
1580 
1581   if (!*Prefix)
1582     O << "0";
1583 }
1584 
1585 void AMDGPUInstPrinter::printHwreg(const MCInst *MI, unsigned OpNo,
1586                                    const MCSubtargetInfo &STI, raw_ostream &O) {
1587   unsigned Id;
1588   unsigned Offset;
1589   unsigned Width;
1590 
1591   using namespace llvm::AMDGPU::Hwreg;
1592   unsigned Val = MI->getOperand(OpNo).getImm();
1593   decodeHwreg(Val, Id, Offset, Width);
1594   StringRef HwRegName = getHwreg(Id, STI);
1595 
1596   O << "hwreg(";
1597   if (!HwRegName.empty()) {
1598     O << HwRegName;
1599   } else {
1600     O << Id;
1601   }
1602   if (Width != WIDTH_DEFAULT_ || Offset != OFFSET_DEFAULT_) {
1603     O << ", " << Offset << ", " << Width;
1604   }
1605   O << ')';
1606 }
1607 
1608 void AMDGPUInstPrinter::printEndpgm(const MCInst *MI, unsigned OpNo,
1609                                     const MCSubtargetInfo &STI,
1610                                     raw_ostream &O) {
1611   uint16_t Imm = MI->getOperand(OpNo).getImm();
1612   if (Imm == 0) {
1613     return;
1614   }
1615 
1616   O << ' ' << formatDec(Imm);
1617 }
1618 
1619 #include "AMDGPUGenAsmWriter.inc"
1620