1 //===-- AMDGPUInstPrinter.cpp - AMDGPU MC Inst -> ASM ---------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 // \file
8 //===----------------------------------------------------------------------===//
9 
10 #include "AMDGPUInstPrinter.h"
11 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
12 #include "SIDefines.h"
13 #include "SIRegisterInfo.h"
14 #include "Utils/AMDGPUAsmUtils.h"
15 #include "Utils/AMDGPUBaseInfo.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCInstrDesc.h"
19 #include "llvm/MC/MCInstrInfo.h"
20 #include "llvm/MC/MCSubtargetInfo.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/TargetParser.h"
23 
24 using namespace llvm;
25 using namespace llvm::AMDGPU;
26 
27 static cl::opt<bool> Keep16BitSuffixes(
28   "amdgpu-keep-16-bit-reg-suffixes",
29   cl::desc("Keep .l and .h suffixes in asm for debugging purposes"),
30   cl::init(false),
31   cl::ReallyHidden);
32 
33 void AMDGPUInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
34   // FIXME: The current implementation of
35   // AsmParser::parseRegisterOrRegisterNumber in MC implies we either emit this
36   // as an integer or we provide a name which represents a physical register.
37   // For CFI instructions we really want to emit a name for the DWARF register
38   // instead, because there may be multiple DWARF registers corresponding to a
39   // single physical register. One case where this problem manifests is with
40   // wave32/wave64 where using the physical register name is ambiguous: if we
41   // write e.g. `.cfi_undefined v0` we lose information about the wavefront
42   // size which we need to encode the register in the final DWARF. Ideally we
43   // would extend MC to support parsing DWARF register names so we could do
44   // something like `.cfi_undefined dwarf_wave32_v0`. For now we just live with
45   // non-pretty DWARF register names in assembly text.
46   OS << RegNo;
47 }
48 
49 void AMDGPUInstPrinter::printInst(const MCInst *MI, uint64_t Address,
50                                   StringRef Annot, const MCSubtargetInfo &STI,
51                                   raw_ostream &OS) {
52   OS.flush();
53   printInstruction(MI, Address, STI, OS);
54   printAnnotation(OS, Annot);
55 }
56 
57 void AMDGPUInstPrinter::printU4ImmOperand(const MCInst *MI, unsigned OpNo,
58                                           const MCSubtargetInfo &STI,
59                                           raw_ostream &O) {
60   O << formatHex(MI->getOperand(OpNo).getImm() & 0xf);
61 }
62 
63 void AMDGPUInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo,
64                                           raw_ostream &O) {
65   O << formatHex(MI->getOperand(OpNo).getImm() & 0xff);
66 }
67 
68 void AMDGPUInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
69                                            const MCSubtargetInfo &STI,
70                                            raw_ostream &O) {
71   // It's possible to end up with a 32-bit literal used with a 16-bit operand
72   // with ignored high bits. Print as 32-bit anyway in that case.
73   int64_t Imm = MI->getOperand(OpNo).getImm();
74   if (isInt<16>(Imm) || isUInt<16>(Imm))
75     O << formatHex(static_cast<uint64_t>(Imm & 0xffff));
76   else
77     printU32ImmOperand(MI, OpNo, STI, O);
78 }
79 
80 void AMDGPUInstPrinter::printU4ImmDecOperand(const MCInst *MI, unsigned OpNo,
81                                              raw_ostream &O) {
82   O << formatDec(MI->getOperand(OpNo).getImm() & 0xf);
83 }
84 
85 void AMDGPUInstPrinter::printU8ImmDecOperand(const MCInst *MI, unsigned OpNo,
86                                              raw_ostream &O) {
87   O << formatDec(MI->getOperand(OpNo).getImm() & 0xff);
88 }
89 
90 void AMDGPUInstPrinter::printU16ImmDecOperand(const MCInst *MI, unsigned OpNo,
91                                               raw_ostream &O) {
92   O << formatDec(MI->getOperand(OpNo).getImm() & 0xffff);
93 }
94 
95 void AMDGPUInstPrinter::printU32ImmOperand(const MCInst *MI, unsigned OpNo,
96                                            const MCSubtargetInfo &STI,
97                                            raw_ostream &O) {
98   O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff);
99 }
100 
101 void AMDGPUInstPrinter::printNamedBit(const MCInst *MI, unsigned OpNo,
102                                       raw_ostream &O, StringRef BitName) {
103   if (MI->getOperand(OpNo).getImm()) {
104     O << ' ' << BitName;
105   }
106 }
107 
108 void AMDGPUInstPrinter::printOffen(const MCInst *MI, unsigned OpNo,
109                                    raw_ostream &O) {
110   printNamedBit(MI, OpNo, O, "offen");
111 }
112 
113 void AMDGPUInstPrinter::printIdxen(const MCInst *MI, unsigned OpNo,
114                                    raw_ostream &O) {
115   printNamedBit(MI, OpNo, O, "idxen");
116 }
117 
118 void AMDGPUInstPrinter::printAddr64(const MCInst *MI, unsigned OpNo,
119                                     raw_ostream &O) {
120   printNamedBit(MI, OpNo, O, "addr64");
121 }
122 
123 void AMDGPUInstPrinter::printOffset(const MCInst *MI, unsigned OpNo,
124                                     const MCSubtargetInfo &STI,
125                                     raw_ostream &O) {
126   uint16_t Imm = MI->getOperand(OpNo).getImm();
127   if (Imm != 0) {
128     O << " offset:";
129     printU16ImmDecOperand(MI, OpNo, O);
130   }
131 }
132 
133 void AMDGPUInstPrinter::printFlatOffset(const MCInst *MI, unsigned OpNo,
134                                         const MCSubtargetInfo &STI,
135                                         raw_ostream &O) {
136   uint16_t Imm = MI->getOperand(OpNo).getImm();
137   if (Imm != 0) {
138     O << " offset:";
139 
140     const MCInstrDesc &Desc = MII.get(MI->getOpcode());
141     bool IsFlatSeg = !(Desc.TSFlags &
142                        (SIInstrFlags::FlatGlobal | SIInstrFlags::FlatScratch));
143 
144     if (IsFlatSeg) { // Unsigned offset
145       printU16ImmDecOperand(MI, OpNo, O);
146     } else {         // Signed offset
147       if (AMDGPU::isGFX10(STI)) {
148         O << formatDec(SignExtend32<12>(MI->getOperand(OpNo).getImm()));
149       } else {
150         O << formatDec(SignExtend32<13>(MI->getOperand(OpNo).getImm()));
151       }
152     }
153   }
154 }
155 
156 void AMDGPUInstPrinter::printOffset0(const MCInst *MI, unsigned OpNo,
157                                      const MCSubtargetInfo &STI,
158                                      raw_ostream &O) {
159   if (MI->getOperand(OpNo).getImm()) {
160     O << " offset0:";
161     printU8ImmDecOperand(MI, OpNo, O);
162   }
163 }
164 
165 void AMDGPUInstPrinter::printOffset1(const MCInst *MI, unsigned OpNo,
166                                      const MCSubtargetInfo &STI,
167                                      raw_ostream &O) {
168   if (MI->getOperand(OpNo).getImm()) {
169     O << " offset1:";
170     printU8ImmDecOperand(MI, OpNo, O);
171   }
172 }
173 
174 void AMDGPUInstPrinter::printSMRDOffset8(const MCInst *MI, unsigned OpNo,
175                                         const MCSubtargetInfo &STI,
176                                         raw_ostream &O) {
177   printU32ImmOperand(MI, OpNo, STI, O);
178 }
179 
180 void AMDGPUInstPrinter::printSMEMOffset(const MCInst *MI, unsigned OpNo,
181                                         const MCSubtargetInfo &STI,
182                                         raw_ostream &O) {
183   O << formatHex(MI->getOperand(OpNo).getImm());
184 }
185 
186 void AMDGPUInstPrinter::printSMEMOffsetMod(const MCInst *MI, unsigned OpNo,
187                                            const MCSubtargetInfo &STI,
188                                            raw_ostream &O) {
189   O << " offset:";
190   printSMEMOffset(MI, OpNo, STI, O);
191 }
192 
193 void AMDGPUInstPrinter::printSMRDLiteralOffset(const MCInst *MI, unsigned OpNo,
194                                                const MCSubtargetInfo &STI,
195                                                raw_ostream &O) {
196   printU32ImmOperand(MI, OpNo, STI, O);
197 }
198 
199 void AMDGPUInstPrinter::printGDS(const MCInst *MI, unsigned OpNo,
200                                  const MCSubtargetInfo &STI, raw_ostream &O) {
201   printNamedBit(MI, OpNo, O, "gds");
202 }
203 
204 void AMDGPUInstPrinter::printCPol(const MCInst *MI, unsigned OpNo,
205                                   const MCSubtargetInfo &STI, raw_ostream &O) {
206   auto Imm = MI->getOperand(OpNo).getImm();
207   if (Imm & CPol::GLC)
208     O << ((AMDGPU::isGFX940(STI) &&
209            !(MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::SMRD)) ? " sc0"
210                                                                      : " glc");
211   if (Imm & CPol::SLC)
212     O << (AMDGPU::isGFX940(STI) ? " nt" : " slc");
213   if ((Imm & CPol::DLC) && AMDGPU::isGFX10Plus(STI))
214     O << " dlc";
215   if ((Imm & CPol::SCC) && AMDGPU::isGFX90A(STI))
216     O << (AMDGPU::isGFX940(STI) ? " sc1" : " scc");
217   if (Imm & ~CPol::ALL)
218     O << " /* unexpected cache policy bit */";
219 }
220 
221 void AMDGPUInstPrinter::printSWZ(const MCInst *MI, unsigned OpNo,
222                                  const MCSubtargetInfo &STI, raw_ostream &O) {
223 }
224 
225 void AMDGPUInstPrinter::printTFE(const MCInst *MI, unsigned OpNo,
226                                  const MCSubtargetInfo &STI, raw_ostream &O) {
227   printNamedBit(MI, OpNo, O, "tfe");
228 }
229 
230 void AMDGPUInstPrinter::printDMask(const MCInst *MI, unsigned OpNo,
231                                    const MCSubtargetInfo &STI, raw_ostream &O) {
232   if (MI->getOperand(OpNo).getImm()) {
233     O << " dmask:";
234     printU16ImmOperand(MI, OpNo, STI, O);
235   }
236 }
237 
238 void AMDGPUInstPrinter::printDim(const MCInst *MI, unsigned OpNo,
239                                  const MCSubtargetInfo &STI, raw_ostream &O) {
240   unsigned Dim = MI->getOperand(OpNo).getImm();
241   O << " dim:SQ_RSRC_IMG_";
242 
243   const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfoByEncoding(Dim);
244   if (DimInfo)
245     O << DimInfo->AsmSuffix;
246   else
247     O << Dim;
248 }
249 
250 void AMDGPUInstPrinter::printUNorm(const MCInst *MI, unsigned OpNo,
251                                    const MCSubtargetInfo &STI, raw_ostream &O) {
252   printNamedBit(MI, OpNo, O, "unorm");
253 }
254 
255 void AMDGPUInstPrinter::printDA(const MCInst *MI, unsigned OpNo,
256                                 const MCSubtargetInfo &STI, raw_ostream &O) {
257   printNamedBit(MI, OpNo, O, "da");
258 }
259 
260 void AMDGPUInstPrinter::printR128A16(const MCInst *MI, unsigned OpNo,
261                                   const MCSubtargetInfo &STI, raw_ostream &O) {
262   if (STI.hasFeature(AMDGPU::FeatureR128A16))
263     printNamedBit(MI, OpNo, O, "a16");
264   else
265     printNamedBit(MI, OpNo, O, "r128");
266 }
267 
268 void AMDGPUInstPrinter::printGFX10A16(const MCInst *MI, unsigned OpNo,
269                                   const MCSubtargetInfo &STI, raw_ostream &O) {
270   printNamedBit(MI, OpNo, O, "a16");
271 }
272 
273 void AMDGPUInstPrinter::printLWE(const MCInst *MI, unsigned OpNo,
274                                  const MCSubtargetInfo &STI, raw_ostream &O) {
275   printNamedBit(MI, OpNo, O, "lwe");
276 }
277 
278 void AMDGPUInstPrinter::printD16(const MCInst *MI, unsigned OpNo,
279                                  const MCSubtargetInfo &STI, raw_ostream &O) {
280   printNamedBit(MI, OpNo, O, "d16");
281 }
282 
283 void AMDGPUInstPrinter::printExpCompr(const MCInst *MI, unsigned OpNo,
284                                       const MCSubtargetInfo &STI,
285                                       raw_ostream &O) {
286   printNamedBit(MI, OpNo, O, "compr");
287 }
288 
289 void AMDGPUInstPrinter::printExpVM(const MCInst *MI, unsigned OpNo,
290                                    const MCSubtargetInfo &STI,
291                                    raw_ostream &O) {
292   printNamedBit(MI, OpNo, O, "vm");
293 }
294 
295 void AMDGPUInstPrinter::printFORMAT(const MCInst *MI, unsigned OpNo,
296                                     const MCSubtargetInfo &STI,
297                                     raw_ostream &O) {
298 }
299 
300 void AMDGPUInstPrinter::printSymbolicFormat(const MCInst *MI,
301                                             const MCSubtargetInfo &STI,
302                                             raw_ostream &O) {
303   using namespace llvm::AMDGPU::MTBUFFormat;
304 
305   int OpNo =
306     AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::format);
307   assert(OpNo != -1);
308 
309   unsigned Val = MI->getOperand(OpNo).getImm();
310   if (AMDGPU::isGFX10Plus(STI)) {
311     if (Val == UFMT_DEFAULT)
312       return;
313     if (isValidUnifiedFormat(Val, STI)) {
314       O << " format:[" << getUnifiedFormatName(Val, STI) << ']';
315     } else {
316       O << " format:" << Val;
317     }
318   } else {
319     if (Val == DFMT_NFMT_DEFAULT)
320       return;
321     if (isValidDfmtNfmt(Val, STI)) {
322       unsigned Dfmt;
323       unsigned Nfmt;
324       decodeDfmtNfmt(Val, Dfmt, Nfmt);
325       O << " format:[";
326       if (Dfmt != DFMT_DEFAULT) {
327         O << getDfmtName(Dfmt);
328         if (Nfmt != NFMT_DEFAULT) {
329           O << ',';
330         }
331       }
332       if (Nfmt != NFMT_DEFAULT) {
333         O << getNfmtName(Nfmt, STI);
334       }
335       O << ']';
336     } else {
337       O << " format:" << Val;
338     }
339   }
340 }
341 
342 void AMDGPUInstPrinter::printRegOperand(unsigned RegNo, raw_ostream &O,
343                                         const MCRegisterInfo &MRI) {
344 #if !defined(NDEBUG)
345   switch (RegNo) {
346   case AMDGPU::FP_REG:
347   case AMDGPU::SP_REG:
348   case AMDGPU::PRIVATE_RSRC_REG:
349     llvm_unreachable("pseudo-register should not ever be emitted");
350   case AMDGPU::SCC:
351     llvm_unreachable("pseudo scc should not ever be emitted");
352   default:
353     break;
354   }
355 #endif
356 
357   StringRef RegName(getRegisterName(RegNo));
358   if (!Keep16BitSuffixes)
359     if (!RegName.consume_back(".l"))
360       RegName.consume_back(".h");
361 
362   O << RegName;
363 }
364 
365 void AMDGPUInstPrinter::printVOPDst(const MCInst *MI, unsigned OpNo,
366                                     const MCSubtargetInfo &STI,
367                                     raw_ostream &O) {
368   auto Opcode = MI->getOpcode();
369   auto Flags = MII.get(Opcode).TSFlags;
370 
371   if (OpNo == 0) {
372     if (Flags & SIInstrFlags::VOP3) {
373       if (!getVOP3IsSingle(Opcode))
374         O << "_e64";
375     } else if (Flags & SIInstrFlags::DPP) {
376       O << "_dpp";
377     } else if (Flags & SIInstrFlags::SDWA) {
378       O << "_sdwa";
379     } else if (((Flags & SIInstrFlags::VOP1) && !getVOP1IsSingle(Opcode)) ||
380                ((Flags & SIInstrFlags::VOP2) && !getVOP2IsSingle(Opcode))) {
381       O << "_e32";
382     }
383     O << " ";
384   }
385 
386   printOperand(MI, OpNo, STI, O);
387 
388   // Print default vcc/vcc_lo operand.
389   switch (Opcode) {
390   default: break;
391 
392   case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10:
393   case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10:
394   case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10:
395   case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10:
396   case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10:
397   case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10:
398   case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10:
399   case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10:
400   case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10:
401   case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10:
402   case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10:
403   case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10:
404     printDefaultVccOperand(1, STI, O);
405     break;
406   }
407 }
408 
409 void AMDGPUInstPrinter::printVINTRPDst(const MCInst *MI, unsigned OpNo,
410                                        const MCSubtargetInfo &STI, raw_ostream &O) {
411   if (AMDGPU::isSI(STI) || AMDGPU::isCI(STI))
412     O << " ";
413   else
414     O << "_e32 ";
415 
416   printOperand(MI, OpNo, STI, O);
417 }
418 
419 void AMDGPUInstPrinter::printImmediateInt16(uint32_t Imm,
420                                             const MCSubtargetInfo &STI,
421                                             raw_ostream &O) {
422   int16_t SImm = static_cast<int16_t>(Imm);
423   if (isInlinableIntLiteral(SImm)) {
424     O << SImm;
425   } else {
426     uint64_t Imm16 = static_cast<uint16_t>(Imm);
427     O << formatHex(Imm16);
428   }
429 }
430 
431 void AMDGPUInstPrinter::printImmediate16(uint32_t Imm,
432                                          const MCSubtargetInfo &STI,
433                                          raw_ostream &O) {
434   int16_t SImm = static_cast<int16_t>(Imm);
435   if (isInlinableIntLiteral(SImm)) {
436     O << SImm;
437     return;
438   }
439 
440   if (Imm == 0x3C00)
441     O<< "1.0";
442   else if (Imm == 0xBC00)
443     O<< "-1.0";
444   else if (Imm == 0x3800)
445     O<< "0.5";
446   else if (Imm == 0xB800)
447     O<< "-0.5";
448   else if (Imm == 0x4000)
449     O<< "2.0";
450   else if (Imm == 0xC000)
451     O<< "-2.0";
452   else if (Imm == 0x4400)
453     O<< "4.0";
454   else if (Imm == 0xC400)
455     O<< "-4.0";
456   else if (Imm == 0x3118 &&
457            STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]) {
458     O << "0.15915494";
459   } else {
460     uint64_t Imm16 = static_cast<uint16_t>(Imm);
461     O << formatHex(Imm16);
462   }
463 }
464 
465 void AMDGPUInstPrinter::printImmediateV216(uint32_t Imm,
466                                            const MCSubtargetInfo &STI,
467                                            raw_ostream &O) {
468   uint16_t Lo16 = static_cast<uint16_t>(Imm);
469   printImmediate16(Lo16, STI, O);
470 }
471 
472 void AMDGPUInstPrinter::printImmediate32(uint32_t Imm,
473                                          const MCSubtargetInfo &STI,
474                                          raw_ostream &O) {
475   int32_t SImm = static_cast<int32_t>(Imm);
476   if (SImm >= -16 && SImm <= 64) {
477     O << SImm;
478     return;
479   }
480 
481   if (Imm == FloatToBits(0.0f))
482     O << "0.0";
483   else if (Imm == FloatToBits(1.0f))
484     O << "1.0";
485   else if (Imm == FloatToBits(-1.0f))
486     O << "-1.0";
487   else if (Imm == FloatToBits(0.5f))
488     O << "0.5";
489   else if (Imm == FloatToBits(-0.5f))
490     O << "-0.5";
491   else if (Imm == FloatToBits(2.0f))
492     O << "2.0";
493   else if (Imm == FloatToBits(-2.0f))
494     O << "-2.0";
495   else if (Imm == FloatToBits(4.0f))
496     O << "4.0";
497   else if (Imm == FloatToBits(-4.0f))
498     O << "-4.0";
499   else if (Imm == 0x3e22f983 &&
500            STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
501     O << "0.15915494";
502   else
503     O << formatHex(static_cast<uint64_t>(Imm));
504 }
505 
506 void AMDGPUInstPrinter::printImmediate64(uint64_t Imm,
507                                          const MCSubtargetInfo &STI,
508                                          raw_ostream &O) {
509   int64_t SImm = static_cast<int64_t>(Imm);
510   if (SImm >= -16 && SImm <= 64) {
511     O << SImm;
512     return;
513   }
514 
515   if (Imm == DoubleToBits(0.0))
516     O << "0.0";
517   else if (Imm == DoubleToBits(1.0))
518     O << "1.0";
519   else if (Imm == DoubleToBits(-1.0))
520     O << "-1.0";
521   else if (Imm == DoubleToBits(0.5))
522     O << "0.5";
523   else if (Imm == DoubleToBits(-0.5))
524     O << "-0.5";
525   else if (Imm == DoubleToBits(2.0))
526     O << "2.0";
527   else if (Imm == DoubleToBits(-2.0))
528     O << "-2.0";
529   else if (Imm == DoubleToBits(4.0))
530     O << "4.0";
531   else if (Imm == DoubleToBits(-4.0))
532     O << "-4.0";
533   else if (Imm == 0x3fc45f306dc9c882 &&
534            STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
535     O << "0.15915494309189532";
536   else {
537     assert(isUInt<32>(Imm) || Imm == 0x3fc45f306dc9c882);
538 
539     // In rare situations, we will have a 32-bit literal in a 64-bit
540     // operand. This is technically allowed for the encoding of s_mov_b64.
541     O << formatHex(static_cast<uint64_t>(Imm));
542   }
543 }
544 
545 void AMDGPUInstPrinter::printBLGP(const MCInst *MI, unsigned OpNo,
546                                   const MCSubtargetInfo &STI,
547                                   raw_ostream &O) {
548   unsigned Imm = MI->getOperand(OpNo).getImm();
549   if (!Imm)
550     return;
551 
552   if (AMDGPU::isGFX940(STI)) {
553     switch (MI->getOpcode()) {
554     case AMDGPU::V_MFMA_F64_16X16X4F64_gfx940_acd:
555     case AMDGPU::V_MFMA_F64_16X16X4F64_gfx940_vcd:
556     case AMDGPU::V_MFMA_F64_4X4X4F64_gfx940_acd:
557     case AMDGPU::V_MFMA_F64_4X4X4F64_gfx940_vcd:
558       O << " neg:[" << (Imm & 1) << ',' << ((Imm >> 1) & 1) << ','
559         << ((Imm >> 2) & 1) << ']';
560       return;
561     }
562   }
563 
564   O << " blgp:" << Imm;
565 }
566 
567 void AMDGPUInstPrinter::printCBSZ(const MCInst *MI, unsigned OpNo,
568                                   const MCSubtargetInfo &STI,
569                                   raw_ostream &O) {
570   unsigned Imm = MI->getOperand(OpNo).getImm();
571   if (!Imm)
572     return;
573 
574   O << " cbsz:" << Imm;
575 }
576 
577 void AMDGPUInstPrinter::printABID(const MCInst *MI, unsigned OpNo,
578                                   const MCSubtargetInfo &STI,
579                                   raw_ostream &O) {
580   unsigned Imm = MI->getOperand(OpNo).getImm();
581   if (!Imm)
582     return;
583 
584   O << " abid:" << Imm;
585 }
586 
587 void AMDGPUInstPrinter::printDefaultVccOperand(unsigned OpNo,
588                                                const MCSubtargetInfo &STI,
589                                                raw_ostream &O) {
590   if (OpNo > 0)
591     O << ", ";
592   printRegOperand(STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ?
593                   AMDGPU::VCC : AMDGPU::VCC_LO, O, MRI);
594   if (OpNo == 0)
595     O << ", ";
596 }
597 
598 void AMDGPUInstPrinter::printWaitVDST(const MCInst *MI, unsigned OpNo,
599                                       const MCSubtargetInfo &STI,
600                                       raw_ostream &O) {
601   uint8_t Imm = MI->getOperand(OpNo).getImm();
602   if (Imm != 0) {
603     O << " wait_vdst:";
604     printU4ImmDecOperand(MI, OpNo, O);
605   }
606 }
607 
608 void AMDGPUInstPrinter::printWaitEXP(const MCInst *MI, unsigned OpNo,
609                                     const MCSubtargetInfo &STI,
610                                     raw_ostream &O) {
611   uint8_t Imm = MI->getOperand(OpNo).getImm();
612   if (Imm != 0) {
613     O << " wait_exp:";
614     printU4ImmDecOperand(MI, OpNo, O);
615   }
616 }
617 
618 // Print default vcc/vcc_lo operand of VOPC.
619 void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
620                                      const MCSubtargetInfo &STI,
621                                      raw_ostream &O) {
622   // Print default vcc/vcc_lo operand of VOPC.
623   const MCInstrDesc &Desc = MII.get(MI->getOpcode());
624   if (OpNo == 0 && (Desc.TSFlags & SIInstrFlags::VOPC) &&
625       (Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC) ||
626        Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC_LO)))
627     printDefaultVccOperand(OpNo, STI, O);
628 
629   if (OpNo >= MI->getNumOperands()) {
630     O << "/*Missing OP" << OpNo << "*/";
631     return;
632   }
633 
634   const MCOperand &Op = MI->getOperand(OpNo);
635   if (Op.isReg()) {
636     printRegOperand(Op.getReg(), O, MRI);
637   } else if (Op.isImm()) {
638     const uint8_t OpTy = Desc.OpInfo[OpNo].OperandType;
639     switch (OpTy) {
640     case AMDGPU::OPERAND_REG_IMM_INT32:
641     case AMDGPU::OPERAND_REG_IMM_FP32:
642     case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED:
643     case AMDGPU::OPERAND_REG_INLINE_C_INT32:
644     case AMDGPU::OPERAND_REG_INLINE_C_FP32:
645     case AMDGPU::OPERAND_REG_INLINE_AC_INT32:
646     case AMDGPU::OPERAND_REG_INLINE_AC_FP32:
647     case AMDGPU::OPERAND_REG_IMM_V2INT32:
648     case AMDGPU::OPERAND_REG_IMM_V2FP32:
649     case AMDGPU::OPERAND_REG_INLINE_C_V2INT32:
650     case AMDGPU::OPERAND_REG_INLINE_C_V2FP32:
651     case MCOI::OPERAND_IMMEDIATE:
652       printImmediate32(Op.getImm(), STI, O);
653       break;
654     case AMDGPU::OPERAND_REG_IMM_INT64:
655     case AMDGPU::OPERAND_REG_IMM_FP64:
656     case AMDGPU::OPERAND_REG_INLINE_C_INT64:
657     case AMDGPU::OPERAND_REG_INLINE_C_FP64:
658     case AMDGPU::OPERAND_REG_INLINE_AC_FP64:
659       printImmediate64(Op.getImm(), STI, O);
660       break;
661     case AMDGPU::OPERAND_REG_INLINE_C_INT16:
662     case AMDGPU::OPERAND_REG_INLINE_AC_INT16:
663     case AMDGPU::OPERAND_REG_IMM_INT16:
664       printImmediateInt16(Op.getImm(), STI, O);
665       break;
666     case AMDGPU::OPERAND_REG_INLINE_C_FP16:
667     case AMDGPU::OPERAND_REG_INLINE_AC_FP16:
668     case AMDGPU::OPERAND_REG_IMM_FP16:
669     case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED:
670       printImmediate16(Op.getImm(), STI, O);
671       break;
672     case AMDGPU::OPERAND_REG_IMM_V2INT16:
673     case AMDGPU::OPERAND_REG_IMM_V2FP16:
674       if (!isUInt<16>(Op.getImm()) &&
675           STI.getFeatureBits()[AMDGPU::FeatureVOP3Literal]) {
676         printImmediate32(Op.getImm(), STI, O);
677         break;
678       }
679 
680       //  Deal with 16-bit FP inline immediates not working.
681       if (OpTy == AMDGPU::OPERAND_REG_IMM_V2FP16) {
682         printImmediate16(static_cast<uint16_t>(Op.getImm()), STI, O);
683         break;
684       }
685       LLVM_FALLTHROUGH;
686     case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
687     case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:
688       printImmediateInt16(static_cast<uint16_t>(Op.getImm()), STI, O);
689       break;
690     case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
691     case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16:
692       printImmediateV216(Op.getImm(), STI, O);
693       break;
694     case MCOI::OPERAND_UNKNOWN:
695     case MCOI::OPERAND_PCREL:
696       O << formatDec(Op.getImm());
697       break;
698     case MCOI::OPERAND_REGISTER:
699       // FIXME: This should be removed and handled somewhere else. Seems to come
700       // from a disassembler bug.
701       O << "/*invalid immediate*/";
702       break;
703     default:
704       // We hit this for the immediate instruction bits that don't yet have a
705       // custom printer.
706       llvm_unreachable("unexpected immediate operand type");
707     }
708   } else if (Op.isDFPImm()) {
709     double Value = bit_cast<double>(Op.getDFPImm());
710     // We special case 0.0 because otherwise it will be printed as an integer.
711     if (Value == 0.0)
712       O << "0.0";
713     else {
714       const MCInstrDesc &Desc = MII.get(MI->getOpcode());
715       int RCID = Desc.OpInfo[OpNo].RegClass;
716       unsigned RCBits = AMDGPU::getRegBitWidth(MRI.getRegClass(RCID));
717       if (RCBits == 32)
718         printImmediate32(FloatToBits(Value), STI, O);
719       else if (RCBits == 64)
720         printImmediate64(DoubleToBits(Value), STI, O);
721       else
722         llvm_unreachable("Invalid register class size");
723     }
724   } else if (Op.isExpr()) {
725     const MCExpr *Exp = Op.getExpr();
726     Exp->print(O, &MAI);
727   } else {
728     O << "/*INV_OP*/";
729   }
730 
731   // Print default vcc/vcc_lo operand of v_cndmask_b32_e32.
732   switch (MI->getOpcode()) {
733   default: break;
734 
735   case AMDGPU::V_CNDMASK_B32_e32_gfx10:
736   case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10:
737   case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10:
738   case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10:
739   case AMDGPU::V_CNDMASK_B32_dpp_gfx10:
740   case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10:
741   case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10:
742   case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10:
743   case AMDGPU::V_CNDMASK_B32_dpp8_gfx10:
744   case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10:
745   case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10:
746   case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10:
747 
748   case AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7:
749   case AMDGPU::V_CNDMASK_B32_e32_vi:
750     if ((int)OpNo == AMDGPU::getNamedOperandIdx(MI->getOpcode(),
751                                                 AMDGPU::OpName::src1))
752       printDefaultVccOperand(OpNo, STI, O);
753     break;
754   }
755 
756   if (Desc.TSFlags & SIInstrFlags::MTBUF) {
757     int SOffsetIdx =
758       AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::soffset);
759     assert(SOffsetIdx != -1);
760     if ((int)OpNo == SOffsetIdx)
761       printSymbolicFormat(MI, STI, O);
762   }
763 }
764 
765 void AMDGPUInstPrinter::printOperandAndFPInputMods(const MCInst *MI,
766                                                    unsigned OpNo,
767                                                    const MCSubtargetInfo &STI,
768                                                    raw_ostream &O) {
769   unsigned InputModifiers = MI->getOperand(OpNo).getImm();
770 
771   // Use 'neg(...)' instead of '-' to avoid ambiguity.
772   // This is important for integer literals because
773   // -1 is not the same value as neg(1).
774   bool NegMnemo = false;
775 
776   if (InputModifiers & SISrcMods::NEG) {
777     if (OpNo + 1 < MI->getNumOperands() &&
778         (InputModifiers & SISrcMods::ABS) == 0) {
779       const MCOperand &Op = MI->getOperand(OpNo + 1);
780       NegMnemo = Op.isImm() || Op.isDFPImm();
781     }
782     if (NegMnemo) {
783       O << "neg(";
784     } else {
785       O << '-';
786     }
787   }
788 
789   if (InputModifiers & SISrcMods::ABS)
790     O << '|';
791   printOperand(MI, OpNo + 1, STI, O);
792   if (InputModifiers & SISrcMods::ABS)
793     O << '|';
794 
795   if (NegMnemo) {
796     O << ')';
797   }
798 }
799 
800 void AMDGPUInstPrinter::printOperandAndIntInputMods(const MCInst *MI,
801                                                     unsigned OpNo,
802                                                     const MCSubtargetInfo &STI,
803                                                     raw_ostream &O) {
804   unsigned InputModifiers = MI->getOperand(OpNo).getImm();
805   if (InputModifiers & SISrcMods::SEXT)
806     O << "sext(";
807   printOperand(MI, OpNo + 1, STI, O);
808   if (InputModifiers & SISrcMods::SEXT)
809     O << ')';
810 
811   // Print default vcc/vcc_lo operand of VOP2b.
812   switch (MI->getOpcode()) {
813   default: break;
814 
815   case AMDGPU::V_CNDMASK_B32_sdwa_gfx10:
816   case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10:
817   case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10:
818   case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10:
819     if ((int)OpNo + 1 == AMDGPU::getNamedOperandIdx(MI->getOpcode(),
820                                                     AMDGPU::OpName::src1))
821       printDefaultVccOperand(OpNo, STI, O);
822     break;
823   }
824 }
825 
826 void AMDGPUInstPrinter::printDPP8(const MCInst *MI, unsigned OpNo,
827                                   const MCSubtargetInfo &STI,
828                                   raw_ostream &O) {
829   if (!AMDGPU::isGFX10Plus(STI))
830     llvm_unreachable("dpp8 is not supported on ASICs earlier than GFX10");
831 
832   unsigned Imm = MI->getOperand(OpNo).getImm();
833   O << "dpp8:[" << formatDec(Imm & 0x7);
834   for (size_t i = 1; i < 8; ++i) {
835     O << ',' << formatDec((Imm >> (3 * i)) & 0x7);
836   }
837   O << ']';
838 }
839 
840 void AMDGPUInstPrinter::printDPPCtrl(const MCInst *MI, unsigned OpNo,
841                                      const MCSubtargetInfo &STI,
842                                      raw_ostream &O) {
843   using namespace AMDGPU::DPP;
844 
845   unsigned Imm = MI->getOperand(OpNo).getImm();
846   const MCInstrDesc &Desc = MII.get(MI->getOpcode());
847   int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
848                                            AMDGPU::OpName::src0);
849 
850   if (Src0Idx >= 0 &&
851       Desc.OpInfo[Src0Idx].RegClass == AMDGPU::VReg_64RegClassID &&
852       !AMDGPU::isLegal64BitDPPControl(Imm)) {
853     O << " /* 64 bit dpp only supports row_newbcast */";
854     return;
855   } else if (Imm <= DppCtrl::QUAD_PERM_LAST) {
856     O << "quad_perm:[";
857     O << formatDec(Imm & 0x3)         << ',';
858     O << formatDec((Imm & 0xc)  >> 2) << ',';
859     O << formatDec((Imm & 0x30) >> 4) << ',';
860     O << formatDec((Imm & 0xc0) >> 6) << ']';
861   } else if ((Imm >= DppCtrl::ROW_SHL_FIRST) &&
862              (Imm <= DppCtrl::ROW_SHL_LAST)) {
863     O << "row_shl:";
864     printU4ImmDecOperand(MI, OpNo, O);
865   } else if ((Imm >= DppCtrl::ROW_SHR_FIRST) &&
866              (Imm <= DppCtrl::ROW_SHR_LAST)) {
867     O << "row_shr:";
868     printU4ImmDecOperand(MI, OpNo, O);
869   } else if ((Imm >= DppCtrl::ROW_ROR_FIRST) &&
870              (Imm <= DppCtrl::ROW_ROR_LAST)) {
871     O << "row_ror:";
872     printU4ImmDecOperand(MI, OpNo, O);
873   } else if (Imm == DppCtrl::WAVE_SHL1) {
874     if (AMDGPU::isGFX10Plus(STI)) {
875       O << "/* wave_shl is not supported starting from GFX10 */";
876       return;
877     }
878     O << "wave_shl:1";
879   } else if (Imm == DppCtrl::WAVE_ROL1) {
880     if (AMDGPU::isGFX10Plus(STI)) {
881       O << "/* wave_rol is not supported starting from GFX10 */";
882       return;
883     }
884     O << "wave_rol:1";
885   } else if (Imm == DppCtrl::WAVE_SHR1) {
886     if (AMDGPU::isGFX10Plus(STI)) {
887       O << "/* wave_shr is not supported starting from GFX10 */";
888       return;
889     }
890     O << "wave_shr:1";
891   } else if (Imm == DppCtrl::WAVE_ROR1) {
892     if (AMDGPU::isGFX10Plus(STI)) {
893       O << "/* wave_ror is not supported starting from GFX10 */";
894       return;
895     }
896     O << "wave_ror:1";
897   } else if (Imm == DppCtrl::ROW_MIRROR) {
898     O << "row_mirror";
899   } else if (Imm == DppCtrl::ROW_HALF_MIRROR) {
900     O << "row_half_mirror";
901   } else if (Imm == DppCtrl::BCAST15) {
902     if (AMDGPU::isGFX10Plus(STI)) {
903       O << "/* row_bcast is not supported starting from GFX10 */";
904       return;
905     }
906     O << "row_bcast:15";
907   } else if (Imm == DppCtrl::BCAST31) {
908     if (AMDGPU::isGFX10Plus(STI)) {
909       O << "/* row_bcast is not supported starting from GFX10 */";
910       return;
911     }
912     O << "row_bcast:31";
913   } else if ((Imm >= DppCtrl::ROW_SHARE_FIRST) &&
914              (Imm <= DppCtrl::ROW_SHARE_LAST)) {
915     if (AMDGPU::isGFX90A(STI)) {
916       O << "row_newbcast:";
917     } else if (AMDGPU::isGFX10Plus(STI)) {
918       O << "row_share:";
919     } else {
920       O << " /* row_newbcast/row_share is not supported on ASICs earlier "
921            "than GFX90A/GFX10 */";
922       return;
923     }
924     printU4ImmDecOperand(MI, OpNo, O);
925   } else if ((Imm >= DppCtrl::ROW_XMASK_FIRST) &&
926              (Imm <= DppCtrl::ROW_XMASK_LAST)) {
927     if (!AMDGPU::isGFX10Plus(STI)) {
928       O << "/* row_xmask is not supported on ASICs earlier than GFX10 */";
929       return;
930     }
931     O << "row_xmask:";
932     printU4ImmDecOperand(MI, OpNo, O);
933   } else {
934     O << "/* Invalid dpp_ctrl value */";
935   }
936 }
937 
938 void AMDGPUInstPrinter::printRowMask(const MCInst *MI, unsigned OpNo,
939                                      const MCSubtargetInfo &STI,
940                                      raw_ostream &O) {
941   O << " row_mask:";
942   printU4ImmOperand(MI, OpNo, STI, O);
943 }
944 
945 void AMDGPUInstPrinter::printBankMask(const MCInst *MI, unsigned OpNo,
946                                       const MCSubtargetInfo &STI,
947                                       raw_ostream &O) {
948   O << " bank_mask:";
949   printU4ImmOperand(MI, OpNo, STI, O);
950 }
951 
952 void AMDGPUInstPrinter::printBoundCtrl(const MCInst *MI, unsigned OpNo,
953                                        const MCSubtargetInfo &STI,
954                                        raw_ostream &O) {
955   unsigned Imm = MI->getOperand(OpNo).getImm();
956   if (Imm) {
957     O << " bound_ctrl:1";
958   }
959 }
960 
961 void AMDGPUInstPrinter::printFI(const MCInst *MI, unsigned OpNo,
962                                 const MCSubtargetInfo &STI,
963                                 raw_ostream &O) {
964   using namespace llvm::AMDGPU::DPP;
965   unsigned Imm = MI->getOperand(OpNo).getImm();
966   if (Imm == DPP_FI_1 || Imm == DPP8_FI_1) {
967     O << " fi:1";
968   }
969 }
970 
971 void AMDGPUInstPrinter::printSDWASel(const MCInst *MI, unsigned OpNo,
972                                      raw_ostream &O) {
973   using namespace llvm::AMDGPU::SDWA;
974 
975   unsigned Imm = MI->getOperand(OpNo).getImm();
976   switch (Imm) {
977   case SdwaSel::BYTE_0: O << "BYTE_0"; break;
978   case SdwaSel::BYTE_1: O << "BYTE_1"; break;
979   case SdwaSel::BYTE_2: O << "BYTE_2"; break;
980   case SdwaSel::BYTE_3: O << "BYTE_3"; break;
981   case SdwaSel::WORD_0: O << "WORD_0"; break;
982   case SdwaSel::WORD_1: O << "WORD_1"; break;
983   case SdwaSel::DWORD: O << "DWORD"; break;
984   default: llvm_unreachable("Invalid SDWA data select operand");
985   }
986 }
987 
988 void AMDGPUInstPrinter::printSDWADstSel(const MCInst *MI, unsigned OpNo,
989                                         const MCSubtargetInfo &STI,
990                                         raw_ostream &O) {
991   O << "dst_sel:";
992   printSDWASel(MI, OpNo, O);
993 }
994 
995 void AMDGPUInstPrinter::printSDWASrc0Sel(const MCInst *MI, unsigned OpNo,
996                                          const MCSubtargetInfo &STI,
997                                          raw_ostream &O) {
998   O << "src0_sel:";
999   printSDWASel(MI, OpNo, O);
1000 }
1001 
1002 void AMDGPUInstPrinter::printSDWASrc1Sel(const MCInst *MI, unsigned OpNo,
1003                                          const MCSubtargetInfo &STI,
1004                                          raw_ostream &O) {
1005   O << "src1_sel:";
1006   printSDWASel(MI, OpNo, O);
1007 }
1008 
1009 void AMDGPUInstPrinter::printSDWADstUnused(const MCInst *MI, unsigned OpNo,
1010                                            const MCSubtargetInfo &STI,
1011                                            raw_ostream &O) {
1012   using namespace llvm::AMDGPU::SDWA;
1013 
1014   O << "dst_unused:";
1015   unsigned Imm = MI->getOperand(OpNo).getImm();
1016   switch (Imm) {
1017   case DstUnused::UNUSED_PAD: O << "UNUSED_PAD"; break;
1018   case DstUnused::UNUSED_SEXT: O << "UNUSED_SEXT"; break;
1019   case DstUnused::UNUSED_PRESERVE: O << "UNUSED_PRESERVE"; break;
1020   default: llvm_unreachable("Invalid SDWA dest_unused operand");
1021   }
1022 }
1023 
1024 void AMDGPUInstPrinter::printExpSrcN(const MCInst *MI, unsigned OpNo,
1025                                      const MCSubtargetInfo &STI, raw_ostream &O,
1026                                      unsigned N) {
1027   unsigned Opc = MI->getOpcode();
1028   int EnIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::en);
1029   unsigned En = MI->getOperand(EnIdx).getImm();
1030 
1031   int ComprIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::compr);
1032 
1033   // If compr is set, print as src0, src0, src1, src1
1034   if (MI->getOperand(ComprIdx).getImm())
1035     OpNo = OpNo - N + N / 2;
1036 
1037   if (En & (1 << N))
1038     printRegOperand(MI->getOperand(OpNo).getReg(), O, MRI);
1039   else
1040     O << "off";
1041 }
1042 
1043 void AMDGPUInstPrinter::printExpSrc0(const MCInst *MI, unsigned OpNo,
1044                                      const MCSubtargetInfo &STI,
1045                                      raw_ostream &O) {
1046   printExpSrcN(MI, OpNo, STI, O, 0);
1047 }
1048 
1049 void AMDGPUInstPrinter::printExpSrc1(const MCInst *MI, unsigned OpNo,
1050                                      const MCSubtargetInfo &STI,
1051                                      raw_ostream &O) {
1052   printExpSrcN(MI, OpNo, STI, O, 1);
1053 }
1054 
1055 void AMDGPUInstPrinter::printExpSrc2(const MCInst *MI, unsigned OpNo,
1056                                      const MCSubtargetInfo &STI,
1057                                      raw_ostream &O) {
1058   printExpSrcN(MI, OpNo, STI, O, 2);
1059 }
1060 
1061 void AMDGPUInstPrinter::printExpSrc3(const MCInst *MI, unsigned OpNo,
1062                                      const MCSubtargetInfo &STI,
1063                                      raw_ostream &O) {
1064   printExpSrcN(MI, OpNo, STI, O, 3);
1065 }
1066 
1067 void AMDGPUInstPrinter::printExpTgt(const MCInst *MI, unsigned OpNo,
1068                                     const MCSubtargetInfo &STI,
1069                                     raw_ostream &O) {
1070   using namespace llvm::AMDGPU::Exp;
1071 
1072   // This is really a 6 bit field.
1073   unsigned Id = MI->getOperand(OpNo).getImm() & ((1 << 6) - 1);
1074 
1075   int Index;
1076   StringRef TgtName;
1077   if (getTgtName(Id, TgtName, Index) && isSupportedTgtId(Id, STI)) {
1078     O << ' ' << TgtName;
1079     if (Index >= 0)
1080       O << Index;
1081   } else {
1082     O << " invalid_target_" << Id;
1083   }
1084 }
1085 
1086 static bool allOpsDefaultValue(const int* Ops, int NumOps, int Mod,
1087                                bool IsPacked, bool HasDstSel) {
1088   int DefaultValue = IsPacked && (Mod == SISrcMods::OP_SEL_1);
1089 
1090   for (int I = 0; I < NumOps; ++I) {
1091     if (!!(Ops[I] & Mod) != DefaultValue)
1092       return false;
1093   }
1094 
1095   if (HasDstSel && (Ops[0] & SISrcMods::DST_OP_SEL) != 0)
1096     return false;
1097 
1098   return true;
1099 }
1100 
1101 void AMDGPUInstPrinter::printPackedModifier(const MCInst *MI,
1102                                             StringRef Name,
1103                                             unsigned Mod,
1104                                             raw_ostream &O) {
1105   unsigned Opc = MI->getOpcode();
1106   int NumOps = 0;
1107   int Ops[3];
1108 
1109   for (int OpName : { AMDGPU::OpName::src0_modifiers,
1110                       AMDGPU::OpName::src1_modifiers,
1111                       AMDGPU::OpName::src2_modifiers }) {
1112     int Idx = AMDGPU::getNamedOperandIdx(Opc, OpName);
1113     if (Idx == -1)
1114       break;
1115 
1116     Ops[NumOps++] = MI->getOperand(Idx).getImm();
1117   }
1118 
1119   const bool HasDstSel =
1120     NumOps > 0 &&
1121     Mod == SISrcMods::OP_SEL_0 &&
1122     MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::VOP3_OPSEL;
1123 
1124   const bool IsPacked =
1125     MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::IsPacked;
1126 
1127   if (allOpsDefaultValue(Ops, NumOps, Mod, IsPacked, HasDstSel))
1128     return;
1129 
1130   O << Name;
1131   for (int I = 0; I < NumOps; ++I) {
1132     if (I != 0)
1133       O << ',';
1134 
1135     O << !!(Ops[I] & Mod);
1136   }
1137 
1138   if (HasDstSel) {
1139     O << ',' << !!(Ops[0] & SISrcMods::DST_OP_SEL);
1140   }
1141 
1142   O << ']';
1143 }
1144 
1145 void AMDGPUInstPrinter::printOpSel(const MCInst *MI, unsigned,
1146                                    const MCSubtargetInfo &STI,
1147                                    raw_ostream &O) {
1148   unsigned Opc = MI->getOpcode();
1149   if (Opc == AMDGPU::V_PERMLANE16_B32_gfx10 ||
1150       Opc == AMDGPU::V_PERMLANEX16_B32_gfx10) {
1151     auto FIN = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers);
1152     auto BCN = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers);
1153     unsigned FI = !!(MI->getOperand(FIN).getImm() & SISrcMods::OP_SEL_0);
1154     unsigned BC = !!(MI->getOperand(BCN).getImm() & SISrcMods::OP_SEL_0);
1155     if (FI || BC)
1156       O << " op_sel:[" << FI << ',' << BC << ']';
1157     return;
1158   }
1159 
1160   printPackedModifier(MI, " op_sel:[", SISrcMods::OP_SEL_0, O);
1161 }
1162 
1163 void AMDGPUInstPrinter::printOpSelHi(const MCInst *MI, unsigned OpNo,
1164                                      const MCSubtargetInfo &STI,
1165                                      raw_ostream &O) {
1166   printPackedModifier(MI, " op_sel_hi:[", SISrcMods::OP_SEL_1, O);
1167 }
1168 
1169 void AMDGPUInstPrinter::printNegLo(const MCInst *MI, unsigned OpNo,
1170                                    const MCSubtargetInfo &STI,
1171                                    raw_ostream &O) {
1172   printPackedModifier(MI, " neg_lo:[", SISrcMods::NEG, O);
1173 }
1174 
1175 void AMDGPUInstPrinter::printNegHi(const MCInst *MI, unsigned OpNo,
1176                                    const MCSubtargetInfo &STI,
1177                                    raw_ostream &O) {
1178   printPackedModifier(MI, " neg_hi:[", SISrcMods::NEG_HI, O);
1179 }
1180 
1181 void AMDGPUInstPrinter::printInterpSlot(const MCInst *MI, unsigned OpNum,
1182                                         const MCSubtargetInfo &STI,
1183                                         raw_ostream &O) {
1184   unsigned Imm = MI->getOperand(OpNum).getImm();
1185   switch (Imm) {
1186   case 0:
1187     O << "p10";
1188     break;
1189   case 1:
1190     O << "p20";
1191     break;
1192   case 2:
1193     O << "p0";
1194     break;
1195   default:
1196     O << "invalid_param_" << Imm;
1197   }
1198 }
1199 
1200 void AMDGPUInstPrinter::printInterpAttr(const MCInst *MI, unsigned OpNum,
1201                                         const MCSubtargetInfo &STI,
1202                                         raw_ostream &O) {
1203   unsigned Attr = MI->getOperand(OpNum).getImm();
1204   O << "attr" << Attr;
1205 }
1206 
1207 void AMDGPUInstPrinter::printInterpAttrChan(const MCInst *MI, unsigned OpNum,
1208                                         const MCSubtargetInfo &STI,
1209                                         raw_ostream &O) {
1210   unsigned Chan = MI->getOperand(OpNum).getImm();
1211   O << '.' << "xyzw"[Chan & 0x3];
1212 }
1213 
1214 void AMDGPUInstPrinter::printVGPRIndexMode(const MCInst *MI, unsigned OpNo,
1215                                            const MCSubtargetInfo &STI,
1216                                            raw_ostream &O) {
1217   using namespace llvm::AMDGPU::VGPRIndexMode;
1218   unsigned Val = MI->getOperand(OpNo).getImm();
1219 
1220   if ((Val & ~ENABLE_MASK) != 0) {
1221     O << formatHex(static_cast<uint64_t>(Val));
1222   } else {
1223     O << "gpr_idx(";
1224     bool NeedComma = false;
1225     for (unsigned ModeId = ID_MIN; ModeId <= ID_MAX; ++ModeId) {
1226       if (Val & (1 << ModeId)) {
1227         if (NeedComma)
1228           O << ',';
1229         O << IdSymbolic[ModeId];
1230         NeedComma = true;
1231       }
1232     }
1233     O << ')';
1234   }
1235 }
1236 
1237 void AMDGPUInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo,
1238                                         const MCSubtargetInfo &STI,
1239                                         raw_ostream &O) {
1240   printOperand(MI, OpNo, STI, O);
1241   O  << ", ";
1242   printOperand(MI, OpNo + 1, STI, O);
1243 }
1244 
1245 void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
1246                                    raw_ostream &O, StringRef Asm,
1247                                    StringRef Default) {
1248   const MCOperand &Op = MI->getOperand(OpNo);
1249   assert(Op.isImm());
1250   if (Op.getImm() == 1) {
1251     O << Asm;
1252   } else {
1253     O << Default;
1254   }
1255 }
1256 
1257 void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
1258                                    raw_ostream &O, char Asm) {
1259   const MCOperand &Op = MI->getOperand(OpNo);
1260   assert(Op.isImm());
1261   if (Op.getImm() == 1)
1262     O << Asm;
1263 }
1264 
1265 void AMDGPUInstPrinter::printHigh(const MCInst *MI, unsigned OpNo,
1266                                   const MCSubtargetInfo &STI,
1267                                   raw_ostream &O) {
1268   printNamedBit(MI, OpNo, O, "high");
1269 }
1270 
1271 void AMDGPUInstPrinter::printClampSI(const MCInst *MI, unsigned OpNo,
1272                                      const MCSubtargetInfo &STI,
1273                                      raw_ostream &O) {
1274   printNamedBit(MI, OpNo, O, "clamp");
1275 }
1276 
1277 void AMDGPUInstPrinter::printOModSI(const MCInst *MI, unsigned OpNo,
1278                                     const MCSubtargetInfo &STI,
1279                                     raw_ostream &O) {
1280   int Imm = MI->getOperand(OpNo).getImm();
1281   if (Imm == SIOutMods::MUL2)
1282     O << " mul:2";
1283   else if (Imm == SIOutMods::MUL4)
1284     O << " mul:4";
1285   else if (Imm == SIOutMods::DIV2)
1286     O << " div:2";
1287 }
1288 
1289 void AMDGPUInstPrinter::printSendMsg(const MCInst *MI, unsigned OpNo,
1290                                      const MCSubtargetInfo &STI,
1291                                      raw_ostream &O) {
1292   using namespace llvm::AMDGPU::SendMsg;
1293 
1294   const unsigned Imm16 = MI->getOperand(OpNo).getImm();
1295 
1296   uint16_t MsgId;
1297   uint16_t OpId;
1298   uint16_t StreamId;
1299   decodeMsg(Imm16, MsgId, OpId, StreamId, STI);
1300 
1301   StringRef MsgName = getMsgName(MsgId, STI);
1302 
1303   if (!MsgName.empty() && isValidMsgOp(MsgId, OpId, STI) &&
1304       isValidMsgStream(MsgId, OpId, StreamId, STI)) {
1305     O << "sendmsg(" << MsgName;
1306     if (msgRequiresOp(MsgId, STI)) {
1307       O << ", " << getMsgOpName(MsgId, OpId, STI);
1308       if (msgSupportsStream(MsgId, OpId, STI)) {
1309         O << ", " << StreamId;
1310       }
1311     }
1312     O << ')';
1313   } else if (encodeMsg(MsgId, OpId, StreamId) == Imm16) {
1314     O << "sendmsg(" << MsgId << ", " << OpId << ", " << StreamId << ')';
1315   } else {
1316     O << Imm16; // Unknown imm16 code.
1317   }
1318 }
1319 
1320 static void printSwizzleBitmask(const uint16_t AndMask,
1321                                 const uint16_t OrMask,
1322                                 const uint16_t XorMask,
1323                                 raw_ostream &O) {
1324   using namespace llvm::AMDGPU::Swizzle;
1325 
1326   uint16_t Probe0 = ((0            & AndMask) | OrMask) ^ XorMask;
1327   uint16_t Probe1 = ((BITMASK_MASK & AndMask) | OrMask) ^ XorMask;
1328 
1329   O << "\"";
1330 
1331   for (unsigned Mask = 1 << (BITMASK_WIDTH - 1); Mask > 0; Mask >>= 1) {
1332     uint16_t p0 = Probe0 & Mask;
1333     uint16_t p1 = Probe1 & Mask;
1334 
1335     if (p0 == p1) {
1336       if (p0 == 0) {
1337         O << "0";
1338       } else {
1339         O << "1";
1340       }
1341     } else {
1342       if (p0 == 0) {
1343         O << "p";
1344       } else {
1345         O << "i";
1346       }
1347     }
1348   }
1349 
1350   O << "\"";
1351 }
1352 
1353 void AMDGPUInstPrinter::printSwizzle(const MCInst *MI, unsigned OpNo,
1354                                      const MCSubtargetInfo &STI,
1355                                      raw_ostream &O) {
1356   using namespace llvm::AMDGPU::Swizzle;
1357 
1358   uint16_t Imm = MI->getOperand(OpNo).getImm();
1359   if (Imm == 0) {
1360     return;
1361   }
1362 
1363   O << " offset:";
1364 
1365   if ((Imm & QUAD_PERM_ENC_MASK) == QUAD_PERM_ENC) {
1366 
1367     O << "swizzle(" << IdSymbolic[ID_QUAD_PERM];
1368     for (unsigned I = 0; I < LANE_NUM; ++I) {
1369       O << ",";
1370       O << formatDec(Imm & LANE_MASK);
1371       Imm >>= LANE_SHIFT;
1372     }
1373     O << ")";
1374 
1375   } else if ((Imm & BITMASK_PERM_ENC_MASK) == BITMASK_PERM_ENC) {
1376 
1377     uint16_t AndMask = (Imm >> BITMASK_AND_SHIFT) & BITMASK_MASK;
1378     uint16_t OrMask  = (Imm >> BITMASK_OR_SHIFT)  & BITMASK_MASK;
1379     uint16_t XorMask = (Imm >> BITMASK_XOR_SHIFT) & BITMASK_MASK;
1380 
1381     if (AndMask == BITMASK_MAX &&
1382         OrMask == 0 &&
1383         countPopulation(XorMask) == 1) {
1384 
1385       O << "swizzle(" << IdSymbolic[ID_SWAP];
1386       O << ",";
1387       O << formatDec(XorMask);
1388       O << ")";
1389 
1390     } else if (AndMask == BITMASK_MAX &&
1391                OrMask == 0 && XorMask > 0 &&
1392                isPowerOf2_64(XorMask + 1)) {
1393 
1394       O << "swizzle(" << IdSymbolic[ID_REVERSE];
1395       O << ",";
1396       O << formatDec(XorMask + 1);
1397       O << ")";
1398 
1399     } else {
1400 
1401       uint16_t GroupSize = BITMASK_MAX - AndMask + 1;
1402       if (GroupSize > 1 &&
1403           isPowerOf2_64(GroupSize) &&
1404           OrMask < GroupSize &&
1405           XorMask == 0) {
1406 
1407         O << "swizzle(" << IdSymbolic[ID_BROADCAST];
1408         O << ",";
1409         O << formatDec(GroupSize);
1410         O << ",";
1411         O << formatDec(OrMask);
1412         O << ")";
1413 
1414       } else {
1415         O << "swizzle(" << IdSymbolic[ID_BITMASK_PERM];
1416         O << ",";
1417         printSwizzleBitmask(AndMask, OrMask, XorMask, O);
1418         O << ")";
1419       }
1420     }
1421   } else {
1422     printU16ImmDecOperand(MI, OpNo, O);
1423   }
1424 }
1425 
1426 void AMDGPUInstPrinter::printWaitFlag(const MCInst *MI, unsigned OpNo,
1427                                       const MCSubtargetInfo &STI,
1428                                       raw_ostream &O) {
1429   AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(STI.getCPU());
1430 
1431   unsigned SImm16 = MI->getOperand(OpNo).getImm();
1432   unsigned Vmcnt, Expcnt, Lgkmcnt;
1433   decodeWaitcnt(ISA, SImm16, Vmcnt, Expcnt, Lgkmcnt);
1434 
1435   bool IsDefaultVmcnt = Vmcnt == getVmcntBitMask(ISA);
1436   bool IsDefaultExpcnt = Expcnt == getExpcntBitMask(ISA);
1437   bool IsDefaultLgkmcnt = Lgkmcnt == getLgkmcntBitMask(ISA);
1438   bool PrintAll = IsDefaultVmcnt && IsDefaultExpcnt && IsDefaultLgkmcnt;
1439 
1440   bool NeedSpace = false;
1441 
1442   if (!IsDefaultVmcnt || PrintAll) {
1443     O << "vmcnt(" << Vmcnt << ')';
1444     NeedSpace = true;
1445   }
1446 
1447   if (!IsDefaultExpcnt || PrintAll) {
1448     if (NeedSpace)
1449       O << ' ';
1450     O << "expcnt(" << Expcnt << ')';
1451     NeedSpace = true;
1452   }
1453 
1454   if (!IsDefaultLgkmcnt || PrintAll) {
1455     if (NeedSpace)
1456       O << ' ';
1457     O << "lgkmcnt(" << Lgkmcnt << ')';
1458   }
1459 }
1460 
1461 void AMDGPUInstPrinter::printDepCtr(const MCInst *MI, unsigned OpNo,
1462                                     const MCSubtargetInfo &STI,
1463                                     raw_ostream &O) {
1464   using namespace llvm::AMDGPU::DepCtr;
1465 
1466   uint64_t Imm16 = MI->getOperand(OpNo).getImm() & 0xffff;
1467 
1468   bool HasNonDefaultVal = false;
1469   if (isSymbolicDepCtrEncoding(Imm16, HasNonDefaultVal, STI)) {
1470     int Id = 0;
1471     StringRef Name;
1472     unsigned Val;
1473     bool IsDefault;
1474     bool NeedSpace = false;
1475     while (decodeDepCtr(Imm16, Id, Name, Val, IsDefault, STI)) {
1476       if (!IsDefault || !HasNonDefaultVal) {
1477         if (NeedSpace)
1478           O << ' ';
1479         O << Name << '(' << Val << ')';
1480         NeedSpace = true;
1481       }
1482     }
1483   } else {
1484     O << formatHex(Imm16);
1485   }
1486 }
1487 
1488 void AMDGPUInstPrinter::printDelayFlag(const MCInst *MI, unsigned OpNo,
1489                                        const MCSubtargetInfo &STI,
1490                                        raw_ostream &O) {
1491   const char *BadInstId = "/* invalid instid value */";
1492   static const std::array<const char *, 12> InstIds = {
1493       "NO_DEP",        "VALU_DEP_1",    "VALU_DEP_2",
1494       "VALU_DEP_3",    "VALU_DEP_4",    "TRANS32_DEP_1",
1495       "TRANS32_DEP_2", "TRANS32_DEP_3", "FMA_ACCUM_CYCLE_1",
1496       "SALU_CYCLE_1",  "SALU_CYCLE_2",  "SALU_CYCLE_3"};
1497 
1498   const char *BadInstSkip = "/* invalid instskip value */";
1499   static const std::array<const char *, 6> InstSkips = {
1500       "SAME", "NEXT", "SKIP_1", "SKIP_2", "SKIP_3", "SKIP_4"};
1501 
1502   unsigned SImm16 = MI->getOperand(OpNo).getImm();
1503   const char *Prefix = "";
1504 
1505   unsigned Value = SImm16 & 0xF;
1506   if (Value) {
1507     const char *Name = Value < InstIds.size() ? InstIds[Value] : BadInstId;
1508     O << Prefix << "instid0(" << Name << ')';
1509     Prefix = " | ";
1510   }
1511 
1512   Value = (SImm16 >> 4) & 7;
1513   if (Value) {
1514     const char *Name =
1515         Value < InstSkips.size() ? InstSkips[Value] : BadInstSkip;
1516     O << Prefix << "instskip(" << Name << ')';
1517     Prefix = " | ";
1518   }
1519 
1520   Value = (SImm16 >> 7) & 0xF;
1521   if (Value) {
1522     const char *Name = Value < InstIds.size() ? InstIds[Value] : BadInstId;
1523     O << Prefix << "instid1(" << Name << ')';
1524     Prefix = " | ";
1525   }
1526 
1527   if (!*Prefix)
1528     O << "0";
1529 }
1530 
1531 void AMDGPUInstPrinter::printHwreg(const MCInst *MI, unsigned OpNo,
1532                                    const MCSubtargetInfo &STI, raw_ostream &O) {
1533   unsigned Id;
1534   unsigned Offset;
1535   unsigned Width;
1536 
1537   using namespace llvm::AMDGPU::Hwreg;
1538   unsigned Val = MI->getOperand(OpNo).getImm();
1539   decodeHwreg(Val, Id, Offset, Width);
1540   StringRef HwRegName = getHwreg(Id, STI);
1541 
1542   O << "hwreg(";
1543   if (!HwRegName.empty()) {
1544     O << HwRegName;
1545   } else {
1546     O << Id;
1547   }
1548   if (Width != WIDTH_DEFAULT_ || Offset != OFFSET_DEFAULT_) {
1549     O << ", " << Offset << ", " << Width;
1550   }
1551   O << ')';
1552 }
1553 
1554 void AMDGPUInstPrinter::printEndpgm(const MCInst *MI, unsigned OpNo,
1555                                     const MCSubtargetInfo &STI,
1556                                     raw_ostream &O) {
1557   uint16_t Imm = MI->getOperand(OpNo).getImm();
1558   if (Imm == 0) {
1559     return;
1560   }
1561 
1562   O << ' ' << formatDec(Imm);
1563 }
1564 
1565 #include "AMDGPUGenAsmWriter.inc"
1566