1 //===-- AMDGPUInstPrinter.cpp - AMDGPU MC Inst -> ASM ---------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 // \file
8 //===----------------------------------------------------------------------===//
9 
10 #include "AMDGPUInstPrinter.h"
11 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
12 #include "SIDefines.h"
13 #include "SIRegisterInfo.h"
14 #include "Utils/AMDGPUAsmUtils.h"
15 #include "Utils/AMDGPUBaseInfo.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCInstrDesc.h"
19 #include "llvm/MC/MCInstrInfo.h"
20 #include "llvm/MC/MCSubtargetInfo.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/TargetParser.h"
23 
24 using namespace llvm;
25 using namespace llvm::AMDGPU;
26 
27 static cl::opt<bool> Keep16BitSuffixes(
28   "amdgpu-keep-16-bit-reg-suffixes",
29   cl::desc("Keep .l and .h suffixes in asm for debugging purposes"),
30   cl::init(false),
31   cl::ReallyHidden);
32 
33 void AMDGPUInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
34   // FIXME: The current implementation of
35   // AsmParser::parseRegisterOrRegisterNumber in MC implies we either emit this
36   // as an integer or we provide a name which represents a physical register.
37   // For CFI instructions we really want to emit a name for the DWARF register
38   // instead, because there may be multiple DWARF registers corresponding to a
39   // single physical register. One case where this problem manifests is with
40   // wave32/wave64 where using the physical register name is ambiguous: if we
41   // write e.g. `.cfi_undefined v0` we lose information about the wavefront
42   // size which we need to encode the register in the final DWARF. Ideally we
43   // would extend MC to support parsing DWARF register names so we could do
44   // something like `.cfi_undefined dwarf_wave32_v0`. For now we just live with
45   // non-pretty DWARF register names in assembly text.
46   OS << RegNo;
47 }
48 
49 void AMDGPUInstPrinter::printInst(const MCInst *MI, uint64_t Address,
50                                   StringRef Annot, const MCSubtargetInfo &STI,
51                                   raw_ostream &OS) {
52   OS.flush();
53   printInstruction(MI, Address, STI, OS);
54   printAnnotation(OS, Annot);
55 }
56 
57 void AMDGPUInstPrinter::printU4ImmOperand(const MCInst *MI, unsigned OpNo,
58                                           const MCSubtargetInfo &STI,
59                                           raw_ostream &O) {
60   O << formatHex(MI->getOperand(OpNo).getImm() & 0xf);
61 }
62 
63 void AMDGPUInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo,
64                                           raw_ostream &O) {
65   O << formatHex(MI->getOperand(OpNo).getImm() & 0xff);
66 }
67 
68 void AMDGPUInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
69                                            const MCSubtargetInfo &STI,
70                                            raw_ostream &O) {
71   // It's possible to end up with a 32-bit literal used with a 16-bit operand
72   // with ignored high bits. Print as 32-bit anyway in that case.
73   int64_t Imm = MI->getOperand(OpNo).getImm();
74   if (isInt<16>(Imm) || isUInt<16>(Imm))
75     O << formatHex(static_cast<uint64_t>(Imm & 0xffff));
76   else
77     printU32ImmOperand(MI, OpNo, STI, O);
78 }
79 
80 void AMDGPUInstPrinter::printU4ImmDecOperand(const MCInst *MI, unsigned OpNo,
81                                              raw_ostream &O) {
82   O << formatDec(MI->getOperand(OpNo).getImm() & 0xf);
83 }
84 
85 void AMDGPUInstPrinter::printU8ImmDecOperand(const MCInst *MI, unsigned OpNo,
86                                              raw_ostream &O) {
87   O << formatDec(MI->getOperand(OpNo).getImm() & 0xff);
88 }
89 
90 void AMDGPUInstPrinter::printU16ImmDecOperand(const MCInst *MI, unsigned OpNo,
91                                               raw_ostream &O) {
92   O << formatDec(MI->getOperand(OpNo).getImm() & 0xffff);
93 }
94 
95 void AMDGPUInstPrinter::printU32ImmOperand(const MCInst *MI, unsigned OpNo,
96                                            const MCSubtargetInfo &STI,
97                                            raw_ostream &O) {
98   O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff);
99 }
100 
101 void AMDGPUInstPrinter::printNamedBit(const MCInst *MI, unsigned OpNo,
102                                       raw_ostream &O, StringRef BitName) {
103   if (MI->getOperand(OpNo).getImm()) {
104     O << ' ' << BitName;
105   }
106 }
107 
108 void AMDGPUInstPrinter::printOffen(const MCInst *MI, unsigned OpNo,
109                                    raw_ostream &O) {
110   printNamedBit(MI, OpNo, O, "offen");
111 }
112 
113 void AMDGPUInstPrinter::printIdxen(const MCInst *MI, unsigned OpNo,
114                                    raw_ostream &O) {
115   printNamedBit(MI, OpNo, O, "idxen");
116 }
117 
118 void AMDGPUInstPrinter::printAddr64(const MCInst *MI, unsigned OpNo,
119                                     raw_ostream &O) {
120   printNamedBit(MI, OpNo, O, "addr64");
121 }
122 
123 void AMDGPUInstPrinter::printMBUFOffset(const MCInst *MI, unsigned OpNo,
124                                         raw_ostream &O) {
125   if (MI->getOperand(OpNo).getImm()) {
126     O << " offset:";
127     printU16ImmDecOperand(MI, OpNo, O);
128   }
129 }
130 
131 void AMDGPUInstPrinter::printOffset(const MCInst *MI, unsigned OpNo,
132                                     const MCSubtargetInfo &STI,
133                                     raw_ostream &O) {
134   uint16_t Imm = MI->getOperand(OpNo).getImm();
135   if (Imm != 0) {
136     O << " offset:";
137     printU16ImmDecOperand(MI, OpNo, O);
138   }
139 }
140 
141 void AMDGPUInstPrinter::printFlatOffset(const MCInst *MI, unsigned OpNo,
142                                         const MCSubtargetInfo &STI,
143                                         raw_ostream &O) {
144   uint16_t Imm = MI->getOperand(OpNo).getImm();
145   if (Imm != 0) {
146     O << " offset:";
147 
148     const MCInstrDesc &Desc = MII.get(MI->getOpcode());
149     bool IsFlatSeg = !(Desc.TSFlags &
150                        (SIInstrFlags::FlatGlobal | SIInstrFlags::FlatScratch));
151 
152     if (IsFlatSeg) { // Unsigned offset
153       printU16ImmDecOperand(MI, OpNo, O);
154     } else {         // Signed offset
155       if (AMDGPU::isGFX10Plus(STI)) {
156         O << formatDec(SignExtend32<12>(MI->getOperand(OpNo).getImm()));
157       } else {
158         O << formatDec(SignExtend32<13>(MI->getOperand(OpNo).getImm()));
159       }
160     }
161   }
162 }
163 
164 void AMDGPUInstPrinter::printOffset0(const MCInst *MI, unsigned OpNo,
165                                      const MCSubtargetInfo &STI,
166                                      raw_ostream &O) {
167   if (MI->getOperand(OpNo).getImm()) {
168     O << " offset0:";
169     printU8ImmDecOperand(MI, OpNo, O);
170   }
171 }
172 
173 void AMDGPUInstPrinter::printOffset1(const MCInst *MI, unsigned OpNo,
174                                      const MCSubtargetInfo &STI,
175                                      raw_ostream &O) {
176   if (MI->getOperand(OpNo).getImm()) {
177     O << " offset1:";
178     printU8ImmDecOperand(MI, OpNo, O);
179   }
180 }
181 
182 void AMDGPUInstPrinter::printSMRDOffset8(const MCInst *MI, unsigned OpNo,
183                                         const MCSubtargetInfo &STI,
184                                         raw_ostream &O) {
185   printU32ImmOperand(MI, OpNo, STI, O);
186 }
187 
188 void AMDGPUInstPrinter::printSMEMOffset(const MCInst *MI, unsigned OpNo,
189                                         const MCSubtargetInfo &STI,
190                                         raw_ostream &O) {
191   O << formatHex(MI->getOperand(OpNo).getImm());
192 }
193 
194 void AMDGPUInstPrinter::printSMEMOffsetMod(const MCInst *MI, unsigned OpNo,
195                                            const MCSubtargetInfo &STI,
196                                            raw_ostream &O) {
197   O << " offset:";
198   printSMEMOffset(MI, OpNo, STI, O);
199 }
200 
201 void AMDGPUInstPrinter::printSMRDLiteralOffset(const MCInst *MI, unsigned OpNo,
202                                                const MCSubtargetInfo &STI,
203                                                raw_ostream &O) {
204   printU32ImmOperand(MI, OpNo, STI, O);
205 }
206 
207 void AMDGPUInstPrinter::printGDS(const MCInst *MI, unsigned OpNo,
208                                  const MCSubtargetInfo &STI, raw_ostream &O) {
209   printNamedBit(MI, OpNo, O, "gds");
210 }
211 
212 void AMDGPUInstPrinter::printCPol(const MCInst *MI, unsigned OpNo,
213                                   const MCSubtargetInfo &STI, raw_ostream &O) {
214   auto Imm = MI->getOperand(OpNo).getImm();
215   if (Imm & CPol::GLC)
216     O << ((AMDGPU::isGFX940(STI) &&
217            !(MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::SMRD)) ? " sc0"
218                                                                      : " glc");
219   if (Imm & CPol::SLC)
220     O << (AMDGPU::isGFX940(STI) ? " nt" : " slc");
221   if ((Imm & CPol::DLC) && AMDGPU::isGFX10Plus(STI))
222     O << " dlc";
223   if ((Imm & CPol::SCC) && AMDGPU::isGFX90A(STI))
224     O << (AMDGPU::isGFX940(STI) ? " sc1" : " scc");
225   if (Imm & ~CPol::ALL)
226     O << " /* unexpected cache policy bit */";
227 }
228 
229 void AMDGPUInstPrinter::printSWZ(const MCInst *MI, unsigned OpNo,
230                                  const MCSubtargetInfo &STI, raw_ostream &O) {
231 }
232 
233 void AMDGPUInstPrinter::printTFE(const MCInst *MI, unsigned OpNo,
234                                  const MCSubtargetInfo &STI, raw_ostream &O) {
235   printNamedBit(MI, OpNo, O, "tfe");
236 }
237 
238 void AMDGPUInstPrinter::printDMask(const MCInst *MI, unsigned OpNo,
239                                    const MCSubtargetInfo &STI, raw_ostream &O) {
240   if (MI->getOperand(OpNo).getImm()) {
241     O << " dmask:";
242     printU16ImmOperand(MI, OpNo, STI, O);
243   }
244 }
245 
246 void AMDGPUInstPrinter::printDim(const MCInst *MI, unsigned OpNo,
247                                  const MCSubtargetInfo &STI, raw_ostream &O) {
248   unsigned Dim = MI->getOperand(OpNo).getImm();
249   O << " dim:SQ_RSRC_IMG_";
250 
251   const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfoByEncoding(Dim);
252   if (DimInfo)
253     O << DimInfo->AsmSuffix;
254   else
255     O << Dim;
256 }
257 
258 void AMDGPUInstPrinter::printUNorm(const MCInst *MI, unsigned OpNo,
259                                    const MCSubtargetInfo &STI, raw_ostream &O) {
260   printNamedBit(MI, OpNo, O, "unorm");
261 }
262 
263 void AMDGPUInstPrinter::printDA(const MCInst *MI, unsigned OpNo,
264                                 const MCSubtargetInfo &STI, raw_ostream &O) {
265   printNamedBit(MI, OpNo, O, "da");
266 }
267 
268 void AMDGPUInstPrinter::printR128A16(const MCInst *MI, unsigned OpNo,
269                                   const MCSubtargetInfo &STI, raw_ostream &O) {
270   if (STI.hasFeature(AMDGPU::FeatureR128A16))
271     printNamedBit(MI, OpNo, O, "a16");
272   else
273     printNamedBit(MI, OpNo, O, "r128");
274 }
275 
276 void AMDGPUInstPrinter::printGFX10A16(const MCInst *MI, unsigned OpNo,
277                                   const MCSubtargetInfo &STI, raw_ostream &O) {
278   printNamedBit(MI, OpNo, O, "a16");
279 }
280 
281 void AMDGPUInstPrinter::printLWE(const MCInst *MI, unsigned OpNo,
282                                  const MCSubtargetInfo &STI, raw_ostream &O) {
283   printNamedBit(MI, OpNo, O, "lwe");
284 }
285 
286 void AMDGPUInstPrinter::printD16(const MCInst *MI, unsigned OpNo,
287                                  const MCSubtargetInfo &STI, raw_ostream &O) {
288   printNamedBit(MI, OpNo, O, "d16");
289 }
290 
291 void AMDGPUInstPrinter::printExpCompr(const MCInst *MI, unsigned OpNo,
292                                       const MCSubtargetInfo &STI,
293                                       raw_ostream &O) {
294   printNamedBit(MI, OpNo, O, "compr");
295 }
296 
297 void AMDGPUInstPrinter::printExpVM(const MCInst *MI, unsigned OpNo,
298                                    const MCSubtargetInfo &STI,
299                                    raw_ostream &O) {
300   printNamedBit(MI, OpNo, O, "vm");
301 }
302 
303 void AMDGPUInstPrinter::printFORMAT(const MCInst *MI, unsigned OpNo,
304                                     const MCSubtargetInfo &STI,
305                                     raw_ostream &O) {
306 }
307 
308 void AMDGPUInstPrinter::printSymbolicFormat(const MCInst *MI,
309                                             const MCSubtargetInfo &STI,
310                                             raw_ostream &O) {
311   using namespace llvm::AMDGPU::MTBUFFormat;
312 
313   int OpNo =
314     AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::format);
315   assert(OpNo != -1);
316 
317   unsigned Val = MI->getOperand(OpNo).getImm();
318   if (AMDGPU::isGFX10Plus(STI)) {
319     if (Val == UFMT_DEFAULT)
320       return;
321     if (isValidUnifiedFormat(Val)) {
322       O << " format:[" << getUnifiedFormatName(Val) << ']';
323     } else {
324       O << " format:" << Val;
325     }
326   } else {
327     if (Val == DFMT_NFMT_DEFAULT)
328       return;
329     if (isValidDfmtNfmt(Val, STI)) {
330       unsigned Dfmt;
331       unsigned Nfmt;
332       decodeDfmtNfmt(Val, Dfmt, Nfmt);
333       O << " format:[";
334       if (Dfmt != DFMT_DEFAULT) {
335         O << getDfmtName(Dfmt);
336         if (Nfmt != NFMT_DEFAULT) {
337           O << ',';
338         }
339       }
340       if (Nfmt != NFMT_DEFAULT) {
341         O << getNfmtName(Nfmt, STI);
342       }
343       O << ']';
344     } else {
345       O << " format:" << Val;
346     }
347   }
348 }
349 
350 void AMDGPUInstPrinter::printRegOperand(unsigned RegNo, raw_ostream &O,
351                                         const MCRegisterInfo &MRI) {
352 #if !defined(NDEBUG)
353   switch (RegNo) {
354   case AMDGPU::FP_REG:
355   case AMDGPU::SP_REG:
356   case AMDGPU::PRIVATE_RSRC_REG:
357     llvm_unreachable("pseudo-register should not ever be emitted");
358   case AMDGPU::SCC:
359     llvm_unreachable("pseudo scc should not ever be emitted");
360   default:
361     break;
362   }
363 #endif
364 
365   StringRef RegName(getRegisterName(RegNo));
366   if (!Keep16BitSuffixes)
367     if (!RegName.consume_back(".l"))
368       RegName.consume_back(".h");
369 
370   O << RegName;
371 }
372 
373 void AMDGPUInstPrinter::printVOPDst(const MCInst *MI, unsigned OpNo,
374                                     const MCSubtargetInfo &STI,
375                                     raw_ostream &O) {
376   auto Opcode = MI->getOpcode();
377   auto Flags = MII.get(Opcode).TSFlags;
378 
379   if (OpNo == 0) {
380     if (Flags & SIInstrFlags::VOP3) {
381       if (!getVOP3IsSingle(Opcode))
382         O << "_e64";
383     } else if (Flags & SIInstrFlags::DPP) {
384       O << "_dpp";
385     } else if (Flags & SIInstrFlags::SDWA) {
386       O << "_sdwa";
387     } else if (((Flags & SIInstrFlags::VOP1) && !getVOP1IsSingle(Opcode)) ||
388                ((Flags & SIInstrFlags::VOP2) && !getVOP2IsSingle(Opcode))) {
389       O << "_e32";
390     }
391     O << " ";
392   }
393 
394   printOperand(MI, OpNo, STI, O);
395 
396   // Print default vcc/vcc_lo operand.
397   switch (Opcode) {
398   default: break;
399 
400   case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10:
401   case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10:
402   case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10:
403   case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10:
404   case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10:
405   case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10:
406   case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10:
407   case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10:
408   case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10:
409   case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10:
410   case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10:
411   case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10:
412     printDefaultVccOperand(1, STI, O);
413     break;
414   }
415 }
416 
417 void AMDGPUInstPrinter::printVINTRPDst(const MCInst *MI, unsigned OpNo,
418                                        const MCSubtargetInfo &STI, raw_ostream &O) {
419   if (AMDGPU::isSI(STI) || AMDGPU::isCI(STI))
420     O << " ";
421   else
422     O << "_e32 ";
423 
424   printOperand(MI, OpNo, STI, O);
425 }
426 
427 void AMDGPUInstPrinter::printImmediateInt16(uint32_t Imm,
428                                             const MCSubtargetInfo &STI,
429                                             raw_ostream &O) {
430   int16_t SImm = static_cast<int16_t>(Imm);
431   if (isInlinableIntLiteral(SImm)) {
432     O << SImm;
433   } else {
434     uint64_t Imm16 = static_cast<uint16_t>(Imm);
435     O << formatHex(Imm16);
436   }
437 }
438 
439 void AMDGPUInstPrinter::printImmediate16(uint32_t Imm,
440                                          const MCSubtargetInfo &STI,
441                                          raw_ostream &O) {
442   int16_t SImm = static_cast<int16_t>(Imm);
443   if (isInlinableIntLiteral(SImm)) {
444     O << SImm;
445     return;
446   }
447 
448   if (Imm == 0x3C00)
449     O<< "1.0";
450   else if (Imm == 0xBC00)
451     O<< "-1.0";
452   else if (Imm == 0x3800)
453     O<< "0.5";
454   else if (Imm == 0xB800)
455     O<< "-0.5";
456   else if (Imm == 0x4000)
457     O<< "2.0";
458   else if (Imm == 0xC000)
459     O<< "-2.0";
460   else if (Imm == 0x4400)
461     O<< "4.0";
462   else if (Imm == 0xC400)
463     O<< "-4.0";
464   else if (Imm == 0x3118 &&
465            STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]) {
466     O << "0.15915494";
467   } else {
468     uint64_t Imm16 = static_cast<uint16_t>(Imm);
469     O << formatHex(Imm16);
470   }
471 }
472 
473 void AMDGPUInstPrinter::printImmediateV216(uint32_t Imm,
474                                            const MCSubtargetInfo &STI,
475                                            raw_ostream &O) {
476   uint16_t Lo16 = static_cast<uint16_t>(Imm);
477   printImmediate16(Lo16, STI, O);
478 }
479 
480 void AMDGPUInstPrinter::printImmediate32(uint32_t Imm,
481                                          const MCSubtargetInfo &STI,
482                                          raw_ostream &O) {
483   int32_t SImm = static_cast<int32_t>(Imm);
484   if (SImm >= -16 && SImm <= 64) {
485     O << SImm;
486     return;
487   }
488 
489   if (Imm == FloatToBits(0.0f))
490     O << "0.0";
491   else if (Imm == FloatToBits(1.0f))
492     O << "1.0";
493   else if (Imm == FloatToBits(-1.0f))
494     O << "-1.0";
495   else if (Imm == FloatToBits(0.5f))
496     O << "0.5";
497   else if (Imm == FloatToBits(-0.5f))
498     O << "-0.5";
499   else if (Imm == FloatToBits(2.0f))
500     O << "2.0";
501   else if (Imm == FloatToBits(-2.0f))
502     O << "-2.0";
503   else if (Imm == FloatToBits(4.0f))
504     O << "4.0";
505   else if (Imm == FloatToBits(-4.0f))
506     O << "-4.0";
507   else if (Imm == 0x3e22f983 &&
508            STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
509     O << "0.15915494";
510   else
511     O << formatHex(static_cast<uint64_t>(Imm));
512 }
513 
514 void AMDGPUInstPrinter::printImmediate64(uint64_t Imm,
515                                          const MCSubtargetInfo &STI,
516                                          raw_ostream &O) {
517   int64_t SImm = static_cast<int64_t>(Imm);
518   if (SImm >= -16 && SImm <= 64) {
519     O << SImm;
520     return;
521   }
522 
523   if (Imm == DoubleToBits(0.0))
524     O << "0.0";
525   else if (Imm == DoubleToBits(1.0))
526     O << "1.0";
527   else if (Imm == DoubleToBits(-1.0))
528     O << "-1.0";
529   else if (Imm == DoubleToBits(0.5))
530     O << "0.5";
531   else if (Imm == DoubleToBits(-0.5))
532     O << "-0.5";
533   else if (Imm == DoubleToBits(2.0))
534     O << "2.0";
535   else if (Imm == DoubleToBits(-2.0))
536     O << "-2.0";
537   else if (Imm == DoubleToBits(4.0))
538     O << "4.0";
539   else if (Imm == DoubleToBits(-4.0))
540     O << "-4.0";
541   else if (Imm == 0x3fc45f306dc9c882 &&
542            STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
543     O << "0.15915494309189532";
544   else {
545     assert(isUInt<32>(Imm) || Imm == 0x3fc45f306dc9c882);
546 
547     // In rare situations, we will have a 32-bit literal in a 64-bit
548     // operand. This is technically allowed for the encoding of s_mov_b64.
549     O << formatHex(static_cast<uint64_t>(Imm));
550   }
551 }
552 
553 void AMDGPUInstPrinter::printBLGP(const MCInst *MI, unsigned OpNo,
554                                   const MCSubtargetInfo &STI,
555                                   raw_ostream &O) {
556   unsigned Imm = MI->getOperand(OpNo).getImm();
557   if (!Imm)
558     return;
559 
560   if (AMDGPU::isGFX940(STI)) {
561     switch (MI->getOpcode()) {
562     case AMDGPU::V_MFMA_F64_16X16X4F64_gfx940_acd:
563     case AMDGPU::V_MFMA_F64_16X16X4F64_gfx940_vcd:
564     case AMDGPU::V_MFMA_F64_4X4X4F64_gfx940_acd:
565     case AMDGPU::V_MFMA_F64_4X4X4F64_gfx940_vcd:
566       O << " neg:[" << (Imm & 1) << ',' << ((Imm >> 1) & 1) << ','
567         << ((Imm >> 2) & 1) << ']';
568       return;
569     }
570   }
571 
572   O << " blgp:" << Imm;
573 }
574 
575 void AMDGPUInstPrinter::printCBSZ(const MCInst *MI, unsigned OpNo,
576                                   const MCSubtargetInfo &STI,
577                                   raw_ostream &O) {
578   unsigned Imm = MI->getOperand(OpNo).getImm();
579   if (!Imm)
580     return;
581 
582   O << " cbsz:" << Imm;
583 }
584 
585 void AMDGPUInstPrinter::printABID(const MCInst *MI, unsigned OpNo,
586                                   const MCSubtargetInfo &STI,
587                                   raw_ostream &O) {
588   unsigned Imm = MI->getOperand(OpNo).getImm();
589   if (!Imm)
590     return;
591 
592   O << " abid:" << Imm;
593 }
594 
595 void AMDGPUInstPrinter::printDefaultVccOperand(unsigned OpNo,
596                                                const MCSubtargetInfo &STI,
597                                                raw_ostream &O) {
598   if (OpNo > 0)
599     O << ", ";
600   printRegOperand(STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ?
601                   AMDGPU::VCC : AMDGPU::VCC_LO, O, MRI);
602   if (OpNo == 0)
603     O << ", ";
604 }
605 
606 void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
607                                      const MCSubtargetInfo &STI,
608                                      raw_ostream &O) {
609   // Print default vcc/vcc_lo operand of VOPC.
610   const MCInstrDesc &Desc = MII.get(MI->getOpcode());
611   if (OpNo == 0 && (Desc.TSFlags & SIInstrFlags::VOPC) &&
612       (Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC) ||
613        Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC_LO)))
614     printDefaultVccOperand(OpNo, STI, O);
615 
616   if (OpNo >= MI->getNumOperands()) {
617     O << "/*Missing OP" << OpNo << "*/";
618     return;
619   }
620 
621   const MCOperand &Op = MI->getOperand(OpNo);
622   if (Op.isReg()) {
623     printRegOperand(Op.getReg(), O, MRI);
624   } else if (Op.isImm()) {
625     const uint8_t OpTy = Desc.OpInfo[OpNo].OperandType;
626     switch (OpTy) {
627     case AMDGPU::OPERAND_REG_IMM_INT32:
628     case AMDGPU::OPERAND_REG_IMM_FP32:
629     case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED:
630     case AMDGPU::OPERAND_REG_INLINE_C_INT32:
631     case AMDGPU::OPERAND_REG_INLINE_C_FP32:
632     case AMDGPU::OPERAND_REG_INLINE_AC_INT32:
633     case AMDGPU::OPERAND_REG_INLINE_AC_FP32:
634     case AMDGPU::OPERAND_REG_IMM_V2INT32:
635     case AMDGPU::OPERAND_REG_IMM_V2FP32:
636     case AMDGPU::OPERAND_REG_INLINE_C_V2INT32:
637     case AMDGPU::OPERAND_REG_INLINE_C_V2FP32:
638     case MCOI::OPERAND_IMMEDIATE:
639       printImmediate32(Op.getImm(), STI, O);
640       break;
641     case AMDGPU::OPERAND_REG_IMM_INT64:
642     case AMDGPU::OPERAND_REG_IMM_FP64:
643     case AMDGPU::OPERAND_REG_INLINE_C_INT64:
644     case AMDGPU::OPERAND_REG_INLINE_C_FP64:
645     case AMDGPU::OPERAND_REG_INLINE_AC_FP64:
646       printImmediate64(Op.getImm(), STI, O);
647       break;
648     case AMDGPU::OPERAND_REG_INLINE_C_INT16:
649     case AMDGPU::OPERAND_REG_INLINE_AC_INT16:
650     case AMDGPU::OPERAND_REG_IMM_INT16:
651       printImmediateInt16(Op.getImm(), STI, O);
652       break;
653     case AMDGPU::OPERAND_REG_INLINE_C_FP16:
654     case AMDGPU::OPERAND_REG_INLINE_AC_FP16:
655     case AMDGPU::OPERAND_REG_IMM_FP16:
656     case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED:
657       printImmediate16(Op.getImm(), STI, O);
658       break;
659     case AMDGPU::OPERAND_REG_IMM_V2INT16:
660     case AMDGPU::OPERAND_REG_IMM_V2FP16:
661       if (!isUInt<16>(Op.getImm()) &&
662           STI.getFeatureBits()[AMDGPU::FeatureVOP3Literal]) {
663         printImmediate32(Op.getImm(), STI, O);
664         break;
665       }
666 
667       //  Deal with 16-bit FP inline immediates not working.
668       if (OpTy == AMDGPU::OPERAND_REG_IMM_V2FP16) {
669         printImmediate16(static_cast<uint16_t>(Op.getImm()), STI, O);
670         break;
671       }
672       LLVM_FALLTHROUGH;
673     case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
674     case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:
675       printImmediateInt16(static_cast<uint16_t>(Op.getImm()), STI, O);
676       break;
677     case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
678     case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16:
679       printImmediateV216(Op.getImm(), STI, O);
680       break;
681     case MCOI::OPERAND_UNKNOWN:
682     case MCOI::OPERAND_PCREL:
683       O << formatDec(Op.getImm());
684       break;
685     case MCOI::OPERAND_REGISTER:
686       // FIXME: This should be removed and handled somewhere else. Seems to come
687       // from a disassembler bug.
688       O << "/*invalid immediate*/";
689       break;
690     default:
691       // We hit this for the immediate instruction bits that don't yet have a
692       // custom printer.
693       llvm_unreachable("unexpected immediate operand type");
694     }
695   } else if (Op.isDFPImm()) {
696     double Value = bit_cast<double>(Op.getDFPImm());
697     // We special case 0.0 because otherwise it will be printed as an integer.
698     if (Value == 0.0)
699       O << "0.0";
700     else {
701       const MCInstrDesc &Desc = MII.get(MI->getOpcode());
702       int RCID = Desc.OpInfo[OpNo].RegClass;
703       unsigned RCBits = AMDGPU::getRegBitWidth(MRI.getRegClass(RCID));
704       if (RCBits == 32)
705         printImmediate32(FloatToBits(Value), STI, O);
706       else if (RCBits == 64)
707         printImmediate64(DoubleToBits(Value), STI, O);
708       else
709         llvm_unreachable("Invalid register class size");
710     }
711   } else if (Op.isExpr()) {
712     const MCExpr *Exp = Op.getExpr();
713     Exp->print(O, &MAI);
714   } else {
715     O << "/*INV_OP*/";
716   }
717 
718   // Print default vcc/vcc_lo operand of v_cndmask_b32_e32.
719   switch (MI->getOpcode()) {
720   default: break;
721 
722   case AMDGPU::V_CNDMASK_B32_e32_gfx10:
723   case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10:
724   case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10:
725   case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10:
726   case AMDGPU::V_CNDMASK_B32_dpp_gfx10:
727   case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10:
728   case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10:
729   case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10:
730   case AMDGPU::V_CNDMASK_B32_dpp8_gfx10:
731   case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10:
732   case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10:
733   case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10:
734 
735   case AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7:
736   case AMDGPU::V_CNDMASK_B32_e32_vi:
737     if ((int)OpNo == AMDGPU::getNamedOperandIdx(MI->getOpcode(),
738                                                 AMDGPU::OpName::src1))
739       printDefaultVccOperand(OpNo, STI, O);
740     break;
741   }
742 
743   if (Desc.TSFlags & SIInstrFlags::MTBUF) {
744     int SOffsetIdx =
745       AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::soffset);
746     assert(SOffsetIdx != -1);
747     if ((int)OpNo == SOffsetIdx)
748       printSymbolicFormat(MI, STI, O);
749   }
750 }
751 
752 void AMDGPUInstPrinter::printOperandAndFPInputMods(const MCInst *MI,
753                                                    unsigned OpNo,
754                                                    const MCSubtargetInfo &STI,
755                                                    raw_ostream &O) {
756   unsigned InputModifiers = MI->getOperand(OpNo).getImm();
757 
758   // Use 'neg(...)' instead of '-' to avoid ambiguity.
759   // This is important for integer literals because
760   // -1 is not the same value as neg(1).
761   bool NegMnemo = false;
762 
763   if (InputModifiers & SISrcMods::NEG) {
764     if (OpNo + 1 < MI->getNumOperands() &&
765         (InputModifiers & SISrcMods::ABS) == 0) {
766       const MCOperand &Op = MI->getOperand(OpNo + 1);
767       NegMnemo = Op.isImm() || Op.isDFPImm();
768     }
769     if (NegMnemo) {
770       O << "neg(";
771     } else {
772       O << '-';
773     }
774   }
775 
776   if (InputModifiers & SISrcMods::ABS)
777     O << '|';
778   printOperand(MI, OpNo + 1, STI, O);
779   if (InputModifiers & SISrcMods::ABS)
780     O << '|';
781 
782   if (NegMnemo) {
783     O << ')';
784   }
785 }
786 
787 void AMDGPUInstPrinter::printOperandAndIntInputMods(const MCInst *MI,
788                                                     unsigned OpNo,
789                                                     const MCSubtargetInfo &STI,
790                                                     raw_ostream &O) {
791   unsigned InputModifiers = MI->getOperand(OpNo).getImm();
792   if (InputModifiers & SISrcMods::SEXT)
793     O << "sext(";
794   printOperand(MI, OpNo + 1, STI, O);
795   if (InputModifiers & SISrcMods::SEXT)
796     O << ')';
797 
798   // Print default vcc/vcc_lo operand of VOP2b.
799   switch (MI->getOpcode()) {
800   default: break;
801 
802   case AMDGPU::V_CNDMASK_B32_sdwa_gfx10:
803   case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10:
804   case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10:
805   case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10:
806     if ((int)OpNo + 1 == AMDGPU::getNamedOperandIdx(MI->getOpcode(),
807                                                     AMDGPU::OpName::src1))
808       printDefaultVccOperand(OpNo, STI, O);
809     break;
810   }
811 }
812 
813 void AMDGPUInstPrinter::printDPP8(const MCInst *MI, unsigned OpNo,
814                                   const MCSubtargetInfo &STI,
815                                   raw_ostream &O) {
816   if (!AMDGPU::isGFX10Plus(STI))
817     llvm_unreachable("dpp8 is not supported on ASICs earlier than GFX10");
818 
819   unsigned Imm = MI->getOperand(OpNo).getImm();
820   O << "dpp8:[" << formatDec(Imm & 0x7);
821   for (size_t i = 1; i < 8; ++i) {
822     O << ',' << formatDec((Imm >> (3 * i)) & 0x7);
823   }
824   O << ']';
825 }
826 
827 void AMDGPUInstPrinter::printDPPCtrl(const MCInst *MI, unsigned OpNo,
828                                      const MCSubtargetInfo &STI,
829                                      raw_ostream &O) {
830   using namespace AMDGPU::DPP;
831 
832   unsigned Imm = MI->getOperand(OpNo).getImm();
833   const MCInstrDesc &Desc = MII.get(MI->getOpcode());
834   int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
835                                            AMDGPU::OpName::src0);
836 
837   if (Src0Idx >= 0 &&
838       Desc.OpInfo[Src0Idx].RegClass == AMDGPU::VReg_64RegClassID &&
839       !AMDGPU::isLegal64BitDPPControl(Imm)) {
840     O << " /* 64 bit dpp only supports row_newbcast */";
841     return;
842   } else if (Imm <= DppCtrl::QUAD_PERM_LAST) {
843     O << "quad_perm:[";
844     O << formatDec(Imm & 0x3)         << ',';
845     O << formatDec((Imm & 0xc)  >> 2) << ',';
846     O << formatDec((Imm & 0x30) >> 4) << ',';
847     O << formatDec((Imm & 0xc0) >> 6) << ']';
848   } else if ((Imm >= DppCtrl::ROW_SHL_FIRST) &&
849              (Imm <= DppCtrl::ROW_SHL_LAST)) {
850     O << "row_shl:";
851     printU4ImmDecOperand(MI, OpNo, O);
852   } else if ((Imm >= DppCtrl::ROW_SHR_FIRST) &&
853              (Imm <= DppCtrl::ROW_SHR_LAST)) {
854     O << "row_shr:";
855     printU4ImmDecOperand(MI, OpNo, O);
856   } else if ((Imm >= DppCtrl::ROW_ROR_FIRST) &&
857              (Imm <= DppCtrl::ROW_ROR_LAST)) {
858     O << "row_ror:";
859     printU4ImmDecOperand(MI, OpNo, O);
860   } else if (Imm == DppCtrl::WAVE_SHL1) {
861     if (AMDGPU::isGFX10Plus(STI)) {
862       O << "/* wave_shl is not supported starting from GFX10 */";
863       return;
864     }
865     O << "wave_shl:1";
866   } else if (Imm == DppCtrl::WAVE_ROL1) {
867     if (AMDGPU::isGFX10Plus(STI)) {
868       O << "/* wave_rol is not supported starting from GFX10 */";
869       return;
870     }
871     O << "wave_rol:1";
872   } else if (Imm == DppCtrl::WAVE_SHR1) {
873     if (AMDGPU::isGFX10Plus(STI)) {
874       O << "/* wave_shr is not supported starting from GFX10 */";
875       return;
876     }
877     O << "wave_shr:1";
878   } else if (Imm == DppCtrl::WAVE_ROR1) {
879     if (AMDGPU::isGFX10Plus(STI)) {
880       O << "/* wave_ror is not supported starting from GFX10 */";
881       return;
882     }
883     O << "wave_ror:1";
884   } else if (Imm == DppCtrl::ROW_MIRROR) {
885     O << "row_mirror";
886   } else if (Imm == DppCtrl::ROW_HALF_MIRROR) {
887     O << "row_half_mirror";
888   } else if (Imm == DppCtrl::BCAST15) {
889     if (AMDGPU::isGFX10Plus(STI)) {
890       O << "/* row_bcast is not supported starting from GFX10 */";
891       return;
892     }
893     O << "row_bcast:15";
894   } else if (Imm == DppCtrl::BCAST31) {
895     if (AMDGPU::isGFX10Plus(STI)) {
896       O << "/* row_bcast is not supported starting from GFX10 */";
897       return;
898     }
899     O << "row_bcast:31";
900   } else if ((Imm >= DppCtrl::ROW_SHARE_FIRST) &&
901              (Imm <= DppCtrl::ROW_SHARE_LAST)) {
902     if (AMDGPU::isGFX90A(STI)) {
903       O << "row_newbcast:";
904     } else if (AMDGPU::isGFX10Plus(STI)) {
905       O << "row_share:";
906     } else {
907       O << " /* row_newbcast/row_share is not supported on ASICs earlier "
908            "than GFX90A/GFX10 */";
909       return;
910     }
911     printU4ImmDecOperand(MI, OpNo, O);
912   } else if ((Imm >= DppCtrl::ROW_XMASK_FIRST) &&
913              (Imm <= DppCtrl::ROW_XMASK_LAST)) {
914     if (!AMDGPU::isGFX10Plus(STI)) {
915       O << "/* row_xmask is not supported on ASICs earlier than GFX10 */";
916       return;
917     }
918     O << "row_xmask:";
919     printU4ImmDecOperand(MI, OpNo, O);
920   } else {
921     O << "/* Invalid dpp_ctrl value */";
922   }
923 }
924 
925 void AMDGPUInstPrinter::printRowMask(const MCInst *MI, unsigned OpNo,
926                                      const MCSubtargetInfo &STI,
927                                      raw_ostream &O) {
928   O << " row_mask:";
929   printU4ImmOperand(MI, OpNo, STI, O);
930 }
931 
932 void AMDGPUInstPrinter::printBankMask(const MCInst *MI, unsigned OpNo,
933                                       const MCSubtargetInfo &STI,
934                                       raw_ostream &O) {
935   O << " bank_mask:";
936   printU4ImmOperand(MI, OpNo, STI, O);
937 }
938 
939 void AMDGPUInstPrinter::printBoundCtrl(const MCInst *MI, unsigned OpNo,
940                                        const MCSubtargetInfo &STI,
941                                        raw_ostream &O) {
942   unsigned Imm = MI->getOperand(OpNo).getImm();
943   if (Imm) {
944     O << " bound_ctrl:1";
945   }
946 }
947 
948 void AMDGPUInstPrinter::printFI(const MCInst *MI, unsigned OpNo,
949                                 const MCSubtargetInfo &STI,
950                                 raw_ostream &O) {
951   using namespace llvm::AMDGPU::DPP;
952   unsigned Imm = MI->getOperand(OpNo).getImm();
953   if (Imm == DPP_FI_1 || Imm == DPP8_FI_1) {
954     O << " fi:1";
955   }
956 }
957 
958 void AMDGPUInstPrinter::printSDWASel(const MCInst *MI, unsigned OpNo,
959                                      raw_ostream &O) {
960   using namespace llvm::AMDGPU::SDWA;
961 
962   unsigned Imm = MI->getOperand(OpNo).getImm();
963   switch (Imm) {
964   case SdwaSel::BYTE_0: O << "BYTE_0"; break;
965   case SdwaSel::BYTE_1: O << "BYTE_1"; break;
966   case SdwaSel::BYTE_2: O << "BYTE_2"; break;
967   case SdwaSel::BYTE_3: O << "BYTE_3"; break;
968   case SdwaSel::WORD_0: O << "WORD_0"; break;
969   case SdwaSel::WORD_1: O << "WORD_1"; break;
970   case SdwaSel::DWORD: O << "DWORD"; break;
971   default: llvm_unreachable("Invalid SDWA data select operand");
972   }
973 }
974 
975 void AMDGPUInstPrinter::printSDWADstSel(const MCInst *MI, unsigned OpNo,
976                                         const MCSubtargetInfo &STI,
977                                         raw_ostream &O) {
978   O << "dst_sel:";
979   printSDWASel(MI, OpNo, O);
980 }
981 
982 void AMDGPUInstPrinter::printSDWASrc0Sel(const MCInst *MI, unsigned OpNo,
983                                          const MCSubtargetInfo &STI,
984                                          raw_ostream &O) {
985   O << "src0_sel:";
986   printSDWASel(MI, OpNo, O);
987 }
988 
989 void AMDGPUInstPrinter::printSDWASrc1Sel(const MCInst *MI, unsigned OpNo,
990                                          const MCSubtargetInfo &STI,
991                                          raw_ostream &O) {
992   O << "src1_sel:";
993   printSDWASel(MI, OpNo, O);
994 }
995 
996 void AMDGPUInstPrinter::printSDWADstUnused(const MCInst *MI, unsigned OpNo,
997                                            const MCSubtargetInfo &STI,
998                                            raw_ostream &O) {
999   using namespace llvm::AMDGPU::SDWA;
1000 
1001   O << "dst_unused:";
1002   unsigned Imm = MI->getOperand(OpNo).getImm();
1003   switch (Imm) {
1004   case DstUnused::UNUSED_PAD: O << "UNUSED_PAD"; break;
1005   case DstUnused::UNUSED_SEXT: O << "UNUSED_SEXT"; break;
1006   case DstUnused::UNUSED_PRESERVE: O << "UNUSED_PRESERVE"; break;
1007   default: llvm_unreachable("Invalid SDWA dest_unused operand");
1008   }
1009 }
1010 
1011 void AMDGPUInstPrinter::printExpSrcN(const MCInst *MI, unsigned OpNo,
1012                                      const MCSubtargetInfo &STI, raw_ostream &O,
1013                                      unsigned N) {
1014   unsigned Opc = MI->getOpcode();
1015   int EnIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::en);
1016   unsigned En = MI->getOperand(EnIdx).getImm();
1017 
1018   int ComprIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::compr);
1019 
1020   // If compr is set, print as src0, src0, src1, src1
1021   if (MI->getOperand(ComprIdx).getImm())
1022     OpNo = OpNo - N + N / 2;
1023 
1024   if (En & (1 << N))
1025     printRegOperand(MI->getOperand(OpNo).getReg(), O, MRI);
1026   else
1027     O << "off";
1028 }
1029 
1030 void AMDGPUInstPrinter::printExpSrc0(const MCInst *MI, unsigned OpNo,
1031                                      const MCSubtargetInfo &STI,
1032                                      raw_ostream &O) {
1033   printExpSrcN(MI, OpNo, STI, O, 0);
1034 }
1035 
1036 void AMDGPUInstPrinter::printExpSrc1(const MCInst *MI, unsigned OpNo,
1037                                      const MCSubtargetInfo &STI,
1038                                      raw_ostream &O) {
1039   printExpSrcN(MI, OpNo, STI, O, 1);
1040 }
1041 
1042 void AMDGPUInstPrinter::printExpSrc2(const MCInst *MI, unsigned OpNo,
1043                                      const MCSubtargetInfo &STI,
1044                                      raw_ostream &O) {
1045   printExpSrcN(MI, OpNo, STI, O, 2);
1046 }
1047 
1048 void AMDGPUInstPrinter::printExpSrc3(const MCInst *MI, unsigned OpNo,
1049                                      const MCSubtargetInfo &STI,
1050                                      raw_ostream &O) {
1051   printExpSrcN(MI, OpNo, STI, O, 3);
1052 }
1053 
1054 void AMDGPUInstPrinter::printExpTgt(const MCInst *MI, unsigned OpNo,
1055                                     const MCSubtargetInfo &STI,
1056                                     raw_ostream &O) {
1057   using namespace llvm::AMDGPU::Exp;
1058 
1059   // This is really a 6 bit field.
1060   unsigned Id = MI->getOperand(OpNo).getImm() & ((1 << 6) - 1);
1061 
1062   int Index;
1063   StringRef TgtName;
1064   if (getTgtName(Id, TgtName, Index) && isSupportedTgtId(Id, STI)) {
1065     O << ' ' << TgtName;
1066     if (Index >= 0)
1067       O << Index;
1068   } else {
1069     O << " invalid_target_" << Id;
1070   }
1071 }
1072 
1073 static bool allOpsDefaultValue(const int* Ops, int NumOps, int Mod,
1074                                bool IsPacked, bool HasDstSel) {
1075   int DefaultValue = IsPacked && (Mod == SISrcMods::OP_SEL_1);
1076 
1077   for (int I = 0; I < NumOps; ++I) {
1078     if (!!(Ops[I] & Mod) != DefaultValue)
1079       return false;
1080   }
1081 
1082   if (HasDstSel && (Ops[0] & SISrcMods::DST_OP_SEL) != 0)
1083     return false;
1084 
1085   return true;
1086 }
1087 
1088 void AMDGPUInstPrinter::printPackedModifier(const MCInst *MI,
1089                                             StringRef Name,
1090                                             unsigned Mod,
1091                                             raw_ostream &O) {
1092   unsigned Opc = MI->getOpcode();
1093   int NumOps = 0;
1094   int Ops[3];
1095 
1096   for (int OpName : { AMDGPU::OpName::src0_modifiers,
1097                       AMDGPU::OpName::src1_modifiers,
1098                       AMDGPU::OpName::src2_modifiers }) {
1099     int Idx = AMDGPU::getNamedOperandIdx(Opc, OpName);
1100     if (Idx == -1)
1101       break;
1102 
1103     Ops[NumOps++] = MI->getOperand(Idx).getImm();
1104   }
1105 
1106   const bool HasDstSel =
1107     NumOps > 0 &&
1108     Mod == SISrcMods::OP_SEL_0 &&
1109     MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::VOP3_OPSEL;
1110 
1111   const bool IsPacked =
1112     MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::IsPacked;
1113 
1114   if (allOpsDefaultValue(Ops, NumOps, Mod, IsPacked, HasDstSel))
1115     return;
1116 
1117   O << Name;
1118   for (int I = 0; I < NumOps; ++I) {
1119     if (I != 0)
1120       O << ',';
1121 
1122     O << !!(Ops[I] & Mod);
1123   }
1124 
1125   if (HasDstSel) {
1126     O << ',' << !!(Ops[0] & SISrcMods::DST_OP_SEL);
1127   }
1128 
1129   O << ']';
1130 }
1131 
1132 void AMDGPUInstPrinter::printOpSel(const MCInst *MI, unsigned,
1133                                    const MCSubtargetInfo &STI,
1134                                    raw_ostream &O) {
1135   unsigned Opc = MI->getOpcode();
1136   if (Opc == AMDGPU::V_PERMLANE16_B32_gfx10 ||
1137       Opc == AMDGPU::V_PERMLANEX16_B32_gfx10) {
1138     auto FIN = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers);
1139     auto BCN = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers);
1140     unsigned FI = !!(MI->getOperand(FIN).getImm() & SISrcMods::OP_SEL_0);
1141     unsigned BC = !!(MI->getOperand(BCN).getImm() & SISrcMods::OP_SEL_0);
1142     if (FI || BC)
1143       O << " op_sel:[" << FI << ',' << BC << ']';
1144     return;
1145   }
1146 
1147   printPackedModifier(MI, " op_sel:[", SISrcMods::OP_SEL_0, O);
1148 }
1149 
1150 void AMDGPUInstPrinter::printOpSelHi(const MCInst *MI, unsigned OpNo,
1151                                      const MCSubtargetInfo &STI,
1152                                      raw_ostream &O) {
1153   printPackedModifier(MI, " op_sel_hi:[", SISrcMods::OP_SEL_1, O);
1154 }
1155 
1156 void AMDGPUInstPrinter::printNegLo(const MCInst *MI, unsigned OpNo,
1157                                    const MCSubtargetInfo &STI,
1158                                    raw_ostream &O) {
1159   printPackedModifier(MI, " neg_lo:[", SISrcMods::NEG, O);
1160 }
1161 
1162 void AMDGPUInstPrinter::printNegHi(const MCInst *MI, unsigned OpNo,
1163                                    const MCSubtargetInfo &STI,
1164                                    raw_ostream &O) {
1165   printPackedModifier(MI, " neg_hi:[", SISrcMods::NEG_HI, O);
1166 }
1167 
1168 void AMDGPUInstPrinter::printInterpSlot(const MCInst *MI, unsigned OpNum,
1169                                         const MCSubtargetInfo &STI,
1170                                         raw_ostream &O) {
1171   unsigned Imm = MI->getOperand(OpNum).getImm();
1172   switch (Imm) {
1173   case 0:
1174     O << "p10";
1175     break;
1176   case 1:
1177     O << "p20";
1178     break;
1179   case 2:
1180     O << "p0";
1181     break;
1182   default:
1183     O << "invalid_param_" << Imm;
1184   }
1185 }
1186 
1187 void AMDGPUInstPrinter::printInterpAttr(const MCInst *MI, unsigned OpNum,
1188                                         const MCSubtargetInfo &STI,
1189                                         raw_ostream &O) {
1190   unsigned Attr = MI->getOperand(OpNum).getImm();
1191   O << "attr" << Attr;
1192 }
1193 
1194 void AMDGPUInstPrinter::printInterpAttrChan(const MCInst *MI, unsigned OpNum,
1195                                         const MCSubtargetInfo &STI,
1196                                         raw_ostream &O) {
1197   unsigned Chan = MI->getOperand(OpNum).getImm();
1198   O << '.' << "xyzw"[Chan & 0x3];
1199 }
1200 
1201 void AMDGPUInstPrinter::printVGPRIndexMode(const MCInst *MI, unsigned OpNo,
1202                                            const MCSubtargetInfo &STI,
1203                                            raw_ostream &O) {
1204   using namespace llvm::AMDGPU::VGPRIndexMode;
1205   unsigned Val = MI->getOperand(OpNo).getImm();
1206 
1207   if ((Val & ~ENABLE_MASK) != 0) {
1208     O << formatHex(static_cast<uint64_t>(Val));
1209   } else {
1210     O << "gpr_idx(";
1211     bool NeedComma = false;
1212     for (unsigned ModeId = ID_MIN; ModeId <= ID_MAX; ++ModeId) {
1213       if (Val & (1 << ModeId)) {
1214         if (NeedComma)
1215           O << ',';
1216         O << IdSymbolic[ModeId];
1217         NeedComma = true;
1218       }
1219     }
1220     O << ')';
1221   }
1222 }
1223 
1224 void AMDGPUInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo,
1225                                         const MCSubtargetInfo &STI,
1226                                         raw_ostream &O) {
1227   printOperand(MI, OpNo, STI, O);
1228   O  << ", ";
1229   printOperand(MI, OpNo + 1, STI, O);
1230 }
1231 
1232 void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
1233                                    raw_ostream &O, StringRef Asm,
1234                                    StringRef Default) {
1235   const MCOperand &Op = MI->getOperand(OpNo);
1236   assert(Op.isImm());
1237   if (Op.getImm() == 1) {
1238     O << Asm;
1239   } else {
1240     O << Default;
1241   }
1242 }
1243 
1244 void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
1245                                    raw_ostream &O, char Asm) {
1246   const MCOperand &Op = MI->getOperand(OpNo);
1247   assert(Op.isImm());
1248   if (Op.getImm() == 1)
1249     O << Asm;
1250 }
1251 
1252 void AMDGPUInstPrinter::printHigh(const MCInst *MI, unsigned OpNo,
1253                                   const MCSubtargetInfo &STI,
1254                                   raw_ostream &O) {
1255   printNamedBit(MI, OpNo, O, "high");
1256 }
1257 
1258 void AMDGPUInstPrinter::printClampSI(const MCInst *MI, unsigned OpNo,
1259                                      const MCSubtargetInfo &STI,
1260                                      raw_ostream &O) {
1261   printNamedBit(MI, OpNo, O, "clamp");
1262 }
1263 
1264 void AMDGPUInstPrinter::printOModSI(const MCInst *MI, unsigned OpNo,
1265                                     const MCSubtargetInfo &STI,
1266                                     raw_ostream &O) {
1267   int Imm = MI->getOperand(OpNo).getImm();
1268   if (Imm == SIOutMods::MUL2)
1269     O << " mul:2";
1270   else if (Imm == SIOutMods::MUL4)
1271     O << " mul:4";
1272   else if (Imm == SIOutMods::DIV2)
1273     O << " div:2";
1274 }
1275 
1276 void AMDGPUInstPrinter::printSendMsg(const MCInst *MI, unsigned OpNo,
1277                                      const MCSubtargetInfo &STI,
1278                                      raw_ostream &O) {
1279   using namespace llvm::AMDGPU::SendMsg;
1280 
1281   const unsigned Imm16 = MI->getOperand(OpNo).getImm();
1282 
1283   uint16_t MsgId;
1284   uint16_t OpId;
1285   uint16_t StreamId;
1286   decodeMsg(Imm16, MsgId, OpId, StreamId);
1287 
1288   StringRef MsgName = getMsgName(MsgId, STI);
1289 
1290   if (!MsgName.empty() && isValidMsgOp(MsgId, OpId, STI) &&
1291       isValidMsgStream(MsgId, OpId, StreamId, STI)) {
1292     O << "sendmsg(" << MsgName;
1293     if (msgRequiresOp(MsgId)) {
1294       O << ", " << getMsgOpName(MsgId, OpId);
1295       if (msgSupportsStream(MsgId, OpId)) {
1296         O << ", " << StreamId;
1297       }
1298     }
1299     O << ')';
1300   } else if (encodeMsg(MsgId, OpId, StreamId) == Imm16) {
1301     O << "sendmsg(" << MsgId << ", " << OpId << ", " << StreamId << ')';
1302   } else {
1303     O << Imm16; // Unknown imm16 code.
1304   }
1305 }
1306 
1307 static void printSwizzleBitmask(const uint16_t AndMask,
1308                                 const uint16_t OrMask,
1309                                 const uint16_t XorMask,
1310                                 raw_ostream &O) {
1311   using namespace llvm::AMDGPU::Swizzle;
1312 
1313   uint16_t Probe0 = ((0            & AndMask) | OrMask) ^ XorMask;
1314   uint16_t Probe1 = ((BITMASK_MASK & AndMask) | OrMask) ^ XorMask;
1315 
1316   O << "\"";
1317 
1318   for (unsigned Mask = 1 << (BITMASK_WIDTH - 1); Mask > 0; Mask >>= 1) {
1319     uint16_t p0 = Probe0 & Mask;
1320     uint16_t p1 = Probe1 & Mask;
1321 
1322     if (p0 == p1) {
1323       if (p0 == 0) {
1324         O << "0";
1325       } else {
1326         O << "1";
1327       }
1328     } else {
1329       if (p0 == 0) {
1330         O << "p";
1331       } else {
1332         O << "i";
1333       }
1334     }
1335   }
1336 
1337   O << "\"";
1338 }
1339 
1340 void AMDGPUInstPrinter::printSwizzle(const MCInst *MI, unsigned OpNo,
1341                                      const MCSubtargetInfo &STI,
1342                                      raw_ostream &O) {
1343   using namespace llvm::AMDGPU::Swizzle;
1344 
1345   uint16_t Imm = MI->getOperand(OpNo).getImm();
1346   if (Imm == 0) {
1347     return;
1348   }
1349 
1350   O << " offset:";
1351 
1352   if ((Imm & QUAD_PERM_ENC_MASK) == QUAD_PERM_ENC) {
1353 
1354     O << "swizzle(" << IdSymbolic[ID_QUAD_PERM];
1355     for (unsigned I = 0; I < LANE_NUM; ++I) {
1356       O << ",";
1357       O << formatDec(Imm & LANE_MASK);
1358       Imm >>= LANE_SHIFT;
1359     }
1360     O << ")";
1361 
1362   } else if ((Imm & BITMASK_PERM_ENC_MASK) == BITMASK_PERM_ENC) {
1363 
1364     uint16_t AndMask = (Imm >> BITMASK_AND_SHIFT) & BITMASK_MASK;
1365     uint16_t OrMask  = (Imm >> BITMASK_OR_SHIFT)  & BITMASK_MASK;
1366     uint16_t XorMask = (Imm >> BITMASK_XOR_SHIFT) & BITMASK_MASK;
1367 
1368     if (AndMask == BITMASK_MAX &&
1369         OrMask == 0 &&
1370         countPopulation(XorMask) == 1) {
1371 
1372       O << "swizzle(" << IdSymbolic[ID_SWAP];
1373       O << ",";
1374       O << formatDec(XorMask);
1375       O << ")";
1376 
1377     } else if (AndMask == BITMASK_MAX &&
1378                OrMask == 0 && XorMask > 0 &&
1379                isPowerOf2_64(XorMask + 1)) {
1380 
1381       O << "swizzle(" << IdSymbolic[ID_REVERSE];
1382       O << ",";
1383       O << formatDec(XorMask + 1);
1384       O << ")";
1385 
1386     } else {
1387 
1388       uint16_t GroupSize = BITMASK_MAX - AndMask + 1;
1389       if (GroupSize > 1 &&
1390           isPowerOf2_64(GroupSize) &&
1391           OrMask < GroupSize &&
1392           XorMask == 0) {
1393 
1394         O << "swizzle(" << IdSymbolic[ID_BROADCAST];
1395         O << ",";
1396         O << formatDec(GroupSize);
1397         O << ",";
1398         O << formatDec(OrMask);
1399         O << ")";
1400 
1401       } else {
1402         O << "swizzle(" << IdSymbolic[ID_BITMASK_PERM];
1403         O << ",";
1404         printSwizzleBitmask(AndMask, OrMask, XorMask, O);
1405         O << ")";
1406       }
1407     }
1408   } else {
1409     printU16ImmDecOperand(MI, OpNo, O);
1410   }
1411 }
1412 
1413 void AMDGPUInstPrinter::printWaitFlag(const MCInst *MI, unsigned OpNo,
1414                                       const MCSubtargetInfo &STI,
1415                                       raw_ostream &O) {
1416   AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(STI.getCPU());
1417 
1418   unsigned SImm16 = MI->getOperand(OpNo).getImm();
1419   unsigned Vmcnt, Expcnt, Lgkmcnt;
1420   decodeWaitcnt(ISA, SImm16, Vmcnt, Expcnt, Lgkmcnt);
1421 
1422   bool IsDefaultVmcnt = Vmcnt == getVmcntBitMask(ISA);
1423   bool IsDefaultExpcnt = Expcnt == getExpcntBitMask(ISA);
1424   bool IsDefaultLgkmcnt = Lgkmcnt == getLgkmcntBitMask(ISA);
1425   bool PrintAll = IsDefaultVmcnt && IsDefaultExpcnt && IsDefaultLgkmcnt;
1426 
1427   bool NeedSpace = false;
1428 
1429   if (!IsDefaultVmcnt || PrintAll) {
1430     O << "vmcnt(" << Vmcnt << ')';
1431     NeedSpace = true;
1432   }
1433 
1434   if (!IsDefaultExpcnt || PrintAll) {
1435     if (NeedSpace)
1436       O << ' ';
1437     O << "expcnt(" << Expcnt << ')';
1438     NeedSpace = true;
1439   }
1440 
1441   if (!IsDefaultLgkmcnt || PrintAll) {
1442     if (NeedSpace)
1443       O << ' ';
1444     O << "lgkmcnt(" << Lgkmcnt << ')';
1445   }
1446 }
1447 
1448 void AMDGPUInstPrinter::printDepCtr(const MCInst *MI, unsigned OpNo,
1449                                     const MCSubtargetInfo &STI,
1450                                     raw_ostream &O) {
1451   using namespace llvm::AMDGPU::DepCtr;
1452 
1453   uint64_t Imm16 = MI->getOperand(OpNo).getImm() & 0xffff;
1454 
1455   bool HasNonDefaultVal = false;
1456   if (isSymbolicDepCtrEncoding(Imm16, HasNonDefaultVal, STI)) {
1457     int Id = 0;
1458     StringRef Name;
1459     unsigned Val;
1460     bool IsDefault;
1461     bool NeedSpace = false;
1462     while (decodeDepCtr(Imm16, Id, Name, Val, IsDefault, STI)) {
1463       if (!IsDefault || !HasNonDefaultVal) {
1464         if (NeedSpace)
1465           O << ' ';
1466         O << Name << '(' << Val << ')';
1467         NeedSpace = true;
1468       }
1469     }
1470   } else {
1471     O << formatHex(Imm16);
1472   }
1473 }
1474 
1475 void AMDGPUInstPrinter::printHwreg(const MCInst *MI, unsigned OpNo,
1476                                    const MCSubtargetInfo &STI, raw_ostream &O) {
1477   unsigned Id;
1478   unsigned Offset;
1479   unsigned Width;
1480 
1481   using namespace llvm::AMDGPU::Hwreg;
1482   unsigned Val = MI->getOperand(OpNo).getImm();
1483   decodeHwreg(Val, Id, Offset, Width);
1484   StringRef HwRegName = getHwreg(Id, STI);
1485 
1486   O << "hwreg(";
1487   if (!HwRegName.empty()) {
1488     O << HwRegName;
1489   } else {
1490     O << Id;
1491   }
1492   if (Width != WIDTH_DEFAULT_ || Offset != OFFSET_DEFAULT_) {
1493     O << ", " << Offset << ", " << Width;
1494   }
1495   O << ')';
1496 }
1497 
1498 void AMDGPUInstPrinter::printEndpgm(const MCInst *MI, unsigned OpNo,
1499                                     const MCSubtargetInfo &STI,
1500                                     raw_ostream &O) {
1501   uint16_t Imm = MI->getOperand(OpNo).getImm();
1502   if (Imm == 0) {
1503     return;
1504   }
1505 
1506   O << ' ' << formatDec(Imm);
1507 }
1508 
1509 #include "AMDGPUGenAsmWriter.inc"
1510