1 //===-- AMDGPUInstPrinter.cpp - AMDGPU MC Inst -> ASM ---------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 // \file
8 //===----------------------------------------------------------------------===//
9 
10 #include "AMDGPUInstPrinter.h"
11 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
12 #include "SIDefines.h"
13 #include "Utils/AMDGPUAsmUtils.h"
14 #include "Utils/AMDGPUBaseInfo.h"
15 #include "llvm/MC/MCExpr.h"
16 #include "llvm/MC/MCInst.h"
17 #include "llvm/MC/MCInstrDesc.h"
18 #include "llvm/MC/MCInstrInfo.h"
19 #include "llvm/MC/MCSubtargetInfo.h"
20 #include "llvm/Support/CommandLine.h"
21 #include "llvm/Support/TargetParser.h"
22 
23 using namespace llvm;
24 using namespace llvm::AMDGPU;
25 
26 static cl::opt<bool> Keep16BitSuffixes(
27   "amdgpu-keep-16-bit-reg-suffixes",
28   cl::desc("Keep .l and .h suffixes in asm for debugging purposes"),
29   cl::init(false),
30   cl::ReallyHidden);
31 
32 void AMDGPUInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
33   // FIXME: The current implementation of
34   // AsmParser::parseRegisterOrRegisterNumber in MC implies we either emit this
35   // as an integer or we provide a name which represents a physical register.
36   // For CFI instructions we really want to emit a name for the DWARF register
37   // instead, because there may be multiple DWARF registers corresponding to a
38   // single physical register. One case where this problem manifests is with
39   // wave32/wave64 where using the physical register name is ambiguous: if we
40   // write e.g. `.cfi_undefined v0` we lose information about the wavefront
41   // size which we need to encode the register in the final DWARF. Ideally we
42   // would extend MC to support parsing DWARF register names so we could do
43   // something like `.cfi_undefined dwarf_wave32_v0`. For now we just live with
44   // non-pretty DWARF register names in assembly text.
45   OS << RegNo;
46 }
47 
48 void AMDGPUInstPrinter::printInst(const MCInst *MI, uint64_t Address,
49                                   StringRef Annot, const MCSubtargetInfo &STI,
50                                   raw_ostream &OS) {
51   OS.flush();
52   printInstruction(MI, Address, STI, OS);
53   printAnnotation(OS, Annot);
54 }
55 
56 void AMDGPUInstPrinter::printU4ImmOperand(const MCInst *MI, unsigned OpNo,
57                                           const MCSubtargetInfo &STI,
58                                           raw_ostream &O) {
59   O << formatHex(MI->getOperand(OpNo).getImm() & 0xf);
60 }
61 
62 void AMDGPUInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo,
63                                           raw_ostream &O) {
64   O << formatHex(MI->getOperand(OpNo).getImm() & 0xff);
65 }
66 
67 void AMDGPUInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
68                                            const MCSubtargetInfo &STI,
69                                            raw_ostream &O) {
70   // It's possible to end up with a 32-bit literal used with a 16-bit operand
71   // with ignored high bits. Print as 32-bit anyway in that case.
72   int64_t Imm = MI->getOperand(OpNo).getImm();
73   if (isInt<16>(Imm) || isUInt<16>(Imm))
74     O << formatHex(static_cast<uint64_t>(Imm & 0xffff));
75   else
76     printU32ImmOperand(MI, OpNo, STI, O);
77 }
78 
79 void AMDGPUInstPrinter::printU4ImmDecOperand(const MCInst *MI, unsigned OpNo,
80                                              raw_ostream &O) {
81   O << formatDec(MI->getOperand(OpNo).getImm() & 0xf);
82 }
83 
84 void AMDGPUInstPrinter::printU8ImmDecOperand(const MCInst *MI, unsigned OpNo,
85                                              raw_ostream &O) {
86   O << formatDec(MI->getOperand(OpNo).getImm() & 0xff);
87 }
88 
89 void AMDGPUInstPrinter::printU16ImmDecOperand(const MCInst *MI, unsigned OpNo,
90                                               raw_ostream &O) {
91   O << formatDec(MI->getOperand(OpNo).getImm() & 0xffff);
92 }
93 
94 void AMDGPUInstPrinter::printU32ImmOperand(const MCInst *MI, unsigned OpNo,
95                                            const MCSubtargetInfo &STI,
96                                            raw_ostream &O) {
97   O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff);
98 }
99 
100 void AMDGPUInstPrinter::printNamedBit(const MCInst *MI, unsigned OpNo,
101                                       raw_ostream &O, StringRef BitName) {
102   if (MI->getOperand(OpNo).getImm()) {
103     O << ' ' << BitName;
104   }
105 }
106 
107 void AMDGPUInstPrinter::printOffen(const MCInst *MI, unsigned OpNo,
108                                    raw_ostream &O) {
109   printNamedBit(MI, OpNo, O, "offen");
110 }
111 
112 void AMDGPUInstPrinter::printIdxen(const MCInst *MI, unsigned OpNo,
113                                    raw_ostream &O) {
114   printNamedBit(MI, OpNo, O, "idxen");
115 }
116 
117 void AMDGPUInstPrinter::printAddr64(const MCInst *MI, unsigned OpNo,
118                                     raw_ostream &O) {
119   printNamedBit(MI, OpNo, O, "addr64");
120 }
121 
122 void AMDGPUInstPrinter::printMBUFOffset(const MCInst *MI, unsigned OpNo,
123                                         raw_ostream &O) {
124   if (MI->getOperand(OpNo).getImm()) {
125     O << " offset:";
126     printU16ImmDecOperand(MI, OpNo, O);
127   }
128 }
129 
130 void AMDGPUInstPrinter::printOffset(const MCInst *MI, unsigned OpNo,
131                                     const MCSubtargetInfo &STI,
132                                     raw_ostream &O) {
133   uint16_t Imm = MI->getOperand(OpNo).getImm();
134   if (Imm != 0) {
135     O << " offset:";
136     printU16ImmDecOperand(MI, OpNo, O);
137   }
138 }
139 
140 void AMDGPUInstPrinter::printFlatOffset(const MCInst *MI, unsigned OpNo,
141                                         const MCSubtargetInfo &STI,
142                                         raw_ostream &O) {
143   uint16_t Imm = MI->getOperand(OpNo).getImm();
144   if (Imm != 0) {
145     O << " offset:";
146 
147     const MCInstrDesc &Desc = MII.get(MI->getOpcode());
148     bool IsFlatSeg = !(Desc.TSFlags &
149         (SIInstrFlags::IsFlatGlobal | SIInstrFlags::IsFlatScratch));
150 
151     if (IsFlatSeg) { // Unsigned offset
152       printU16ImmDecOperand(MI, OpNo, O);
153     } else {         // Signed offset
154       if (AMDGPU::isGFX10Plus(STI)) {
155         O << formatDec(SignExtend32<12>(MI->getOperand(OpNo).getImm()));
156       } else {
157         O << formatDec(SignExtend32<13>(MI->getOperand(OpNo).getImm()));
158       }
159     }
160   }
161 }
162 
163 void AMDGPUInstPrinter::printOffset0(const MCInst *MI, unsigned OpNo,
164                                      const MCSubtargetInfo &STI,
165                                      raw_ostream &O) {
166   if (MI->getOperand(OpNo).getImm()) {
167     O << " offset0:";
168     printU8ImmDecOperand(MI, OpNo, O);
169   }
170 }
171 
172 void AMDGPUInstPrinter::printOffset1(const MCInst *MI, unsigned OpNo,
173                                      const MCSubtargetInfo &STI,
174                                      raw_ostream &O) {
175   if (MI->getOperand(OpNo).getImm()) {
176     O << " offset1:";
177     printU8ImmDecOperand(MI, OpNo, O);
178   }
179 }
180 
181 void AMDGPUInstPrinter::printSMRDOffset8(const MCInst *MI, unsigned OpNo,
182                                         const MCSubtargetInfo &STI,
183                                         raw_ostream &O) {
184   printU32ImmOperand(MI, OpNo, STI, O);
185 }
186 
187 void AMDGPUInstPrinter::printSMEMOffset(const MCInst *MI, unsigned OpNo,
188                                         const MCSubtargetInfo &STI,
189                                         raw_ostream &O) {
190   O << formatHex(MI->getOperand(OpNo).getImm());
191 }
192 
193 void AMDGPUInstPrinter::printSMRDLiteralOffset(const MCInst *MI, unsigned OpNo,
194                                                const MCSubtargetInfo &STI,
195                                                raw_ostream &O) {
196   printU32ImmOperand(MI, OpNo, STI, O);
197 }
198 
199 void AMDGPUInstPrinter::printGDS(const MCInst *MI, unsigned OpNo,
200                                  const MCSubtargetInfo &STI, raw_ostream &O) {
201   printNamedBit(MI, OpNo, O, "gds");
202 }
203 
204 void AMDGPUInstPrinter::printDLC(const MCInst *MI, unsigned OpNo,
205                                  const MCSubtargetInfo &STI, raw_ostream &O) {
206   if (AMDGPU::isGFX10Plus(STI))
207     printNamedBit(MI, OpNo, O, "dlc");
208 }
209 
210 void AMDGPUInstPrinter::printGLC(const MCInst *MI, unsigned OpNo,
211                                  const MCSubtargetInfo &STI, raw_ostream &O) {
212   printNamedBit(MI, OpNo, O, "glc");
213 }
214 
215 void AMDGPUInstPrinter::printSLC(const MCInst *MI, unsigned OpNo,
216                                  const MCSubtargetInfo &STI, raw_ostream &O) {
217   printNamedBit(MI, OpNo, O, "slc");
218 }
219 
220 void AMDGPUInstPrinter::printSWZ(const MCInst *MI, unsigned OpNo,
221                                  const MCSubtargetInfo &STI, raw_ostream &O) {
222 }
223 
224 void AMDGPUInstPrinter::printTFE(const MCInst *MI, unsigned OpNo,
225                                  const MCSubtargetInfo &STI, raw_ostream &O) {
226   printNamedBit(MI, OpNo, O, "tfe");
227 }
228 
229 void AMDGPUInstPrinter::printDMask(const MCInst *MI, unsigned OpNo,
230                                    const MCSubtargetInfo &STI, raw_ostream &O) {
231   if (MI->getOperand(OpNo).getImm()) {
232     O << " dmask:";
233     printU16ImmOperand(MI, OpNo, STI, O);
234   }
235 }
236 
237 void AMDGPUInstPrinter::printDim(const MCInst *MI, unsigned OpNo,
238                                  const MCSubtargetInfo &STI, raw_ostream &O) {
239   unsigned Dim = MI->getOperand(OpNo).getImm();
240   O << " dim:SQ_RSRC_IMG_";
241 
242   const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfoByEncoding(Dim);
243   if (DimInfo)
244     O << DimInfo->AsmSuffix;
245   else
246     O << Dim;
247 }
248 
249 void AMDGPUInstPrinter::printUNorm(const MCInst *MI, unsigned OpNo,
250                                    const MCSubtargetInfo &STI, raw_ostream &O) {
251   printNamedBit(MI, OpNo, O, "unorm");
252 }
253 
254 void AMDGPUInstPrinter::printDA(const MCInst *MI, unsigned OpNo,
255                                 const MCSubtargetInfo &STI, raw_ostream &O) {
256   printNamedBit(MI, OpNo, O, "da");
257 }
258 
259 void AMDGPUInstPrinter::printR128A16(const MCInst *MI, unsigned OpNo,
260                                   const MCSubtargetInfo &STI, raw_ostream &O) {
261   if (STI.hasFeature(AMDGPU::FeatureR128A16))
262     printNamedBit(MI, OpNo, O, "a16");
263   else
264     printNamedBit(MI, OpNo, O, "r128");
265 }
266 
267 void AMDGPUInstPrinter::printGFX10A16(const MCInst *MI, unsigned OpNo,
268                                   const MCSubtargetInfo &STI, raw_ostream &O) {
269   printNamedBit(MI, OpNo, O, "a16");
270 }
271 
272 void AMDGPUInstPrinter::printLWE(const MCInst *MI, unsigned OpNo,
273                                  const MCSubtargetInfo &STI, raw_ostream &O) {
274   printNamedBit(MI, OpNo, O, "lwe");
275 }
276 
277 void AMDGPUInstPrinter::printD16(const MCInst *MI, unsigned OpNo,
278                                  const MCSubtargetInfo &STI, raw_ostream &O) {
279   printNamedBit(MI, OpNo, O, "d16");
280 }
281 
282 void AMDGPUInstPrinter::printExpCompr(const MCInst *MI, unsigned OpNo,
283                                       const MCSubtargetInfo &STI,
284                                       raw_ostream &O) {
285   printNamedBit(MI, OpNo, O, "compr");
286 }
287 
288 void AMDGPUInstPrinter::printExpVM(const MCInst *MI, unsigned OpNo,
289                                    const MCSubtargetInfo &STI,
290                                    raw_ostream &O) {
291   printNamedBit(MI, OpNo, O, "vm");
292 }
293 
294 void AMDGPUInstPrinter::printFORMAT(const MCInst *MI, unsigned OpNo,
295                                     const MCSubtargetInfo &STI,
296                                     raw_ostream &O) {
297 }
298 
299 void AMDGPUInstPrinter::printSymbolicFormat(const MCInst *MI,
300                                             const MCSubtargetInfo &STI,
301                                             raw_ostream &O) {
302   using namespace llvm::AMDGPU::MTBUFFormat;
303 
304   int OpNo =
305     AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::format);
306   assert(OpNo != -1);
307 
308   unsigned Val = MI->getOperand(OpNo).getImm();
309   if (AMDGPU::isGFX10Plus(STI)) {
310     if (Val == UFMT_DEFAULT)
311       return;
312     if (isValidUnifiedFormat(Val)) {
313       O << " format:[" << getUnifiedFormatName(Val) << ']';
314     } else {
315       O << " format:" << Val;
316     }
317   } else {
318     if (Val == DFMT_NFMT_DEFAULT)
319       return;
320     if (isValidDfmtNfmt(Val, STI)) {
321       unsigned Dfmt;
322       unsigned Nfmt;
323       decodeDfmtNfmt(Val, Dfmt, Nfmt);
324       O << " format:[";
325       if (Dfmt != DFMT_DEFAULT) {
326         O << getDfmtName(Dfmt);
327         if (Nfmt != NFMT_DEFAULT) {
328           O << ',';
329         }
330       }
331       if (Nfmt != NFMT_DEFAULT) {
332         O << getNfmtName(Nfmt, STI);
333       }
334       O << ']';
335     } else {
336       O << " format:" << Val;
337     }
338   }
339 }
340 
341 void AMDGPUInstPrinter::printRegOperand(unsigned RegNo, raw_ostream &O,
342                                         const MCRegisterInfo &MRI) {
343 #if !defined(NDEBUG)
344   switch (RegNo) {
345   case AMDGPU::FP_REG:
346   case AMDGPU::SP_REG:
347   case AMDGPU::PRIVATE_RSRC_REG:
348     llvm_unreachable("pseudo-register should not ever be emitted");
349   case AMDGPU::SCC:
350     llvm_unreachable("pseudo scc should not ever be emitted");
351   default:
352     break;
353   }
354 #endif
355 
356   StringRef RegName(getRegisterName(RegNo));
357   if (!Keep16BitSuffixes)
358     if (!RegName.consume_back(".l"))
359       RegName.consume_back(".h");
360 
361   O << RegName;
362 }
363 
364 void AMDGPUInstPrinter::printVOPDst(const MCInst *MI, unsigned OpNo,
365                                     const MCSubtargetInfo &STI, raw_ostream &O) {
366   if (OpNo == 0) {
367     if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::VOP3)
368       O << "_e64 ";
369     else if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::DPP)
370       O << "_dpp ";
371     else if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::SDWA)
372       O << "_sdwa ";
373     else
374       O << "_e32 ";
375   }
376 
377   printOperand(MI, OpNo, STI, O);
378 
379   // Print default vcc/vcc_lo operand.
380   switch (MI->getOpcode()) {
381   default: break;
382 
383   case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10:
384   case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10:
385   case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10:
386   case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10:
387   case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10:
388   case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10:
389   case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10:
390   case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10:
391   case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10:
392   case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10:
393   case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10:
394   case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10:
395     printDefaultVccOperand(1, STI, O);
396     break;
397   }
398 }
399 
400 void AMDGPUInstPrinter::printVINTRPDst(const MCInst *MI, unsigned OpNo,
401                                        const MCSubtargetInfo &STI, raw_ostream &O) {
402   if (AMDGPU::isSI(STI) || AMDGPU::isCI(STI))
403     O << " ";
404   else
405     O << "_e32 ";
406 
407   printOperand(MI, OpNo, STI, O);
408 }
409 
410 void AMDGPUInstPrinter::printImmediateInt16(uint32_t Imm,
411                                             const MCSubtargetInfo &STI,
412                                             raw_ostream &O) {
413   int16_t SImm = static_cast<int16_t>(Imm);
414   if (isInlinableIntLiteral(SImm)) {
415     O << SImm;
416   } else {
417     uint64_t Imm16 = static_cast<uint16_t>(Imm);
418     O << formatHex(Imm16);
419   }
420 }
421 
422 void AMDGPUInstPrinter::printImmediate16(uint32_t Imm,
423                                          const MCSubtargetInfo &STI,
424                                          raw_ostream &O) {
425   int16_t SImm = static_cast<int16_t>(Imm);
426   if (isInlinableIntLiteral(SImm)) {
427     O << SImm;
428     return;
429   }
430 
431   if (Imm == 0x3C00)
432     O<< "1.0";
433   else if (Imm == 0xBC00)
434     O<< "-1.0";
435   else if (Imm == 0x3800)
436     O<< "0.5";
437   else if (Imm == 0xB800)
438     O<< "-0.5";
439   else if (Imm == 0x4000)
440     O<< "2.0";
441   else if (Imm == 0xC000)
442     O<< "-2.0";
443   else if (Imm == 0x4400)
444     O<< "4.0";
445   else if (Imm == 0xC400)
446     O<< "-4.0";
447   else if (Imm == 0x3118 &&
448            STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]) {
449     O << "0.15915494";
450   } else {
451     uint64_t Imm16 = static_cast<uint16_t>(Imm);
452     O << formatHex(Imm16);
453   }
454 }
455 
456 void AMDGPUInstPrinter::printImmediateV216(uint32_t Imm,
457                                            const MCSubtargetInfo &STI,
458                                            raw_ostream &O) {
459   uint16_t Lo16 = static_cast<uint16_t>(Imm);
460   printImmediate16(Lo16, STI, O);
461 }
462 
463 void AMDGPUInstPrinter::printImmediate32(uint32_t Imm,
464                                          const MCSubtargetInfo &STI,
465                                          raw_ostream &O) {
466   int32_t SImm = static_cast<int32_t>(Imm);
467   if (SImm >= -16 && SImm <= 64) {
468     O << SImm;
469     return;
470   }
471 
472   if (Imm == FloatToBits(0.0f))
473     O << "0.0";
474   else if (Imm == FloatToBits(1.0f))
475     O << "1.0";
476   else if (Imm == FloatToBits(-1.0f))
477     O << "-1.0";
478   else if (Imm == FloatToBits(0.5f))
479     O << "0.5";
480   else if (Imm == FloatToBits(-0.5f))
481     O << "-0.5";
482   else if (Imm == FloatToBits(2.0f))
483     O << "2.0";
484   else if (Imm == FloatToBits(-2.0f))
485     O << "-2.0";
486   else if (Imm == FloatToBits(4.0f))
487     O << "4.0";
488   else if (Imm == FloatToBits(-4.0f))
489     O << "-4.0";
490   else if (Imm == 0x3e22f983 &&
491            STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
492     O << "0.15915494";
493   else
494     O << formatHex(static_cast<uint64_t>(Imm));
495 }
496 
497 void AMDGPUInstPrinter::printImmediate64(uint64_t Imm,
498                                          const MCSubtargetInfo &STI,
499                                          raw_ostream &O) {
500   int64_t SImm = static_cast<int64_t>(Imm);
501   if (SImm >= -16 && SImm <= 64) {
502     O << SImm;
503     return;
504   }
505 
506   if (Imm == DoubleToBits(0.0))
507     O << "0.0";
508   else if (Imm == DoubleToBits(1.0))
509     O << "1.0";
510   else if (Imm == DoubleToBits(-1.0))
511     O << "-1.0";
512   else if (Imm == DoubleToBits(0.5))
513     O << "0.5";
514   else if (Imm == DoubleToBits(-0.5))
515     O << "-0.5";
516   else if (Imm == DoubleToBits(2.0))
517     O << "2.0";
518   else if (Imm == DoubleToBits(-2.0))
519     O << "-2.0";
520   else if (Imm == DoubleToBits(4.0))
521     O << "4.0";
522   else if (Imm == DoubleToBits(-4.0))
523     O << "-4.0";
524   else if (Imm == 0x3fc45f306dc9c882 &&
525            STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
526     O << "0.15915494309189532";
527   else {
528     assert(isUInt<32>(Imm) || Imm == 0x3fc45f306dc9c882);
529 
530     // In rare situations, we will have a 32-bit literal in a 64-bit
531     // operand. This is technically allowed for the encoding of s_mov_b64.
532     O << formatHex(static_cast<uint64_t>(Imm));
533   }
534 }
535 
536 void AMDGPUInstPrinter::printBLGP(const MCInst *MI, unsigned OpNo,
537                                   const MCSubtargetInfo &STI,
538                                   raw_ostream &O) {
539   unsigned Imm = MI->getOperand(OpNo).getImm();
540   if (!Imm)
541     return;
542 
543   O << " blgp:" << Imm;
544 }
545 
546 void AMDGPUInstPrinter::printCBSZ(const MCInst *MI, unsigned OpNo,
547                                   const MCSubtargetInfo &STI,
548                                   raw_ostream &O) {
549   unsigned Imm = MI->getOperand(OpNo).getImm();
550   if (!Imm)
551     return;
552 
553   O << " cbsz:" << Imm;
554 }
555 
556 void AMDGPUInstPrinter::printABID(const MCInst *MI, unsigned OpNo,
557                                   const MCSubtargetInfo &STI,
558                                   raw_ostream &O) {
559   unsigned Imm = MI->getOperand(OpNo).getImm();
560   if (!Imm)
561     return;
562 
563   O << " abid:" << Imm;
564 }
565 
566 void AMDGPUInstPrinter::printDefaultVccOperand(unsigned OpNo,
567                                                const MCSubtargetInfo &STI,
568                                                raw_ostream &O) {
569   if (OpNo > 0)
570     O << ", ";
571   printRegOperand(STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ?
572                   AMDGPU::VCC : AMDGPU::VCC_LO, O, MRI);
573   if (OpNo == 0)
574     O << ", ";
575 }
576 
577 void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
578                                      const MCSubtargetInfo &STI,
579                                      raw_ostream &O) {
580   // Print default vcc/vcc_lo operand of VOPC.
581   const MCInstrDesc &Desc = MII.get(MI->getOpcode());
582   if (OpNo == 0 && (Desc.TSFlags & SIInstrFlags::VOPC) &&
583       (Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC) ||
584        Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC_LO)))
585     printDefaultVccOperand(OpNo, STI, O);
586 
587   if (OpNo >= MI->getNumOperands()) {
588     O << "/*Missing OP" << OpNo << "*/";
589     return;
590   }
591 
592   const MCOperand &Op = MI->getOperand(OpNo);
593   if (Op.isReg()) {
594     printRegOperand(Op.getReg(), O, MRI);
595   } else if (Op.isImm()) {
596     const uint8_t OpTy = Desc.OpInfo[OpNo].OperandType;
597     switch (OpTy) {
598     case AMDGPU::OPERAND_REG_IMM_INT32:
599     case AMDGPU::OPERAND_REG_IMM_FP32:
600     case AMDGPU::OPERAND_REG_INLINE_C_INT32:
601     case AMDGPU::OPERAND_REG_INLINE_C_FP32:
602     case AMDGPU::OPERAND_REG_INLINE_AC_INT32:
603     case AMDGPU::OPERAND_REG_INLINE_AC_FP32:
604     case MCOI::OPERAND_IMMEDIATE:
605       printImmediate32(Op.getImm(), STI, O);
606       break;
607     case AMDGPU::OPERAND_REG_IMM_INT64:
608     case AMDGPU::OPERAND_REG_IMM_FP64:
609     case AMDGPU::OPERAND_REG_INLINE_C_INT64:
610     case AMDGPU::OPERAND_REG_INLINE_C_FP64:
611       printImmediate64(Op.getImm(), STI, O);
612       break;
613     case AMDGPU::OPERAND_REG_INLINE_C_INT16:
614     case AMDGPU::OPERAND_REG_INLINE_AC_INT16:
615     case AMDGPU::OPERAND_REG_IMM_INT16:
616       printImmediateInt16(Op.getImm(), STI, O);
617       break;
618     case AMDGPU::OPERAND_REG_INLINE_C_FP16:
619     case AMDGPU::OPERAND_REG_INLINE_AC_FP16:
620     case AMDGPU::OPERAND_REG_IMM_FP16:
621       printImmediate16(Op.getImm(), STI, O);
622       break;
623     case AMDGPU::OPERAND_REG_IMM_V2INT16:
624     case AMDGPU::OPERAND_REG_IMM_V2FP16:
625       if (!isUInt<16>(Op.getImm()) &&
626           STI.getFeatureBits()[AMDGPU::FeatureVOP3Literal]) {
627         printImmediate32(Op.getImm(), STI, O);
628         break;
629       }
630 
631       //  Deal with 16-bit FP inline immediates not working.
632       if (OpTy == AMDGPU::OPERAND_REG_IMM_V2FP16) {
633         printImmediate16(static_cast<uint16_t>(Op.getImm()), STI, O);
634         break;
635       }
636       LLVM_FALLTHROUGH;
637     case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
638     case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:
639       printImmediateInt16(static_cast<uint16_t>(Op.getImm()), STI, O);
640       break;
641     case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
642     case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16:
643       printImmediateV216(Op.getImm(), STI, O);
644       break;
645     case MCOI::OPERAND_UNKNOWN:
646     case MCOI::OPERAND_PCREL:
647       O << formatDec(Op.getImm());
648       break;
649     case MCOI::OPERAND_REGISTER:
650       // FIXME: This should be removed and handled somewhere else. Seems to come
651       // from a disassembler bug.
652       O << "/*invalid immediate*/";
653       break;
654     default:
655       // We hit this for the immediate instruction bits that don't yet have a
656       // custom printer.
657       llvm_unreachable("unexpected immediate operand type");
658     }
659   } else if (Op.isFPImm()) {
660     // We special case 0.0 because otherwise it will be printed as an integer.
661     if (Op.getFPImm() == 0.0)
662       O << "0.0";
663     else {
664       const MCInstrDesc &Desc = MII.get(MI->getOpcode());
665       int RCID = Desc.OpInfo[OpNo].RegClass;
666       unsigned RCBits = AMDGPU::getRegBitWidth(MRI.getRegClass(RCID));
667       if (RCBits == 32)
668         printImmediate32(FloatToBits(Op.getFPImm()), STI, O);
669       else if (RCBits == 64)
670         printImmediate64(DoubleToBits(Op.getFPImm()), STI, O);
671       else
672         llvm_unreachable("Invalid register class size");
673     }
674   } else if (Op.isExpr()) {
675     const MCExpr *Exp = Op.getExpr();
676     Exp->print(O, &MAI);
677   } else {
678     O << "/*INV_OP*/";
679   }
680 
681   // Print default vcc/vcc_lo operand of v_cndmask_b32_e32.
682   switch (MI->getOpcode()) {
683   default: break;
684 
685   case AMDGPU::V_CNDMASK_B32_e32_gfx10:
686   case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10:
687   case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10:
688   case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10:
689   case AMDGPU::V_CNDMASK_B32_dpp_gfx10:
690   case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10:
691   case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10:
692   case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10:
693   case AMDGPU::V_CNDMASK_B32_dpp8_gfx10:
694   case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10:
695   case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10:
696   case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10:
697 
698   case AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7:
699   case AMDGPU::V_CNDMASK_B32_e32_vi:
700     if ((int)OpNo == AMDGPU::getNamedOperandIdx(MI->getOpcode(),
701                                                 AMDGPU::OpName::src1))
702       printDefaultVccOperand(OpNo, STI, O);
703     break;
704   }
705 
706   if (Desc.TSFlags & SIInstrFlags::MTBUF) {
707     int SOffsetIdx =
708       AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::soffset);
709     assert(SOffsetIdx != -1);
710     if ((int)OpNo == SOffsetIdx)
711       printSymbolicFormat(MI, STI, O);
712   }
713 }
714 
715 void AMDGPUInstPrinter::printOperandAndFPInputMods(const MCInst *MI,
716                                                    unsigned OpNo,
717                                                    const MCSubtargetInfo &STI,
718                                                    raw_ostream &O) {
719   unsigned InputModifiers = MI->getOperand(OpNo).getImm();
720 
721   // Use 'neg(...)' instead of '-' to avoid ambiguity.
722   // This is important for integer literals because
723   // -1 is not the same value as neg(1).
724   bool NegMnemo = false;
725 
726   if (InputModifiers & SISrcMods::NEG) {
727     if (OpNo + 1 < MI->getNumOperands() &&
728         (InputModifiers & SISrcMods::ABS) == 0) {
729       const MCOperand &Op = MI->getOperand(OpNo + 1);
730       NegMnemo = Op.isImm() || Op.isFPImm();
731     }
732     if (NegMnemo) {
733       O << "neg(";
734     } else {
735       O << '-';
736     }
737   }
738 
739   if (InputModifiers & SISrcMods::ABS)
740     O << '|';
741   printOperand(MI, OpNo + 1, STI, O);
742   if (InputModifiers & SISrcMods::ABS)
743     O << '|';
744 
745   if (NegMnemo) {
746     O << ')';
747   }
748 }
749 
750 void AMDGPUInstPrinter::printOperandAndIntInputMods(const MCInst *MI,
751                                                     unsigned OpNo,
752                                                     const MCSubtargetInfo &STI,
753                                                     raw_ostream &O) {
754   unsigned InputModifiers = MI->getOperand(OpNo).getImm();
755   if (InputModifiers & SISrcMods::SEXT)
756     O << "sext(";
757   printOperand(MI, OpNo + 1, STI, O);
758   if (InputModifiers & SISrcMods::SEXT)
759     O << ')';
760 
761   // Print default vcc/vcc_lo operand of VOP2b.
762   switch (MI->getOpcode()) {
763   default: break;
764 
765   case AMDGPU::V_CNDMASK_B32_sdwa_gfx10:
766   case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10:
767   case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10:
768   case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10:
769     if ((int)OpNo + 1 == AMDGPU::getNamedOperandIdx(MI->getOpcode(),
770                                                     AMDGPU::OpName::src1))
771       printDefaultVccOperand(OpNo, STI, O);
772     break;
773   }
774 }
775 
776 void AMDGPUInstPrinter::printDPP8(const MCInst *MI, unsigned OpNo,
777                                   const MCSubtargetInfo &STI,
778                                   raw_ostream &O) {
779   if (!AMDGPU::isGFX10Plus(STI))
780     llvm_unreachable("dpp8 is not supported on ASICs earlier than GFX10");
781 
782   unsigned Imm = MI->getOperand(OpNo).getImm();
783   O << "dpp8:[" << formatDec(Imm & 0x7);
784   for (size_t i = 1; i < 8; ++i) {
785     O << ',' << formatDec((Imm >> (3 * i)) & 0x7);
786   }
787   O << ']';
788 }
789 
790 void AMDGPUInstPrinter::printDPPCtrl(const MCInst *MI, unsigned OpNo,
791                                      const MCSubtargetInfo &STI,
792                                      raw_ostream &O) {
793   using namespace AMDGPU::DPP;
794 
795   unsigned Imm = MI->getOperand(OpNo).getImm();
796   if (Imm <= DppCtrl::QUAD_PERM_LAST) {
797     O << "quad_perm:[";
798     O << formatDec(Imm & 0x3)         << ',';
799     O << formatDec((Imm & 0xc)  >> 2) << ',';
800     O << formatDec((Imm & 0x30) >> 4) << ',';
801     O << formatDec((Imm & 0xc0) >> 6) << ']';
802   } else if ((Imm >= DppCtrl::ROW_SHL_FIRST) &&
803              (Imm <= DppCtrl::ROW_SHL_LAST)) {
804     O << "row_shl:";
805     printU4ImmDecOperand(MI, OpNo, O);
806   } else if ((Imm >= DppCtrl::ROW_SHR_FIRST) &&
807              (Imm <= DppCtrl::ROW_SHR_LAST)) {
808     O << "row_shr:";
809     printU4ImmDecOperand(MI, OpNo, O);
810   } else if ((Imm >= DppCtrl::ROW_ROR_FIRST) &&
811              (Imm <= DppCtrl::ROW_ROR_LAST)) {
812     O << "row_ror:";
813     printU4ImmDecOperand(MI, OpNo, O);
814   } else if (Imm == DppCtrl::WAVE_SHL1) {
815     if (AMDGPU::isGFX10Plus(STI)) {
816       O << "/* wave_shl is not supported starting from GFX10 */";
817       return;
818     }
819     O << "wave_shl:1";
820   } else if (Imm == DppCtrl::WAVE_ROL1) {
821     if (AMDGPU::isGFX10Plus(STI)) {
822       O << "/* wave_rol is not supported starting from GFX10 */";
823       return;
824     }
825     O << "wave_rol:1";
826   } else if (Imm == DppCtrl::WAVE_SHR1) {
827     if (AMDGPU::isGFX10Plus(STI)) {
828       O << "/* wave_shr is not supported starting from GFX10 */";
829       return;
830     }
831     O << "wave_shr:1";
832   } else if (Imm == DppCtrl::WAVE_ROR1) {
833     if (AMDGPU::isGFX10Plus(STI)) {
834       O << "/* wave_ror is not supported starting from GFX10 */";
835       return;
836     }
837     O << "wave_ror:1";
838   } else if (Imm == DppCtrl::ROW_MIRROR) {
839     O << "row_mirror";
840   } else if (Imm == DppCtrl::ROW_HALF_MIRROR) {
841     O << "row_half_mirror";
842   } else if (Imm == DppCtrl::BCAST15) {
843     if (AMDGPU::isGFX10Plus(STI)) {
844       O << "/* row_bcast is not supported starting from GFX10 */";
845       return;
846     }
847     O << "row_bcast:15";
848   } else if (Imm == DppCtrl::BCAST31) {
849     if (AMDGPU::isGFX10Plus(STI)) {
850       O << "/* row_bcast is not supported starting from GFX10 */";
851       return;
852     }
853     O << "row_bcast:31";
854   } else if ((Imm >= DppCtrl::ROW_SHARE_FIRST) &&
855              (Imm <= DppCtrl::ROW_SHARE_LAST)) {
856     if (!AMDGPU::isGFX10Plus(STI)) {
857       O << "/* row_share is not supported on ASICs earlier than GFX10 */";
858       return;
859     }
860     O << "row_share:";
861     printU4ImmDecOperand(MI, OpNo, O);
862   } else if ((Imm >= DppCtrl::ROW_XMASK_FIRST) &&
863              (Imm <= DppCtrl::ROW_XMASK_LAST)) {
864     if (!AMDGPU::isGFX10Plus(STI)) {
865       O << "/* row_xmask is not supported on ASICs earlier than GFX10 */";
866       return;
867     }
868     O << "row_xmask:";
869     printU4ImmDecOperand(MI, OpNo, O);
870   } else {
871     O << "/* Invalid dpp_ctrl value */";
872   }
873 }
874 
875 void AMDGPUInstPrinter::printRowMask(const MCInst *MI, unsigned OpNo,
876                                      const MCSubtargetInfo &STI,
877                                      raw_ostream &O) {
878   O << " row_mask:";
879   printU4ImmOperand(MI, OpNo, STI, O);
880 }
881 
882 void AMDGPUInstPrinter::printBankMask(const MCInst *MI, unsigned OpNo,
883                                       const MCSubtargetInfo &STI,
884                                       raw_ostream &O) {
885   O << " bank_mask:";
886   printU4ImmOperand(MI, OpNo, STI, O);
887 }
888 
889 void AMDGPUInstPrinter::printBoundCtrl(const MCInst *MI, unsigned OpNo,
890                                        const MCSubtargetInfo &STI,
891                                        raw_ostream &O) {
892   unsigned Imm = MI->getOperand(OpNo).getImm();
893   if (Imm) {
894     O << " bound_ctrl:0"; // XXX - this syntax is used in sp3
895   }
896 }
897 
898 void AMDGPUInstPrinter::printFI(const MCInst *MI, unsigned OpNo,
899                                 const MCSubtargetInfo &STI,
900                                 raw_ostream &O) {
901   using namespace llvm::AMDGPU::DPP;
902   unsigned Imm = MI->getOperand(OpNo).getImm();
903   if (Imm == DPP_FI_1 || Imm == DPP8_FI_1) {
904     O << " fi:1";
905   }
906 }
907 
908 void AMDGPUInstPrinter::printSDWASel(const MCInst *MI, unsigned OpNo,
909                                      raw_ostream &O) {
910   using namespace llvm::AMDGPU::SDWA;
911 
912   unsigned Imm = MI->getOperand(OpNo).getImm();
913   switch (Imm) {
914   case SdwaSel::BYTE_0: O << "BYTE_0"; break;
915   case SdwaSel::BYTE_1: O << "BYTE_1"; break;
916   case SdwaSel::BYTE_2: O << "BYTE_2"; break;
917   case SdwaSel::BYTE_3: O << "BYTE_3"; break;
918   case SdwaSel::WORD_0: O << "WORD_0"; break;
919   case SdwaSel::WORD_1: O << "WORD_1"; break;
920   case SdwaSel::DWORD: O << "DWORD"; break;
921   default: llvm_unreachable("Invalid SDWA data select operand");
922   }
923 }
924 
925 void AMDGPUInstPrinter::printSDWADstSel(const MCInst *MI, unsigned OpNo,
926                                         const MCSubtargetInfo &STI,
927                                         raw_ostream &O) {
928   O << "dst_sel:";
929   printSDWASel(MI, OpNo, O);
930 }
931 
932 void AMDGPUInstPrinter::printSDWASrc0Sel(const MCInst *MI, unsigned OpNo,
933                                          const MCSubtargetInfo &STI,
934                                          raw_ostream &O) {
935   O << "src0_sel:";
936   printSDWASel(MI, OpNo, O);
937 }
938 
939 void AMDGPUInstPrinter::printSDWASrc1Sel(const MCInst *MI, unsigned OpNo,
940                                          const MCSubtargetInfo &STI,
941                                          raw_ostream &O) {
942   O << "src1_sel:";
943   printSDWASel(MI, OpNo, O);
944 }
945 
946 void AMDGPUInstPrinter::printSDWADstUnused(const MCInst *MI, unsigned OpNo,
947                                            const MCSubtargetInfo &STI,
948                                            raw_ostream &O) {
949   using namespace llvm::AMDGPU::SDWA;
950 
951   O << "dst_unused:";
952   unsigned Imm = MI->getOperand(OpNo).getImm();
953   switch (Imm) {
954   case DstUnused::UNUSED_PAD: O << "UNUSED_PAD"; break;
955   case DstUnused::UNUSED_SEXT: O << "UNUSED_SEXT"; break;
956   case DstUnused::UNUSED_PRESERVE: O << "UNUSED_PRESERVE"; break;
957   default: llvm_unreachable("Invalid SDWA dest_unused operand");
958   }
959 }
960 
961 template <unsigned N>
962 void AMDGPUInstPrinter::printExpSrcN(const MCInst *MI, unsigned OpNo,
963                                      const MCSubtargetInfo &STI,
964                                      raw_ostream &O) {
965   unsigned Opc = MI->getOpcode();
966   int EnIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::en);
967   unsigned En = MI->getOperand(EnIdx).getImm();
968 
969   int ComprIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::compr);
970 
971   // If compr is set, print as src0, src0, src1, src1
972   if (MI->getOperand(ComprIdx).getImm()) {
973     if (N == 1 || N == 2)
974       --OpNo;
975     else if (N == 3)
976       OpNo -= 2;
977   }
978 
979   if (En & (1 << N))
980     printRegOperand(MI->getOperand(OpNo).getReg(), O, MRI);
981   else
982     O << "off";
983 }
984 
985 void AMDGPUInstPrinter::printExpSrc0(const MCInst *MI, unsigned OpNo,
986                                      const MCSubtargetInfo &STI,
987                                      raw_ostream &O) {
988   printExpSrcN<0>(MI, OpNo, STI, O);
989 }
990 
991 void AMDGPUInstPrinter::printExpSrc1(const MCInst *MI, unsigned OpNo,
992                                      const MCSubtargetInfo &STI,
993                                      raw_ostream &O) {
994   printExpSrcN<1>(MI, OpNo, STI, O);
995 }
996 
997 void AMDGPUInstPrinter::printExpSrc2(const MCInst *MI, unsigned OpNo,
998                                      const MCSubtargetInfo &STI,
999                                      raw_ostream &O) {
1000   printExpSrcN<2>(MI, OpNo, STI, O);
1001 }
1002 
1003 void AMDGPUInstPrinter::printExpSrc3(const MCInst *MI, unsigned OpNo,
1004                                      const MCSubtargetInfo &STI,
1005                                      raw_ostream &O) {
1006   printExpSrcN<3>(MI, OpNo, STI, O);
1007 }
1008 
1009 void AMDGPUInstPrinter::printExpTgt(const MCInst *MI, unsigned OpNo,
1010                                     const MCSubtargetInfo &STI,
1011                                     raw_ostream &O) {
1012   // This is really a 6 bit field.
1013   uint32_t Tgt = MI->getOperand(OpNo).getImm() & ((1 << 6) - 1);
1014 
1015   if (Tgt <= Exp::ET_MRT7)
1016     O << " mrt" << Tgt - Exp::ET_MRT0;
1017   else if (Tgt == Exp::ET_MRTZ)
1018     O << " mrtz";
1019   else if (Tgt == Exp::ET_NULL)
1020     O << " null";
1021   else if (Tgt >= Exp::ET_POS0 &&
1022            Tgt <= uint32_t(isGFX10Plus(STI) ? Exp::ET_POS4 : Exp::ET_POS3))
1023     O << " pos" << Tgt - Exp::ET_POS0;
1024   else if (isGFX10Plus(STI) && Tgt == Exp::ET_PRIM)
1025     O << " prim";
1026   else if (Tgt >= Exp::ET_PARAM0 && Tgt <= Exp::ET_PARAM31)
1027     O << " param" << Tgt - Exp::ET_PARAM0;
1028   else {
1029     // Reserved values 10, 11
1030     O << " invalid_target_" << Tgt;
1031   }
1032 }
1033 
1034 static bool allOpsDefaultValue(const int* Ops, int NumOps, int Mod,
1035                                bool IsPacked, bool HasDstSel) {
1036   int DefaultValue = IsPacked && (Mod == SISrcMods::OP_SEL_1);
1037 
1038   for (int I = 0; I < NumOps; ++I) {
1039     if (!!(Ops[I] & Mod) != DefaultValue)
1040       return false;
1041   }
1042 
1043   if (HasDstSel && (Ops[0] & SISrcMods::DST_OP_SEL) != 0)
1044     return false;
1045 
1046   return true;
1047 }
1048 
1049 void AMDGPUInstPrinter::printPackedModifier(const MCInst *MI,
1050                                             StringRef Name,
1051                                             unsigned Mod,
1052                                             raw_ostream &O) {
1053   unsigned Opc = MI->getOpcode();
1054   int NumOps = 0;
1055   int Ops[3];
1056 
1057   for (int OpName : { AMDGPU::OpName::src0_modifiers,
1058                       AMDGPU::OpName::src1_modifiers,
1059                       AMDGPU::OpName::src2_modifiers }) {
1060     int Idx = AMDGPU::getNamedOperandIdx(Opc, OpName);
1061     if (Idx == -1)
1062       break;
1063 
1064     Ops[NumOps++] = MI->getOperand(Idx).getImm();
1065   }
1066 
1067   const bool HasDstSel =
1068     NumOps > 0 &&
1069     Mod == SISrcMods::OP_SEL_0 &&
1070     MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::VOP3_OPSEL;
1071 
1072   const bool IsPacked =
1073     MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::IsPacked;
1074 
1075   if (allOpsDefaultValue(Ops, NumOps, Mod, IsPacked, HasDstSel))
1076     return;
1077 
1078   O << Name;
1079   for (int I = 0; I < NumOps; ++I) {
1080     if (I != 0)
1081       O << ',';
1082 
1083     O << !!(Ops[I] & Mod);
1084   }
1085 
1086   if (HasDstSel) {
1087     O << ',' << !!(Ops[0] & SISrcMods::DST_OP_SEL);
1088   }
1089 
1090   O << ']';
1091 }
1092 
1093 void AMDGPUInstPrinter::printOpSel(const MCInst *MI, unsigned,
1094                                    const MCSubtargetInfo &STI,
1095                                    raw_ostream &O) {
1096   unsigned Opc = MI->getOpcode();
1097   if (Opc == AMDGPU::V_PERMLANE16_B32_gfx10 ||
1098       Opc == AMDGPU::V_PERMLANEX16_B32_gfx10) {
1099     auto FIN = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers);
1100     auto BCN = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers);
1101     unsigned FI = !!(MI->getOperand(FIN).getImm() & SISrcMods::OP_SEL_0);
1102     unsigned BC = !!(MI->getOperand(BCN).getImm() & SISrcMods::OP_SEL_0);
1103     if (FI || BC)
1104       O << " op_sel:[" << FI << ',' << BC << ']';
1105     return;
1106   }
1107 
1108   printPackedModifier(MI, " op_sel:[", SISrcMods::OP_SEL_0, O);
1109 }
1110 
1111 void AMDGPUInstPrinter::printOpSelHi(const MCInst *MI, unsigned OpNo,
1112                                      const MCSubtargetInfo &STI,
1113                                      raw_ostream &O) {
1114   printPackedModifier(MI, " op_sel_hi:[", SISrcMods::OP_SEL_1, O);
1115 }
1116 
1117 void AMDGPUInstPrinter::printNegLo(const MCInst *MI, unsigned OpNo,
1118                                    const MCSubtargetInfo &STI,
1119                                    raw_ostream &O) {
1120   printPackedModifier(MI, " neg_lo:[", SISrcMods::NEG, O);
1121 }
1122 
1123 void AMDGPUInstPrinter::printNegHi(const MCInst *MI, unsigned OpNo,
1124                                    const MCSubtargetInfo &STI,
1125                                    raw_ostream &O) {
1126   printPackedModifier(MI, " neg_hi:[", SISrcMods::NEG_HI, O);
1127 }
1128 
1129 void AMDGPUInstPrinter::printInterpSlot(const MCInst *MI, unsigned OpNum,
1130                                         const MCSubtargetInfo &STI,
1131                                         raw_ostream &O) {
1132   unsigned Imm = MI->getOperand(OpNum).getImm();
1133   switch (Imm) {
1134   case 0:
1135     O << "p10";
1136     break;
1137   case 1:
1138     O << "p20";
1139     break;
1140   case 2:
1141     O << "p0";
1142     break;
1143   default:
1144     O << "invalid_param_" << Imm;
1145   }
1146 }
1147 
1148 void AMDGPUInstPrinter::printInterpAttr(const MCInst *MI, unsigned OpNum,
1149                                         const MCSubtargetInfo &STI,
1150                                         raw_ostream &O) {
1151   unsigned Attr = MI->getOperand(OpNum).getImm();
1152   O << "attr" << Attr;
1153 }
1154 
1155 void AMDGPUInstPrinter::printInterpAttrChan(const MCInst *MI, unsigned OpNum,
1156                                         const MCSubtargetInfo &STI,
1157                                         raw_ostream &O) {
1158   unsigned Chan = MI->getOperand(OpNum).getImm();
1159   O << '.' << "xyzw"[Chan & 0x3];
1160 }
1161 
1162 void AMDGPUInstPrinter::printVGPRIndexMode(const MCInst *MI, unsigned OpNo,
1163                                            const MCSubtargetInfo &STI,
1164                                            raw_ostream &O) {
1165   using namespace llvm::AMDGPU::VGPRIndexMode;
1166   unsigned Val = MI->getOperand(OpNo).getImm();
1167 
1168   if ((Val & ~ENABLE_MASK) != 0) {
1169     O << formatHex(static_cast<uint64_t>(Val));
1170   } else {
1171     O << "gpr_idx(";
1172     bool NeedComma = false;
1173     for (unsigned ModeId = ID_MIN; ModeId <= ID_MAX; ++ModeId) {
1174       if (Val & (1 << ModeId)) {
1175         if (NeedComma)
1176           O << ',';
1177         O << IdSymbolic[ModeId];
1178         NeedComma = true;
1179       }
1180     }
1181     O << ')';
1182   }
1183 }
1184 
1185 void AMDGPUInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo,
1186                                         const MCSubtargetInfo &STI,
1187                                         raw_ostream &O) {
1188   printOperand(MI, OpNo, STI, O);
1189   O  << ", ";
1190   printOperand(MI, OpNo + 1, STI, O);
1191 }
1192 
1193 void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
1194                                    raw_ostream &O, StringRef Asm,
1195                                    StringRef Default) {
1196   const MCOperand &Op = MI->getOperand(OpNo);
1197   assert(Op.isImm());
1198   if (Op.getImm() == 1) {
1199     O << Asm;
1200   } else {
1201     O << Default;
1202   }
1203 }
1204 
1205 void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
1206                                    raw_ostream &O, char Asm) {
1207   const MCOperand &Op = MI->getOperand(OpNo);
1208   assert(Op.isImm());
1209   if (Op.getImm() == 1)
1210     O << Asm;
1211 }
1212 
1213 void AMDGPUInstPrinter::printHigh(const MCInst *MI, unsigned OpNo,
1214                                   const MCSubtargetInfo &STI,
1215                                   raw_ostream &O) {
1216   printNamedBit(MI, OpNo, O, "high");
1217 }
1218 
1219 void AMDGPUInstPrinter::printClampSI(const MCInst *MI, unsigned OpNo,
1220                                      const MCSubtargetInfo &STI,
1221                                      raw_ostream &O) {
1222   printNamedBit(MI, OpNo, O, "clamp");
1223 }
1224 
1225 void AMDGPUInstPrinter::printOModSI(const MCInst *MI, unsigned OpNo,
1226                                     const MCSubtargetInfo &STI,
1227                                     raw_ostream &O) {
1228   int Imm = MI->getOperand(OpNo).getImm();
1229   if (Imm == SIOutMods::MUL2)
1230     O << " mul:2";
1231   else if (Imm == SIOutMods::MUL4)
1232     O << " mul:4";
1233   else if (Imm == SIOutMods::DIV2)
1234     O << " div:2";
1235 }
1236 
1237 void AMDGPUInstPrinter::printSendMsg(const MCInst *MI, unsigned OpNo,
1238                                      const MCSubtargetInfo &STI,
1239                                      raw_ostream &O) {
1240   using namespace llvm::AMDGPU::SendMsg;
1241 
1242   const unsigned Imm16 = MI->getOperand(OpNo).getImm();
1243 
1244   uint16_t MsgId;
1245   uint16_t OpId;
1246   uint16_t StreamId;
1247   decodeMsg(Imm16, MsgId, OpId, StreamId);
1248 
1249   if (isValidMsgId(MsgId, STI) &&
1250       isValidMsgOp(MsgId, OpId) &&
1251       isValidMsgStream(MsgId, OpId, StreamId)) {
1252     O << "sendmsg(" << getMsgName(MsgId);
1253     if (msgRequiresOp(MsgId)) {
1254       O << ", " << getMsgOpName(MsgId, OpId);
1255       if (msgSupportsStream(MsgId, OpId)) {
1256         O << ", " << StreamId;
1257       }
1258     }
1259     O << ')';
1260   } else if (encodeMsg(MsgId, OpId, StreamId) == Imm16) {
1261     O << "sendmsg(" << MsgId << ", " << OpId << ", " << StreamId << ')';
1262   } else {
1263     O << Imm16; // Unknown imm16 code.
1264   }
1265 }
1266 
1267 static void printSwizzleBitmask(const uint16_t AndMask,
1268                                 const uint16_t OrMask,
1269                                 const uint16_t XorMask,
1270                                 raw_ostream &O) {
1271   using namespace llvm::AMDGPU::Swizzle;
1272 
1273   uint16_t Probe0 = ((0            & AndMask) | OrMask) ^ XorMask;
1274   uint16_t Probe1 = ((BITMASK_MASK & AndMask) | OrMask) ^ XorMask;
1275 
1276   O << "\"";
1277 
1278   for (unsigned Mask = 1 << (BITMASK_WIDTH - 1); Mask > 0; Mask >>= 1) {
1279     uint16_t p0 = Probe0 & Mask;
1280     uint16_t p1 = Probe1 & Mask;
1281 
1282     if (p0 == p1) {
1283       if (p0 == 0) {
1284         O << "0";
1285       } else {
1286         O << "1";
1287       }
1288     } else {
1289       if (p0 == 0) {
1290         O << "p";
1291       } else {
1292         O << "i";
1293       }
1294     }
1295   }
1296 
1297   O << "\"";
1298 }
1299 
1300 void AMDGPUInstPrinter::printSwizzle(const MCInst *MI, unsigned OpNo,
1301                                      const MCSubtargetInfo &STI,
1302                                      raw_ostream &O) {
1303   using namespace llvm::AMDGPU::Swizzle;
1304 
1305   uint16_t Imm = MI->getOperand(OpNo).getImm();
1306   if (Imm == 0) {
1307     return;
1308   }
1309 
1310   O << " offset:";
1311 
1312   if ((Imm & QUAD_PERM_ENC_MASK) == QUAD_PERM_ENC) {
1313 
1314     O << "swizzle(" << IdSymbolic[ID_QUAD_PERM];
1315     for (unsigned I = 0; I < LANE_NUM; ++I) {
1316       O << ",";
1317       O << formatDec(Imm & LANE_MASK);
1318       Imm >>= LANE_SHIFT;
1319     }
1320     O << ")";
1321 
1322   } else if ((Imm & BITMASK_PERM_ENC_MASK) == BITMASK_PERM_ENC) {
1323 
1324     uint16_t AndMask = (Imm >> BITMASK_AND_SHIFT) & BITMASK_MASK;
1325     uint16_t OrMask  = (Imm >> BITMASK_OR_SHIFT)  & BITMASK_MASK;
1326     uint16_t XorMask = (Imm >> BITMASK_XOR_SHIFT) & BITMASK_MASK;
1327 
1328     if (AndMask == BITMASK_MAX &&
1329         OrMask == 0 &&
1330         countPopulation(XorMask) == 1) {
1331 
1332       O << "swizzle(" << IdSymbolic[ID_SWAP];
1333       O << ",";
1334       O << formatDec(XorMask);
1335       O << ")";
1336 
1337     } else if (AndMask == BITMASK_MAX &&
1338                OrMask == 0 && XorMask > 0 &&
1339                isPowerOf2_64(XorMask + 1)) {
1340 
1341       O << "swizzle(" << IdSymbolic[ID_REVERSE];
1342       O << ",";
1343       O << formatDec(XorMask + 1);
1344       O << ")";
1345 
1346     } else {
1347 
1348       uint16_t GroupSize = BITMASK_MAX - AndMask + 1;
1349       if (GroupSize > 1 &&
1350           isPowerOf2_64(GroupSize) &&
1351           OrMask < GroupSize &&
1352           XorMask == 0) {
1353 
1354         O << "swizzle(" << IdSymbolic[ID_BROADCAST];
1355         O << ",";
1356         O << formatDec(GroupSize);
1357         O << ",";
1358         O << formatDec(OrMask);
1359         O << ")";
1360 
1361       } else {
1362         O << "swizzle(" << IdSymbolic[ID_BITMASK_PERM];
1363         O << ",";
1364         printSwizzleBitmask(AndMask, OrMask, XorMask, O);
1365         O << ")";
1366       }
1367     }
1368   } else {
1369     printU16ImmDecOperand(MI, OpNo, O);
1370   }
1371 }
1372 
1373 void AMDGPUInstPrinter::printWaitFlag(const MCInst *MI, unsigned OpNo,
1374                                       const MCSubtargetInfo &STI,
1375                                       raw_ostream &O) {
1376   AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(STI.getCPU());
1377 
1378   unsigned SImm16 = MI->getOperand(OpNo).getImm();
1379   unsigned Vmcnt, Expcnt, Lgkmcnt;
1380   decodeWaitcnt(ISA, SImm16, Vmcnt, Expcnt, Lgkmcnt);
1381 
1382   bool NeedSpace = false;
1383 
1384   if (Vmcnt != getVmcntBitMask(ISA)) {
1385     O << "vmcnt(" << Vmcnt << ')';
1386     NeedSpace = true;
1387   }
1388 
1389   if (Expcnt != getExpcntBitMask(ISA)) {
1390     if (NeedSpace)
1391       O << ' ';
1392     O << "expcnt(" << Expcnt << ')';
1393     NeedSpace = true;
1394   }
1395 
1396   if (Lgkmcnt != getLgkmcntBitMask(ISA)) {
1397     if (NeedSpace)
1398       O << ' ';
1399     O << "lgkmcnt(" << Lgkmcnt << ')';
1400   }
1401 }
1402 
1403 void AMDGPUInstPrinter::printHwreg(const MCInst *MI, unsigned OpNo,
1404                                    const MCSubtargetInfo &STI, raw_ostream &O) {
1405   unsigned Id;
1406   unsigned Offset;
1407   unsigned Width;
1408 
1409   using namespace llvm::AMDGPU::Hwreg;
1410   unsigned Val = MI->getOperand(OpNo).getImm();
1411   decodeHwreg(Val, Id, Offset, Width);
1412   StringRef HwRegName = getHwreg(Id, STI);
1413 
1414   O << "hwreg(";
1415   if (!HwRegName.empty()) {
1416     O << HwRegName;
1417   } else {
1418     O << Id;
1419   }
1420   if (Width != WIDTH_DEFAULT_ || Offset != OFFSET_DEFAULT_) {
1421     O << ", " << Offset << ", " << Width;
1422   }
1423   O << ')';
1424 }
1425 
1426 void AMDGPUInstPrinter::printEndpgm(const MCInst *MI, unsigned OpNo,
1427                                     const MCSubtargetInfo &STI,
1428                                     raw_ostream &O) {
1429   uint16_t Imm = MI->getOperand(OpNo).getImm();
1430   if (Imm == 0) {
1431     return;
1432   }
1433 
1434   O << ' ' << formatDec(Imm);
1435 }
1436 
1437 #include "AMDGPUGenAsmWriter.inc"
1438 
1439 void R600InstPrinter::printInst(const MCInst *MI, uint64_t Address,
1440                                 StringRef Annot, const MCSubtargetInfo &STI,
1441                                 raw_ostream &O) {
1442   O.flush();
1443   printInstruction(MI, Address, O);
1444   printAnnotation(O, Annot);
1445 }
1446 
1447 void R600InstPrinter::printAbs(const MCInst *MI, unsigned OpNo,
1448                                raw_ostream &O) {
1449   AMDGPUInstPrinter::printIfSet(MI, OpNo, O, '|');
1450 }
1451 
1452 void R600InstPrinter::printBankSwizzle(const MCInst *MI, unsigned OpNo,
1453                                        raw_ostream &O) {
1454   int BankSwizzle = MI->getOperand(OpNo).getImm();
1455   switch (BankSwizzle) {
1456   case 1:
1457     O << "BS:VEC_021/SCL_122";
1458     break;
1459   case 2:
1460     O << "BS:VEC_120/SCL_212";
1461     break;
1462   case 3:
1463     O << "BS:VEC_102/SCL_221";
1464     break;
1465   case 4:
1466     O << "BS:VEC_201";
1467     break;
1468   case 5:
1469     O << "BS:VEC_210";
1470     break;
1471   default:
1472     break;
1473   }
1474 }
1475 
1476 void R600InstPrinter::printClamp(const MCInst *MI, unsigned OpNo,
1477                                  raw_ostream &O) {
1478   AMDGPUInstPrinter::printIfSet(MI, OpNo, O, "_SAT");
1479 }
1480 
1481 void R600InstPrinter::printCT(const MCInst *MI, unsigned OpNo,
1482                                 raw_ostream &O) {
1483   unsigned CT = MI->getOperand(OpNo).getImm();
1484   switch (CT) {
1485   case 0:
1486     O << 'U';
1487     break;
1488   case 1:
1489     O << 'N';
1490     break;
1491   default:
1492     break;
1493   }
1494 }
1495 
1496 void R600InstPrinter::printKCache(const MCInst *MI, unsigned OpNo,
1497                                   raw_ostream &O) {
1498   int KCacheMode = MI->getOperand(OpNo).getImm();
1499   if (KCacheMode > 0) {
1500     int KCacheBank = MI->getOperand(OpNo - 2).getImm();
1501     O << "CB" << KCacheBank << ':';
1502     int KCacheAddr = MI->getOperand(OpNo + 2).getImm();
1503     int LineSize = (KCacheMode == 1) ? 16 : 32;
1504     O << KCacheAddr * 16 << '-' << KCacheAddr * 16 + LineSize;
1505   }
1506 }
1507 
1508 void R600InstPrinter::printLast(const MCInst *MI, unsigned OpNo,
1509                                 raw_ostream &O) {
1510   AMDGPUInstPrinter::printIfSet(MI, OpNo, O, "*", " ");
1511 }
1512 
1513 void R600InstPrinter::printLiteral(const MCInst *MI, unsigned OpNo,
1514                                    raw_ostream &O) {
1515   const MCOperand &Op = MI->getOperand(OpNo);
1516   assert(Op.isImm() || Op.isExpr());
1517   if (Op.isImm()) {
1518     int64_t Imm = Op.getImm();
1519     O << Imm << '(' << BitsToFloat(Imm) << ')';
1520   }
1521   if (Op.isExpr()) {
1522     Op.getExpr()->print(O << '@', &MAI);
1523   }
1524 }
1525 
1526 void R600InstPrinter::printNeg(const MCInst *MI, unsigned OpNo,
1527                                raw_ostream &O) {
1528   AMDGPUInstPrinter::printIfSet(MI, OpNo, O, '-');
1529 }
1530 
1531 void R600InstPrinter::printOMOD(const MCInst *MI, unsigned OpNo,
1532                                 raw_ostream &O) {
1533   switch (MI->getOperand(OpNo).getImm()) {
1534   default: break;
1535   case 1:
1536     O << " * 2.0";
1537     break;
1538   case 2:
1539     O << " * 4.0";
1540     break;
1541   case 3:
1542     O << " / 2.0";
1543     break;
1544   }
1545 }
1546 
1547 void R600InstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo,
1548                                       raw_ostream &O) {
1549   printOperand(MI, OpNo, O);
1550   O  << ", ";
1551   printOperand(MI, OpNo + 1, O);
1552 }
1553 
1554 void R600InstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
1555                                    raw_ostream &O) {
1556   if (OpNo >= MI->getNumOperands()) {
1557     O << "/*Missing OP" << OpNo << "*/";
1558     return;
1559   }
1560 
1561   const MCOperand &Op = MI->getOperand(OpNo);
1562   if (Op.isReg()) {
1563     switch (Op.getReg()) {
1564     // This is the default predicate state, so we don't need to print it.
1565     case R600::PRED_SEL_OFF:
1566       break;
1567 
1568     default:
1569       O << getRegisterName(Op.getReg());
1570       break;
1571     }
1572   } else if (Op.isImm()) {
1573       O << Op.getImm();
1574   } else if (Op.isFPImm()) {
1575     // We special case 0.0 because otherwise it will be printed as an integer.
1576     if (Op.getFPImm() == 0.0)
1577       O << "0.0";
1578     else {
1579       O << Op.getFPImm();
1580     }
1581   } else if (Op.isExpr()) {
1582     const MCExpr *Exp = Op.getExpr();
1583     Exp->print(O, &MAI);
1584   } else {
1585     O << "/*INV_OP*/";
1586   }
1587 }
1588 
1589 void R600InstPrinter::printRel(const MCInst *MI, unsigned OpNo,
1590                                raw_ostream &O) {
1591   AMDGPUInstPrinter::printIfSet(MI, OpNo, O, '+');
1592 }
1593 
1594 void R600InstPrinter::printRSel(const MCInst *MI, unsigned OpNo,
1595                                   raw_ostream &O) {
1596   unsigned Sel = MI->getOperand(OpNo).getImm();
1597   switch (Sel) {
1598   case 0:
1599     O << 'X';
1600     break;
1601   case 1:
1602     O << 'Y';
1603     break;
1604   case 2:
1605     O << 'Z';
1606     break;
1607   case 3:
1608     O << 'W';
1609     break;
1610   case 4:
1611     O << '0';
1612     break;
1613   case 5:
1614     O << '1';
1615     break;
1616   case 7:
1617     O << '_';
1618     break;
1619   default:
1620     break;
1621   }
1622 }
1623 
1624 void R600InstPrinter::printUpdateExecMask(const MCInst *MI, unsigned OpNo,
1625                                           raw_ostream &O) {
1626   AMDGPUInstPrinter::printIfSet(MI, OpNo, O, "ExecMask,");
1627 }
1628 
1629 void R600InstPrinter::printUpdatePred(const MCInst *MI, unsigned OpNo,
1630                                       raw_ostream &O) {
1631   AMDGPUInstPrinter::printIfSet(MI, OpNo, O, "Pred,");
1632 }
1633 
1634 void R600InstPrinter::printWrite(const MCInst *MI, unsigned OpNo,
1635                                  raw_ostream &O) {
1636   const MCOperand &Op = MI->getOperand(OpNo);
1637   if (Op.getImm() == 0) {
1638     O << " (MASKED)";
1639   }
1640 }
1641 
1642 #include "R600GenAsmWriter.inc"
1643