1 //===-- AMDGPUInstPrinter.cpp - AMDGPU MC Inst -> ASM ---------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 // \file
8 //===----------------------------------------------------------------------===//
9 
10 #include "AMDGPUInstPrinter.h"
11 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
12 #include "SIDefines.h"
13 #include "SIRegisterInfo.h"
14 #include "Utils/AMDGPUAsmUtils.h"
15 #include "Utils/AMDGPUBaseInfo.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCInstrDesc.h"
19 #include "llvm/MC/MCInstrInfo.h"
20 #include "llvm/MC/MCSubtargetInfo.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/TargetParser.h"
23 
24 using namespace llvm;
25 using namespace llvm::AMDGPU;
26 
27 static cl::opt<bool> Keep16BitSuffixes(
28   "amdgpu-keep-16-bit-reg-suffixes",
29   cl::desc("Keep .l and .h suffixes in asm for debugging purposes"),
30   cl::init(false),
31   cl::ReallyHidden);
32 
33 void AMDGPUInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
34   // FIXME: The current implementation of
35   // AsmParser::parseRegisterOrRegisterNumber in MC implies we either emit this
36   // as an integer or we provide a name which represents a physical register.
37   // For CFI instructions we really want to emit a name for the DWARF register
38   // instead, because there may be multiple DWARF registers corresponding to a
39   // single physical register. One case where this problem manifests is with
40   // wave32/wave64 where using the physical register name is ambiguous: if we
41   // write e.g. `.cfi_undefined v0` we lose information about the wavefront
42   // size which we need to encode the register in the final DWARF. Ideally we
43   // would extend MC to support parsing DWARF register names so we could do
44   // something like `.cfi_undefined dwarf_wave32_v0`. For now we just live with
45   // non-pretty DWARF register names in assembly text.
46   OS << RegNo;
47 }
48 
49 void AMDGPUInstPrinter::printInst(const MCInst *MI, uint64_t Address,
50                                   StringRef Annot, const MCSubtargetInfo &STI,
51                                   raw_ostream &OS) {
52   OS.flush();
53   printInstruction(MI, Address, STI, OS);
54   printAnnotation(OS, Annot);
55 }
56 
57 void AMDGPUInstPrinter::printU4ImmOperand(const MCInst *MI, unsigned OpNo,
58                                           const MCSubtargetInfo &STI,
59                                           raw_ostream &O) {
60   O << formatHex(MI->getOperand(OpNo).getImm() & 0xf);
61 }
62 
63 void AMDGPUInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo,
64                                           raw_ostream &O) {
65   O << formatHex(MI->getOperand(OpNo).getImm() & 0xff);
66 }
67 
68 void AMDGPUInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
69                                            const MCSubtargetInfo &STI,
70                                            raw_ostream &O) {
71   // It's possible to end up with a 32-bit literal used with a 16-bit operand
72   // with ignored high bits. Print as 32-bit anyway in that case.
73   int64_t Imm = MI->getOperand(OpNo).getImm();
74   if (isInt<16>(Imm) || isUInt<16>(Imm))
75     O << formatHex(static_cast<uint64_t>(Imm & 0xffff));
76   else
77     printU32ImmOperand(MI, OpNo, STI, O);
78 }
79 
80 void AMDGPUInstPrinter::printU4ImmDecOperand(const MCInst *MI, unsigned OpNo,
81                                              raw_ostream &O) {
82   O << formatDec(MI->getOperand(OpNo).getImm() & 0xf);
83 }
84 
85 void AMDGPUInstPrinter::printU8ImmDecOperand(const MCInst *MI, unsigned OpNo,
86                                              raw_ostream &O) {
87   O << formatDec(MI->getOperand(OpNo).getImm() & 0xff);
88 }
89 
90 void AMDGPUInstPrinter::printU16ImmDecOperand(const MCInst *MI, unsigned OpNo,
91                                               raw_ostream &O) {
92   O << formatDec(MI->getOperand(OpNo).getImm() & 0xffff);
93 }
94 
95 void AMDGPUInstPrinter::printU32ImmOperand(const MCInst *MI, unsigned OpNo,
96                                            const MCSubtargetInfo &STI,
97                                            raw_ostream &O) {
98   O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff);
99 }
100 
101 void AMDGPUInstPrinter::printNamedBit(const MCInst *MI, unsigned OpNo,
102                                       raw_ostream &O, StringRef BitName) {
103   if (MI->getOperand(OpNo).getImm()) {
104     O << ' ' << BitName;
105   }
106 }
107 
108 void AMDGPUInstPrinter::printOffen(const MCInst *MI, unsigned OpNo,
109                                    raw_ostream &O) {
110   printNamedBit(MI, OpNo, O, "offen");
111 }
112 
113 void AMDGPUInstPrinter::printIdxen(const MCInst *MI, unsigned OpNo,
114                                    raw_ostream &O) {
115   printNamedBit(MI, OpNo, O, "idxen");
116 }
117 
118 void AMDGPUInstPrinter::printAddr64(const MCInst *MI, unsigned OpNo,
119                                     raw_ostream &O) {
120   printNamedBit(MI, OpNo, O, "addr64");
121 }
122 
123 void AMDGPUInstPrinter::printMBUFOffset(const MCInst *MI, unsigned OpNo,
124                                         raw_ostream &O) {
125   if (MI->getOperand(OpNo).getImm()) {
126     O << " offset:";
127     printU16ImmDecOperand(MI, OpNo, O);
128   }
129 }
130 
131 void AMDGPUInstPrinter::printOffset(const MCInst *MI, unsigned OpNo,
132                                     const MCSubtargetInfo &STI,
133                                     raw_ostream &O) {
134   uint16_t Imm = MI->getOperand(OpNo).getImm();
135   if (Imm != 0) {
136     O << " offset:";
137     printU16ImmDecOperand(MI, OpNo, O);
138   }
139 }
140 
141 void AMDGPUInstPrinter::printFlatOffset(const MCInst *MI, unsigned OpNo,
142                                         const MCSubtargetInfo &STI,
143                                         raw_ostream &O) {
144   uint16_t Imm = MI->getOperand(OpNo).getImm();
145   if (Imm != 0) {
146     O << " offset:";
147 
148     const MCInstrDesc &Desc = MII.get(MI->getOpcode());
149     bool IsFlatSeg = !(Desc.TSFlags &
150         (SIInstrFlags::IsFlatGlobal | SIInstrFlags::IsFlatScratch));
151 
152     if (IsFlatSeg) { // Unsigned offset
153       printU16ImmDecOperand(MI, OpNo, O);
154     } else {         // Signed offset
155       if (AMDGPU::isGFX10Plus(STI)) {
156         O << formatDec(SignExtend32<12>(MI->getOperand(OpNo).getImm()));
157       } else {
158         O << formatDec(SignExtend32<13>(MI->getOperand(OpNo).getImm()));
159       }
160     }
161   }
162 }
163 
164 void AMDGPUInstPrinter::printOffset0(const MCInst *MI, unsigned OpNo,
165                                      const MCSubtargetInfo &STI,
166                                      raw_ostream &O) {
167   if (MI->getOperand(OpNo).getImm()) {
168     O << " offset0:";
169     printU8ImmDecOperand(MI, OpNo, O);
170   }
171 }
172 
173 void AMDGPUInstPrinter::printOffset1(const MCInst *MI, unsigned OpNo,
174                                      const MCSubtargetInfo &STI,
175                                      raw_ostream &O) {
176   if (MI->getOperand(OpNo).getImm()) {
177     O << " offset1:";
178     printU8ImmDecOperand(MI, OpNo, O);
179   }
180 }
181 
182 void AMDGPUInstPrinter::printSMRDOffset8(const MCInst *MI, unsigned OpNo,
183                                         const MCSubtargetInfo &STI,
184                                         raw_ostream &O) {
185   printU32ImmOperand(MI, OpNo, STI, O);
186 }
187 
188 void AMDGPUInstPrinter::printSMEMOffset(const MCInst *MI, unsigned OpNo,
189                                         const MCSubtargetInfo &STI,
190                                         raw_ostream &O) {
191   O << formatHex(MI->getOperand(OpNo).getImm());
192 }
193 
194 void AMDGPUInstPrinter::printSMRDLiteralOffset(const MCInst *MI, unsigned OpNo,
195                                                const MCSubtargetInfo &STI,
196                                                raw_ostream &O) {
197   printU32ImmOperand(MI, OpNo, STI, O);
198 }
199 
200 void AMDGPUInstPrinter::printGDS(const MCInst *MI, unsigned OpNo,
201                                  const MCSubtargetInfo &STI, raw_ostream &O) {
202   printNamedBit(MI, OpNo, O, "gds");
203 }
204 
205 void AMDGPUInstPrinter::printDLC(const MCInst *MI, unsigned OpNo,
206                                  const MCSubtargetInfo &STI, raw_ostream &O) {
207   if (AMDGPU::isGFX10Plus(STI))
208     printNamedBit(MI, OpNo, O, "dlc");
209 }
210 
211 void AMDGPUInstPrinter::printSCCB(const MCInst *MI, unsigned OpNo,
212                                   const MCSubtargetInfo &STI, raw_ostream &O) {
213   if (AMDGPU::isGFX90A(STI))
214     printNamedBit(MI, OpNo, O, "scc");
215 }
216 
217 void AMDGPUInstPrinter::printGLC(const MCInst *MI, unsigned OpNo,
218                                  const MCSubtargetInfo &STI, raw_ostream &O) {
219   printNamedBit(MI, OpNo, O, "glc");
220 }
221 
222 void AMDGPUInstPrinter::printSLC(const MCInst *MI, unsigned OpNo,
223                                  const MCSubtargetInfo &STI, raw_ostream &O) {
224   printNamedBit(MI, OpNo, O, "slc");
225 }
226 
227 void AMDGPUInstPrinter::printSWZ(const MCInst *MI, unsigned OpNo,
228                                  const MCSubtargetInfo &STI, raw_ostream &O) {
229 }
230 
231 void AMDGPUInstPrinter::printTFE(const MCInst *MI, unsigned OpNo,
232                                  const MCSubtargetInfo &STI, raw_ostream &O) {
233   printNamedBit(MI, OpNo, O, "tfe");
234 }
235 
236 void AMDGPUInstPrinter::printDMask(const MCInst *MI, unsigned OpNo,
237                                    const MCSubtargetInfo &STI, raw_ostream &O) {
238   if (MI->getOperand(OpNo).getImm()) {
239     O << " dmask:";
240     printU16ImmOperand(MI, OpNo, STI, O);
241   }
242 }
243 
244 void AMDGPUInstPrinter::printDim(const MCInst *MI, unsigned OpNo,
245                                  const MCSubtargetInfo &STI, raw_ostream &O) {
246   unsigned Dim = MI->getOperand(OpNo).getImm();
247   O << " dim:SQ_RSRC_IMG_";
248 
249   const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfoByEncoding(Dim);
250   if (DimInfo)
251     O << DimInfo->AsmSuffix;
252   else
253     O << Dim;
254 }
255 
256 void AMDGPUInstPrinter::printUNorm(const MCInst *MI, unsigned OpNo,
257                                    const MCSubtargetInfo &STI, raw_ostream &O) {
258   printNamedBit(MI, OpNo, O, "unorm");
259 }
260 
261 void AMDGPUInstPrinter::printDA(const MCInst *MI, unsigned OpNo,
262                                 const MCSubtargetInfo &STI, raw_ostream &O) {
263   printNamedBit(MI, OpNo, O, "da");
264 }
265 
266 void AMDGPUInstPrinter::printR128A16(const MCInst *MI, unsigned OpNo,
267                                   const MCSubtargetInfo &STI, raw_ostream &O) {
268   if (STI.hasFeature(AMDGPU::FeatureR128A16))
269     printNamedBit(MI, OpNo, O, "a16");
270   else
271     printNamedBit(MI, OpNo, O, "r128");
272 }
273 
274 void AMDGPUInstPrinter::printGFX10A16(const MCInst *MI, unsigned OpNo,
275                                   const MCSubtargetInfo &STI, raw_ostream &O) {
276   printNamedBit(MI, OpNo, O, "a16");
277 }
278 
279 void AMDGPUInstPrinter::printLWE(const MCInst *MI, unsigned OpNo,
280                                  const MCSubtargetInfo &STI, raw_ostream &O) {
281   printNamedBit(MI, OpNo, O, "lwe");
282 }
283 
284 void AMDGPUInstPrinter::printD16(const MCInst *MI, unsigned OpNo,
285                                  const MCSubtargetInfo &STI, raw_ostream &O) {
286   printNamedBit(MI, OpNo, O, "d16");
287 }
288 
289 void AMDGPUInstPrinter::printExpCompr(const MCInst *MI, unsigned OpNo,
290                                       const MCSubtargetInfo &STI,
291                                       raw_ostream &O) {
292   printNamedBit(MI, OpNo, O, "compr");
293 }
294 
295 void AMDGPUInstPrinter::printExpVM(const MCInst *MI, unsigned OpNo,
296                                    const MCSubtargetInfo &STI,
297                                    raw_ostream &O) {
298   printNamedBit(MI, OpNo, O, "vm");
299 }
300 
301 void AMDGPUInstPrinter::printFORMAT(const MCInst *MI, unsigned OpNo,
302                                     const MCSubtargetInfo &STI,
303                                     raw_ostream &O) {
304 }
305 
306 void AMDGPUInstPrinter::printSymbolicFormat(const MCInst *MI,
307                                             const MCSubtargetInfo &STI,
308                                             raw_ostream &O) {
309   using namespace llvm::AMDGPU::MTBUFFormat;
310 
311   int OpNo =
312     AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::format);
313   assert(OpNo != -1);
314 
315   unsigned Val = MI->getOperand(OpNo).getImm();
316   if (AMDGPU::isGFX10Plus(STI)) {
317     if (Val == UFMT_DEFAULT)
318       return;
319     if (isValidUnifiedFormat(Val)) {
320       O << " format:[" << getUnifiedFormatName(Val) << ']';
321     } else {
322       O << " format:" << Val;
323     }
324   } else {
325     if (Val == DFMT_NFMT_DEFAULT)
326       return;
327     if (isValidDfmtNfmt(Val, STI)) {
328       unsigned Dfmt;
329       unsigned Nfmt;
330       decodeDfmtNfmt(Val, Dfmt, Nfmt);
331       O << " format:[";
332       if (Dfmt != DFMT_DEFAULT) {
333         O << getDfmtName(Dfmt);
334         if (Nfmt != NFMT_DEFAULT) {
335           O << ',';
336         }
337       }
338       if (Nfmt != NFMT_DEFAULT) {
339         O << getNfmtName(Nfmt, STI);
340       }
341       O << ']';
342     } else {
343       O << " format:" << Val;
344     }
345   }
346 }
347 
348 void AMDGPUInstPrinter::printRegOperand(unsigned RegNo, raw_ostream &O,
349                                         const MCRegisterInfo &MRI) {
350 #if !defined(NDEBUG)
351   switch (RegNo) {
352   case AMDGPU::FP_REG:
353   case AMDGPU::SP_REG:
354   case AMDGPU::PRIVATE_RSRC_REG:
355     llvm_unreachable("pseudo-register should not ever be emitted");
356   case AMDGPU::SCC:
357     llvm_unreachable("pseudo scc should not ever be emitted");
358   default:
359     break;
360   }
361 #endif
362 
363   StringRef RegName(getRegisterName(RegNo));
364   if (!Keep16BitSuffixes)
365     if (!RegName.consume_back(".l"))
366       RegName.consume_back(".h");
367 
368   O << RegName;
369 }
370 
371 void AMDGPUInstPrinter::printVOPDst(const MCInst *MI, unsigned OpNo,
372                                     const MCSubtargetInfo &STI, raw_ostream &O) {
373   if (OpNo == 0) {
374     if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::VOP3)
375       O << "_e64 ";
376     else if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::DPP)
377       O << "_dpp ";
378     else if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::SDWA)
379       O << "_sdwa ";
380     else
381       O << "_e32 ";
382   }
383 
384   printOperand(MI, OpNo, STI, O);
385 
386   // Print default vcc/vcc_lo operand.
387   switch (MI->getOpcode()) {
388   default: break;
389 
390   case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10:
391   case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10:
392   case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10:
393   case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10:
394   case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10:
395   case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10:
396   case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10:
397   case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10:
398   case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10:
399   case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10:
400   case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10:
401   case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10:
402     printDefaultVccOperand(1, STI, O);
403     break;
404   }
405 }
406 
407 void AMDGPUInstPrinter::printVINTRPDst(const MCInst *MI, unsigned OpNo,
408                                        const MCSubtargetInfo &STI, raw_ostream &O) {
409   if (AMDGPU::isSI(STI) || AMDGPU::isCI(STI))
410     O << " ";
411   else
412     O << "_e32 ";
413 
414   printOperand(MI, OpNo, STI, O);
415 }
416 
417 void AMDGPUInstPrinter::printImmediateInt16(uint32_t Imm,
418                                             const MCSubtargetInfo &STI,
419                                             raw_ostream &O) {
420   int16_t SImm = static_cast<int16_t>(Imm);
421   if (isInlinableIntLiteral(SImm)) {
422     O << SImm;
423   } else {
424     uint64_t Imm16 = static_cast<uint16_t>(Imm);
425     O << formatHex(Imm16);
426   }
427 }
428 
429 void AMDGPUInstPrinter::printImmediate16(uint32_t Imm,
430                                          const MCSubtargetInfo &STI,
431                                          raw_ostream &O) {
432   int16_t SImm = static_cast<int16_t>(Imm);
433   if (isInlinableIntLiteral(SImm)) {
434     O << SImm;
435     return;
436   }
437 
438   if (Imm == 0x3C00)
439     O<< "1.0";
440   else if (Imm == 0xBC00)
441     O<< "-1.0";
442   else if (Imm == 0x3800)
443     O<< "0.5";
444   else if (Imm == 0xB800)
445     O<< "-0.5";
446   else if (Imm == 0x4000)
447     O<< "2.0";
448   else if (Imm == 0xC000)
449     O<< "-2.0";
450   else if (Imm == 0x4400)
451     O<< "4.0";
452   else if (Imm == 0xC400)
453     O<< "-4.0";
454   else if (Imm == 0x3118 &&
455            STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]) {
456     O << "0.15915494";
457   } else {
458     uint64_t Imm16 = static_cast<uint16_t>(Imm);
459     O << formatHex(Imm16);
460   }
461 }
462 
463 void AMDGPUInstPrinter::printImmediateV216(uint32_t Imm,
464                                            const MCSubtargetInfo &STI,
465                                            raw_ostream &O) {
466   uint16_t Lo16 = static_cast<uint16_t>(Imm);
467   printImmediate16(Lo16, STI, O);
468 }
469 
470 void AMDGPUInstPrinter::printImmediate32(uint32_t Imm,
471                                          const MCSubtargetInfo &STI,
472                                          raw_ostream &O) {
473   int32_t SImm = static_cast<int32_t>(Imm);
474   if (SImm >= -16 && SImm <= 64) {
475     O << SImm;
476     return;
477   }
478 
479   if (Imm == FloatToBits(0.0f))
480     O << "0.0";
481   else if (Imm == FloatToBits(1.0f))
482     O << "1.0";
483   else if (Imm == FloatToBits(-1.0f))
484     O << "-1.0";
485   else if (Imm == FloatToBits(0.5f))
486     O << "0.5";
487   else if (Imm == FloatToBits(-0.5f))
488     O << "-0.5";
489   else if (Imm == FloatToBits(2.0f))
490     O << "2.0";
491   else if (Imm == FloatToBits(-2.0f))
492     O << "-2.0";
493   else if (Imm == FloatToBits(4.0f))
494     O << "4.0";
495   else if (Imm == FloatToBits(-4.0f))
496     O << "-4.0";
497   else if (Imm == 0x3e22f983 &&
498            STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
499     O << "0.15915494";
500   else
501     O << formatHex(static_cast<uint64_t>(Imm));
502 }
503 
504 void AMDGPUInstPrinter::printImmediate64(uint64_t Imm,
505                                          const MCSubtargetInfo &STI,
506                                          raw_ostream &O) {
507   int64_t SImm = static_cast<int64_t>(Imm);
508   if (SImm >= -16 && SImm <= 64) {
509     O << SImm;
510     return;
511   }
512 
513   if (Imm == DoubleToBits(0.0))
514     O << "0.0";
515   else if (Imm == DoubleToBits(1.0))
516     O << "1.0";
517   else if (Imm == DoubleToBits(-1.0))
518     O << "-1.0";
519   else if (Imm == DoubleToBits(0.5))
520     O << "0.5";
521   else if (Imm == DoubleToBits(-0.5))
522     O << "-0.5";
523   else if (Imm == DoubleToBits(2.0))
524     O << "2.0";
525   else if (Imm == DoubleToBits(-2.0))
526     O << "-2.0";
527   else if (Imm == DoubleToBits(4.0))
528     O << "4.0";
529   else if (Imm == DoubleToBits(-4.0))
530     O << "-4.0";
531   else if (Imm == 0x3fc45f306dc9c882 &&
532            STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
533     O << "0.15915494309189532";
534   else {
535     assert(isUInt<32>(Imm) || Imm == 0x3fc45f306dc9c882);
536 
537     // In rare situations, we will have a 32-bit literal in a 64-bit
538     // operand. This is technically allowed for the encoding of s_mov_b64.
539     O << formatHex(static_cast<uint64_t>(Imm));
540   }
541 }
542 
543 void AMDGPUInstPrinter::printBLGP(const MCInst *MI, unsigned OpNo,
544                                   const MCSubtargetInfo &STI,
545                                   raw_ostream &O) {
546   unsigned Imm = MI->getOperand(OpNo).getImm();
547   if (!Imm)
548     return;
549 
550   O << " blgp:" << Imm;
551 }
552 
553 void AMDGPUInstPrinter::printCBSZ(const MCInst *MI, unsigned OpNo,
554                                   const MCSubtargetInfo &STI,
555                                   raw_ostream &O) {
556   unsigned Imm = MI->getOperand(OpNo).getImm();
557   if (!Imm)
558     return;
559 
560   O << " cbsz:" << Imm;
561 }
562 
563 void AMDGPUInstPrinter::printABID(const MCInst *MI, unsigned OpNo,
564                                   const MCSubtargetInfo &STI,
565                                   raw_ostream &O) {
566   unsigned Imm = MI->getOperand(OpNo).getImm();
567   if (!Imm)
568     return;
569 
570   O << " abid:" << Imm;
571 }
572 
573 void AMDGPUInstPrinter::printDefaultVccOperand(unsigned OpNo,
574                                                const MCSubtargetInfo &STI,
575                                                raw_ostream &O) {
576   if (OpNo > 0)
577     O << ", ";
578   printRegOperand(STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ?
579                   AMDGPU::VCC : AMDGPU::VCC_LO, O, MRI);
580   if (OpNo == 0)
581     O << ", ";
582 }
583 
584 void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
585                                      const MCSubtargetInfo &STI,
586                                      raw_ostream &O) {
587   // Print default vcc/vcc_lo operand of VOPC.
588   const MCInstrDesc &Desc = MII.get(MI->getOpcode());
589   if (OpNo == 0 && (Desc.TSFlags & SIInstrFlags::VOPC) &&
590       (Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC) ||
591        Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC_LO)))
592     printDefaultVccOperand(OpNo, STI, O);
593 
594   if (OpNo >= MI->getNumOperands()) {
595     O << "/*Missing OP" << OpNo << "*/";
596     return;
597   }
598 
599   const MCOperand &Op = MI->getOperand(OpNo);
600   if (Op.isReg()) {
601     printRegOperand(Op.getReg(), O, MRI);
602   } else if (Op.isImm()) {
603     const uint8_t OpTy = Desc.OpInfo[OpNo].OperandType;
604     switch (OpTy) {
605     case AMDGPU::OPERAND_REG_IMM_INT32:
606     case AMDGPU::OPERAND_REG_IMM_FP32:
607     case AMDGPU::OPERAND_REG_INLINE_C_INT32:
608     case AMDGPU::OPERAND_REG_INLINE_C_FP32:
609     case AMDGPU::OPERAND_REG_INLINE_AC_INT32:
610     case AMDGPU::OPERAND_REG_INLINE_AC_FP32:
611     case AMDGPU::OPERAND_REG_IMM_V2INT32:
612     case AMDGPU::OPERAND_REG_IMM_V2FP32:
613     case AMDGPU::OPERAND_REG_INLINE_C_V2INT32:
614     case AMDGPU::OPERAND_REG_INLINE_C_V2FP32:
615     case MCOI::OPERAND_IMMEDIATE:
616       printImmediate32(Op.getImm(), STI, O);
617       break;
618     case AMDGPU::OPERAND_REG_IMM_INT64:
619     case AMDGPU::OPERAND_REG_IMM_FP64:
620     case AMDGPU::OPERAND_REG_INLINE_C_INT64:
621     case AMDGPU::OPERAND_REG_INLINE_C_FP64:
622     case AMDGPU::OPERAND_REG_INLINE_AC_FP64:
623       printImmediate64(Op.getImm(), STI, O);
624       break;
625     case AMDGPU::OPERAND_REG_INLINE_C_INT16:
626     case AMDGPU::OPERAND_REG_INLINE_AC_INT16:
627     case AMDGPU::OPERAND_REG_IMM_INT16:
628       printImmediateInt16(Op.getImm(), STI, O);
629       break;
630     case AMDGPU::OPERAND_REG_INLINE_C_FP16:
631     case AMDGPU::OPERAND_REG_INLINE_AC_FP16:
632     case AMDGPU::OPERAND_REG_IMM_FP16:
633       printImmediate16(Op.getImm(), STI, O);
634       break;
635     case AMDGPU::OPERAND_REG_IMM_V2INT16:
636     case AMDGPU::OPERAND_REG_IMM_V2FP16:
637       if (!isUInt<16>(Op.getImm()) &&
638           STI.getFeatureBits()[AMDGPU::FeatureVOP3Literal]) {
639         printImmediate32(Op.getImm(), STI, O);
640         break;
641       }
642 
643       //  Deal with 16-bit FP inline immediates not working.
644       if (OpTy == AMDGPU::OPERAND_REG_IMM_V2FP16) {
645         printImmediate16(static_cast<uint16_t>(Op.getImm()), STI, O);
646         break;
647       }
648       LLVM_FALLTHROUGH;
649     case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
650     case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:
651       printImmediateInt16(static_cast<uint16_t>(Op.getImm()), STI, O);
652       break;
653     case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
654     case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16:
655       printImmediateV216(Op.getImm(), STI, O);
656       break;
657     case MCOI::OPERAND_UNKNOWN:
658     case MCOI::OPERAND_PCREL:
659       O << formatDec(Op.getImm());
660       break;
661     case MCOI::OPERAND_REGISTER:
662       // FIXME: This should be removed and handled somewhere else. Seems to come
663       // from a disassembler bug.
664       O << "/*invalid immediate*/";
665       break;
666     default:
667       // We hit this for the immediate instruction bits that don't yet have a
668       // custom printer.
669       llvm_unreachable("unexpected immediate operand type");
670     }
671   } else if (Op.isDFPImm()) {
672     double Value = bit_cast<double>(Op.getDFPImm());
673     // We special case 0.0 because otherwise it will be printed as an integer.
674     if (Value == 0.0)
675       O << "0.0";
676     else {
677       const MCInstrDesc &Desc = MII.get(MI->getOpcode());
678       int RCID = Desc.OpInfo[OpNo].RegClass;
679       unsigned RCBits = AMDGPU::getRegBitWidth(MRI.getRegClass(RCID));
680       if (RCBits == 32)
681         printImmediate32(FloatToBits(Value), STI, O);
682       else if (RCBits == 64)
683         printImmediate64(DoubleToBits(Value), STI, O);
684       else
685         llvm_unreachable("Invalid register class size");
686     }
687   } else if (Op.isExpr()) {
688     const MCExpr *Exp = Op.getExpr();
689     Exp->print(O, &MAI);
690   } else {
691     O << "/*INV_OP*/";
692   }
693 
694   // Print default vcc/vcc_lo operand of v_cndmask_b32_e32.
695   switch (MI->getOpcode()) {
696   default: break;
697 
698   case AMDGPU::V_CNDMASK_B32_e32_gfx10:
699   case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10:
700   case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10:
701   case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10:
702   case AMDGPU::V_CNDMASK_B32_dpp_gfx10:
703   case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10:
704   case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10:
705   case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10:
706   case AMDGPU::V_CNDMASK_B32_dpp8_gfx10:
707   case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10:
708   case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10:
709   case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10:
710 
711   case AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7:
712   case AMDGPU::V_CNDMASK_B32_e32_vi:
713     if ((int)OpNo == AMDGPU::getNamedOperandIdx(MI->getOpcode(),
714                                                 AMDGPU::OpName::src1))
715       printDefaultVccOperand(OpNo, STI, O);
716     break;
717   }
718 
719   if (Desc.TSFlags & SIInstrFlags::MTBUF) {
720     int SOffsetIdx =
721       AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::soffset);
722     assert(SOffsetIdx != -1);
723     if ((int)OpNo == SOffsetIdx)
724       printSymbolicFormat(MI, STI, O);
725   }
726 }
727 
728 void AMDGPUInstPrinter::printOperandAndFPInputMods(const MCInst *MI,
729                                                    unsigned OpNo,
730                                                    const MCSubtargetInfo &STI,
731                                                    raw_ostream &O) {
732   unsigned InputModifiers = MI->getOperand(OpNo).getImm();
733 
734   // Use 'neg(...)' instead of '-' to avoid ambiguity.
735   // This is important for integer literals because
736   // -1 is not the same value as neg(1).
737   bool NegMnemo = false;
738 
739   if (InputModifiers & SISrcMods::NEG) {
740     if (OpNo + 1 < MI->getNumOperands() &&
741         (InputModifiers & SISrcMods::ABS) == 0) {
742       const MCOperand &Op = MI->getOperand(OpNo + 1);
743       NegMnemo = Op.isImm() || Op.isDFPImm();
744     }
745     if (NegMnemo) {
746       O << "neg(";
747     } else {
748       O << '-';
749     }
750   }
751 
752   if (InputModifiers & SISrcMods::ABS)
753     O << '|';
754   printOperand(MI, OpNo + 1, STI, O);
755   if (InputModifiers & SISrcMods::ABS)
756     O << '|';
757 
758   if (NegMnemo) {
759     O << ')';
760   }
761 }
762 
763 void AMDGPUInstPrinter::printOperandAndIntInputMods(const MCInst *MI,
764                                                     unsigned OpNo,
765                                                     const MCSubtargetInfo &STI,
766                                                     raw_ostream &O) {
767   unsigned InputModifiers = MI->getOperand(OpNo).getImm();
768   if (InputModifiers & SISrcMods::SEXT)
769     O << "sext(";
770   printOperand(MI, OpNo + 1, STI, O);
771   if (InputModifiers & SISrcMods::SEXT)
772     O << ')';
773 
774   // Print default vcc/vcc_lo operand of VOP2b.
775   switch (MI->getOpcode()) {
776   default: break;
777 
778   case AMDGPU::V_CNDMASK_B32_sdwa_gfx10:
779   case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10:
780   case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10:
781   case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10:
782     if ((int)OpNo + 1 == AMDGPU::getNamedOperandIdx(MI->getOpcode(),
783                                                     AMDGPU::OpName::src1))
784       printDefaultVccOperand(OpNo, STI, O);
785     break;
786   }
787 }
788 
789 void AMDGPUInstPrinter::printDPP8(const MCInst *MI, unsigned OpNo,
790                                   const MCSubtargetInfo &STI,
791                                   raw_ostream &O) {
792   if (!AMDGPU::isGFX10Plus(STI))
793     llvm_unreachable("dpp8 is not supported on ASICs earlier than GFX10");
794 
795   unsigned Imm = MI->getOperand(OpNo).getImm();
796   O << "dpp8:[" << formatDec(Imm & 0x7);
797   for (size_t i = 1; i < 8; ++i) {
798     O << ',' << formatDec((Imm >> (3 * i)) & 0x7);
799   }
800   O << ']';
801 }
802 
803 void AMDGPUInstPrinter::printDPPCtrl(const MCInst *MI, unsigned OpNo,
804                                      const MCSubtargetInfo &STI,
805                                      raw_ostream &O) {
806   using namespace AMDGPU::DPP;
807 
808   unsigned Imm = MI->getOperand(OpNo).getImm();
809   const MCInstrDesc &Desc = MII.get(MI->getOpcode());
810   int DstIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
811                                           AMDGPU::OpName::vdst);
812   int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
813                                            AMDGPU::OpName::src0);
814 
815   if (((DstIdx >= 0 &&
816         Desc.OpInfo[DstIdx].RegClass == AMDGPU::VReg_64RegClassID) ||
817       ((Src0Idx >= 0 &&
818         Desc.OpInfo[Src0Idx].RegClass == AMDGPU::VReg_64RegClassID))) &&
819       !AMDGPU::isLegal64BitDPPControl(Imm)) {
820     O << " /* 64 bit dpp only supports row_newbcast */";
821     return;
822   } else if (Imm <= DppCtrl::QUAD_PERM_LAST) {
823     O << "quad_perm:[";
824     O << formatDec(Imm & 0x3)         << ',';
825     O << formatDec((Imm & 0xc)  >> 2) << ',';
826     O << formatDec((Imm & 0x30) >> 4) << ',';
827     O << formatDec((Imm & 0xc0) >> 6) << ']';
828   } else if ((Imm >= DppCtrl::ROW_SHL_FIRST) &&
829              (Imm <= DppCtrl::ROW_SHL_LAST)) {
830     O << "row_shl:";
831     printU4ImmDecOperand(MI, OpNo, O);
832   } else if ((Imm >= DppCtrl::ROW_SHR_FIRST) &&
833              (Imm <= DppCtrl::ROW_SHR_LAST)) {
834     O << "row_shr:";
835     printU4ImmDecOperand(MI, OpNo, O);
836   } else if ((Imm >= DppCtrl::ROW_ROR_FIRST) &&
837              (Imm <= DppCtrl::ROW_ROR_LAST)) {
838     O << "row_ror:";
839     printU4ImmDecOperand(MI, OpNo, O);
840   } else if (Imm == DppCtrl::WAVE_SHL1) {
841     if (AMDGPU::isGFX10Plus(STI)) {
842       O << "/* wave_shl is not supported starting from GFX10 */";
843       return;
844     }
845     O << "wave_shl:1";
846   } else if (Imm == DppCtrl::WAVE_ROL1) {
847     if (AMDGPU::isGFX10Plus(STI)) {
848       O << "/* wave_rol is not supported starting from GFX10 */";
849       return;
850     }
851     O << "wave_rol:1";
852   } else if (Imm == DppCtrl::WAVE_SHR1) {
853     if (AMDGPU::isGFX10Plus(STI)) {
854       O << "/* wave_shr is not supported starting from GFX10 */";
855       return;
856     }
857     O << "wave_shr:1";
858   } else if (Imm == DppCtrl::WAVE_ROR1) {
859     if (AMDGPU::isGFX10Plus(STI)) {
860       O << "/* wave_ror is not supported starting from GFX10 */";
861       return;
862     }
863     O << "wave_ror:1";
864   } else if (Imm == DppCtrl::ROW_MIRROR) {
865     O << "row_mirror";
866   } else if (Imm == DppCtrl::ROW_HALF_MIRROR) {
867     O << "row_half_mirror";
868   } else if (Imm == DppCtrl::BCAST15) {
869     if (AMDGPU::isGFX10Plus(STI)) {
870       O << "/* row_bcast is not supported starting from GFX10 */";
871       return;
872     }
873     O << "row_bcast:15";
874   } else if (Imm == DppCtrl::BCAST31) {
875     if (AMDGPU::isGFX10Plus(STI)) {
876       O << "/* row_bcast is not supported starting from GFX10 */";
877       return;
878     }
879     O << "row_bcast:31";
880   } else if ((Imm >= DppCtrl::ROW_SHARE_FIRST) &&
881              (Imm <= DppCtrl::ROW_SHARE_LAST)) {
882     if (AMDGPU::isGFX90A(STI)) {
883       O << " row_newbcast:";
884     } else if (AMDGPU::isGFX10Plus(STI)) {
885       O << "row_share:";
886     } else {
887       O << " /* row_newbcast/row_share is not supported on ASICs earlier "
888            "than GFX90A/GFX10 */";
889       return;
890     }
891     printU4ImmDecOperand(MI, OpNo, O);
892   } else if ((Imm >= DppCtrl::ROW_XMASK_FIRST) &&
893              (Imm <= DppCtrl::ROW_XMASK_LAST)) {
894     if (!AMDGPU::isGFX10Plus(STI)) {
895       O << "/* row_xmask is not supported on ASICs earlier than GFX10 */";
896       return;
897     }
898     O << "row_xmask:";
899     printU4ImmDecOperand(MI, OpNo, O);
900   } else {
901     O << "/* Invalid dpp_ctrl value */";
902   }
903 }
904 
905 void AMDGPUInstPrinter::printRowMask(const MCInst *MI, unsigned OpNo,
906                                      const MCSubtargetInfo &STI,
907                                      raw_ostream &O) {
908   O << " row_mask:";
909   printU4ImmOperand(MI, OpNo, STI, O);
910 }
911 
912 void AMDGPUInstPrinter::printBankMask(const MCInst *MI, unsigned OpNo,
913                                       const MCSubtargetInfo &STI,
914                                       raw_ostream &O) {
915   O << " bank_mask:";
916   printU4ImmOperand(MI, OpNo, STI, O);
917 }
918 
919 void AMDGPUInstPrinter::printBoundCtrl(const MCInst *MI, unsigned OpNo,
920                                        const MCSubtargetInfo &STI,
921                                        raw_ostream &O) {
922   unsigned Imm = MI->getOperand(OpNo).getImm();
923   if (Imm) {
924     O << " bound_ctrl:1";
925   }
926 }
927 
928 void AMDGPUInstPrinter::printFI(const MCInst *MI, unsigned OpNo,
929                                 const MCSubtargetInfo &STI,
930                                 raw_ostream &O) {
931   using namespace llvm::AMDGPU::DPP;
932   unsigned Imm = MI->getOperand(OpNo).getImm();
933   if (Imm == DPP_FI_1 || Imm == DPP8_FI_1) {
934     O << " fi:1";
935   }
936 }
937 
938 void AMDGPUInstPrinter::printSDWASel(const MCInst *MI, unsigned OpNo,
939                                      raw_ostream &O) {
940   using namespace llvm::AMDGPU::SDWA;
941 
942   unsigned Imm = MI->getOperand(OpNo).getImm();
943   switch (Imm) {
944   case SdwaSel::BYTE_0: O << "BYTE_0"; break;
945   case SdwaSel::BYTE_1: O << "BYTE_1"; break;
946   case SdwaSel::BYTE_2: O << "BYTE_2"; break;
947   case SdwaSel::BYTE_3: O << "BYTE_3"; break;
948   case SdwaSel::WORD_0: O << "WORD_0"; break;
949   case SdwaSel::WORD_1: O << "WORD_1"; break;
950   case SdwaSel::DWORD: O << "DWORD"; break;
951   default: llvm_unreachable("Invalid SDWA data select operand");
952   }
953 }
954 
955 void AMDGPUInstPrinter::printSDWADstSel(const MCInst *MI, unsigned OpNo,
956                                         const MCSubtargetInfo &STI,
957                                         raw_ostream &O) {
958   O << "dst_sel:";
959   printSDWASel(MI, OpNo, O);
960 }
961 
962 void AMDGPUInstPrinter::printSDWASrc0Sel(const MCInst *MI, unsigned OpNo,
963                                          const MCSubtargetInfo &STI,
964                                          raw_ostream &O) {
965   O << "src0_sel:";
966   printSDWASel(MI, OpNo, O);
967 }
968 
969 void AMDGPUInstPrinter::printSDWASrc1Sel(const MCInst *MI, unsigned OpNo,
970                                          const MCSubtargetInfo &STI,
971                                          raw_ostream &O) {
972   O << "src1_sel:";
973   printSDWASel(MI, OpNo, O);
974 }
975 
976 void AMDGPUInstPrinter::printSDWADstUnused(const MCInst *MI, unsigned OpNo,
977                                            const MCSubtargetInfo &STI,
978                                            raw_ostream &O) {
979   using namespace llvm::AMDGPU::SDWA;
980 
981   O << "dst_unused:";
982   unsigned Imm = MI->getOperand(OpNo).getImm();
983   switch (Imm) {
984   case DstUnused::UNUSED_PAD: O << "UNUSED_PAD"; break;
985   case DstUnused::UNUSED_SEXT: O << "UNUSED_SEXT"; break;
986   case DstUnused::UNUSED_PRESERVE: O << "UNUSED_PRESERVE"; break;
987   default: llvm_unreachable("Invalid SDWA dest_unused operand");
988   }
989 }
990 
991 void AMDGPUInstPrinter::printExpSrcN(const MCInst *MI, unsigned OpNo,
992                                      const MCSubtargetInfo &STI, raw_ostream &O,
993                                      unsigned N) {
994   unsigned Opc = MI->getOpcode();
995   int EnIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::en);
996   unsigned En = MI->getOperand(EnIdx).getImm();
997 
998   int ComprIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::compr);
999 
1000   // If compr is set, print as src0, src0, src1, src1
1001   if (MI->getOperand(ComprIdx).getImm())
1002     OpNo = OpNo - N + N / 2;
1003 
1004   if (En & (1 << N))
1005     printRegOperand(MI->getOperand(OpNo).getReg(), O, MRI);
1006   else
1007     O << "off";
1008 }
1009 
1010 void AMDGPUInstPrinter::printExpSrc0(const MCInst *MI, unsigned OpNo,
1011                                      const MCSubtargetInfo &STI,
1012                                      raw_ostream &O) {
1013   printExpSrcN(MI, OpNo, STI, O, 0);
1014 }
1015 
1016 void AMDGPUInstPrinter::printExpSrc1(const MCInst *MI, unsigned OpNo,
1017                                      const MCSubtargetInfo &STI,
1018                                      raw_ostream &O) {
1019   printExpSrcN(MI, OpNo, STI, O, 1);
1020 }
1021 
1022 void AMDGPUInstPrinter::printExpSrc2(const MCInst *MI, unsigned OpNo,
1023                                      const MCSubtargetInfo &STI,
1024                                      raw_ostream &O) {
1025   printExpSrcN(MI, OpNo, STI, O, 2);
1026 }
1027 
1028 void AMDGPUInstPrinter::printExpSrc3(const MCInst *MI, unsigned OpNo,
1029                                      const MCSubtargetInfo &STI,
1030                                      raw_ostream &O) {
1031   printExpSrcN(MI, OpNo, STI, O, 3);
1032 }
1033 
1034 void AMDGPUInstPrinter::printExpTgt(const MCInst *MI, unsigned OpNo,
1035                                     const MCSubtargetInfo &STI,
1036                                     raw_ostream &O) {
1037   using namespace llvm::AMDGPU::Exp;
1038 
1039   // This is really a 6 bit field.
1040   unsigned Id = MI->getOperand(OpNo).getImm() & ((1 << 6) - 1);
1041 
1042   int Index;
1043   StringRef TgtName;
1044   if (getTgtName(Id, TgtName, Index) && isSupportedTgtId(Id, STI)) {
1045     O << ' ' << TgtName;
1046     if (Index >= 0)
1047       O << Index;
1048   } else {
1049     O << " invalid_target_" << Id;
1050   }
1051 }
1052 
1053 static bool allOpsDefaultValue(const int* Ops, int NumOps, int Mod,
1054                                bool IsPacked, bool HasDstSel) {
1055   int DefaultValue = IsPacked && (Mod == SISrcMods::OP_SEL_1);
1056 
1057   for (int I = 0; I < NumOps; ++I) {
1058     if (!!(Ops[I] & Mod) != DefaultValue)
1059       return false;
1060   }
1061 
1062   if (HasDstSel && (Ops[0] & SISrcMods::DST_OP_SEL) != 0)
1063     return false;
1064 
1065   return true;
1066 }
1067 
1068 void AMDGPUInstPrinter::printPackedModifier(const MCInst *MI,
1069                                             StringRef Name,
1070                                             unsigned Mod,
1071                                             raw_ostream &O) {
1072   unsigned Opc = MI->getOpcode();
1073   int NumOps = 0;
1074   int Ops[3];
1075 
1076   for (int OpName : { AMDGPU::OpName::src0_modifiers,
1077                       AMDGPU::OpName::src1_modifiers,
1078                       AMDGPU::OpName::src2_modifiers }) {
1079     int Idx = AMDGPU::getNamedOperandIdx(Opc, OpName);
1080     if (Idx == -1)
1081       break;
1082 
1083     Ops[NumOps++] = MI->getOperand(Idx).getImm();
1084   }
1085 
1086   const bool HasDstSel =
1087     NumOps > 0 &&
1088     Mod == SISrcMods::OP_SEL_0 &&
1089     MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::VOP3_OPSEL;
1090 
1091   const bool IsPacked =
1092     MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::IsPacked;
1093 
1094   if (allOpsDefaultValue(Ops, NumOps, Mod, IsPacked, HasDstSel))
1095     return;
1096 
1097   O << Name;
1098   for (int I = 0; I < NumOps; ++I) {
1099     if (I != 0)
1100       O << ',';
1101 
1102     O << !!(Ops[I] & Mod);
1103   }
1104 
1105   if (HasDstSel) {
1106     O << ',' << !!(Ops[0] & SISrcMods::DST_OP_SEL);
1107   }
1108 
1109   O << ']';
1110 }
1111 
1112 void AMDGPUInstPrinter::printOpSel(const MCInst *MI, unsigned,
1113                                    const MCSubtargetInfo &STI,
1114                                    raw_ostream &O) {
1115   unsigned Opc = MI->getOpcode();
1116   if (Opc == AMDGPU::V_PERMLANE16_B32_gfx10 ||
1117       Opc == AMDGPU::V_PERMLANEX16_B32_gfx10) {
1118     auto FIN = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers);
1119     auto BCN = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers);
1120     unsigned FI = !!(MI->getOperand(FIN).getImm() & SISrcMods::OP_SEL_0);
1121     unsigned BC = !!(MI->getOperand(BCN).getImm() & SISrcMods::OP_SEL_0);
1122     if (FI || BC)
1123       O << " op_sel:[" << FI << ',' << BC << ']';
1124     return;
1125   }
1126 
1127   printPackedModifier(MI, " op_sel:[", SISrcMods::OP_SEL_0, O);
1128 }
1129 
1130 void AMDGPUInstPrinter::printOpSelHi(const MCInst *MI, unsigned OpNo,
1131                                      const MCSubtargetInfo &STI,
1132                                      raw_ostream &O) {
1133   printPackedModifier(MI, " op_sel_hi:[", SISrcMods::OP_SEL_1, O);
1134 }
1135 
1136 void AMDGPUInstPrinter::printNegLo(const MCInst *MI, unsigned OpNo,
1137                                    const MCSubtargetInfo &STI,
1138                                    raw_ostream &O) {
1139   printPackedModifier(MI, " neg_lo:[", SISrcMods::NEG, O);
1140 }
1141 
1142 void AMDGPUInstPrinter::printNegHi(const MCInst *MI, unsigned OpNo,
1143                                    const MCSubtargetInfo &STI,
1144                                    raw_ostream &O) {
1145   printPackedModifier(MI, " neg_hi:[", SISrcMods::NEG_HI, O);
1146 }
1147 
1148 void AMDGPUInstPrinter::printInterpSlot(const MCInst *MI, unsigned OpNum,
1149                                         const MCSubtargetInfo &STI,
1150                                         raw_ostream &O) {
1151   unsigned Imm = MI->getOperand(OpNum).getImm();
1152   switch (Imm) {
1153   case 0:
1154     O << "p10";
1155     break;
1156   case 1:
1157     O << "p20";
1158     break;
1159   case 2:
1160     O << "p0";
1161     break;
1162   default:
1163     O << "invalid_param_" << Imm;
1164   }
1165 }
1166 
1167 void AMDGPUInstPrinter::printInterpAttr(const MCInst *MI, unsigned OpNum,
1168                                         const MCSubtargetInfo &STI,
1169                                         raw_ostream &O) {
1170   unsigned Attr = MI->getOperand(OpNum).getImm();
1171   O << "attr" << Attr;
1172 }
1173 
1174 void AMDGPUInstPrinter::printInterpAttrChan(const MCInst *MI, unsigned OpNum,
1175                                         const MCSubtargetInfo &STI,
1176                                         raw_ostream &O) {
1177   unsigned Chan = MI->getOperand(OpNum).getImm();
1178   O << '.' << "xyzw"[Chan & 0x3];
1179 }
1180 
1181 void AMDGPUInstPrinter::printVGPRIndexMode(const MCInst *MI, unsigned OpNo,
1182                                            const MCSubtargetInfo &STI,
1183                                            raw_ostream &O) {
1184   using namespace llvm::AMDGPU::VGPRIndexMode;
1185   unsigned Val = MI->getOperand(OpNo).getImm();
1186 
1187   if ((Val & ~ENABLE_MASK) != 0) {
1188     O << formatHex(static_cast<uint64_t>(Val));
1189   } else {
1190     O << "gpr_idx(";
1191     bool NeedComma = false;
1192     for (unsigned ModeId = ID_MIN; ModeId <= ID_MAX; ++ModeId) {
1193       if (Val & (1 << ModeId)) {
1194         if (NeedComma)
1195           O << ',';
1196         O << IdSymbolic[ModeId];
1197         NeedComma = true;
1198       }
1199     }
1200     O << ')';
1201   }
1202 }
1203 
1204 void AMDGPUInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo,
1205                                         const MCSubtargetInfo &STI,
1206                                         raw_ostream &O) {
1207   printOperand(MI, OpNo, STI, O);
1208   O  << ", ";
1209   printOperand(MI, OpNo + 1, STI, O);
1210 }
1211 
1212 void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
1213                                    raw_ostream &O, StringRef Asm,
1214                                    StringRef Default) {
1215   const MCOperand &Op = MI->getOperand(OpNo);
1216   assert(Op.isImm());
1217   if (Op.getImm() == 1) {
1218     O << Asm;
1219   } else {
1220     O << Default;
1221   }
1222 }
1223 
1224 void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
1225                                    raw_ostream &O, char Asm) {
1226   const MCOperand &Op = MI->getOperand(OpNo);
1227   assert(Op.isImm());
1228   if (Op.getImm() == 1)
1229     O << Asm;
1230 }
1231 
1232 void AMDGPUInstPrinter::printHigh(const MCInst *MI, unsigned OpNo,
1233                                   const MCSubtargetInfo &STI,
1234                                   raw_ostream &O) {
1235   printNamedBit(MI, OpNo, O, "high");
1236 }
1237 
1238 void AMDGPUInstPrinter::printClampSI(const MCInst *MI, unsigned OpNo,
1239                                      const MCSubtargetInfo &STI,
1240                                      raw_ostream &O) {
1241   printNamedBit(MI, OpNo, O, "clamp");
1242 }
1243 
1244 void AMDGPUInstPrinter::printOModSI(const MCInst *MI, unsigned OpNo,
1245                                     const MCSubtargetInfo &STI,
1246                                     raw_ostream &O) {
1247   int Imm = MI->getOperand(OpNo).getImm();
1248   if (Imm == SIOutMods::MUL2)
1249     O << " mul:2";
1250   else if (Imm == SIOutMods::MUL4)
1251     O << " mul:4";
1252   else if (Imm == SIOutMods::DIV2)
1253     O << " div:2";
1254 }
1255 
1256 void AMDGPUInstPrinter::printSendMsg(const MCInst *MI, unsigned OpNo,
1257                                      const MCSubtargetInfo &STI,
1258                                      raw_ostream &O) {
1259   using namespace llvm::AMDGPU::SendMsg;
1260 
1261   const unsigned Imm16 = MI->getOperand(OpNo).getImm();
1262 
1263   uint16_t MsgId;
1264   uint16_t OpId;
1265   uint16_t StreamId;
1266   decodeMsg(Imm16, MsgId, OpId, StreamId);
1267 
1268   if (isValidMsgId(MsgId, STI) &&
1269       isValidMsgOp(MsgId, OpId, STI) &&
1270       isValidMsgStream(MsgId, OpId, StreamId, STI)) {
1271     O << "sendmsg(" << getMsgName(MsgId);
1272     if (msgRequiresOp(MsgId)) {
1273       O << ", " << getMsgOpName(MsgId, OpId);
1274       if (msgSupportsStream(MsgId, OpId)) {
1275         O << ", " << StreamId;
1276       }
1277     }
1278     O << ')';
1279   } else if (encodeMsg(MsgId, OpId, StreamId) == Imm16) {
1280     O << "sendmsg(" << MsgId << ", " << OpId << ", " << StreamId << ')';
1281   } else {
1282     O << Imm16; // Unknown imm16 code.
1283   }
1284 }
1285 
1286 static void printSwizzleBitmask(const uint16_t AndMask,
1287                                 const uint16_t OrMask,
1288                                 const uint16_t XorMask,
1289                                 raw_ostream &O) {
1290   using namespace llvm::AMDGPU::Swizzle;
1291 
1292   uint16_t Probe0 = ((0            & AndMask) | OrMask) ^ XorMask;
1293   uint16_t Probe1 = ((BITMASK_MASK & AndMask) | OrMask) ^ XorMask;
1294 
1295   O << "\"";
1296 
1297   for (unsigned Mask = 1 << (BITMASK_WIDTH - 1); Mask > 0; Mask >>= 1) {
1298     uint16_t p0 = Probe0 & Mask;
1299     uint16_t p1 = Probe1 & Mask;
1300 
1301     if (p0 == p1) {
1302       if (p0 == 0) {
1303         O << "0";
1304       } else {
1305         O << "1";
1306       }
1307     } else {
1308       if (p0 == 0) {
1309         O << "p";
1310       } else {
1311         O << "i";
1312       }
1313     }
1314   }
1315 
1316   O << "\"";
1317 }
1318 
1319 void AMDGPUInstPrinter::printSwizzle(const MCInst *MI, unsigned OpNo,
1320                                      const MCSubtargetInfo &STI,
1321                                      raw_ostream &O) {
1322   using namespace llvm::AMDGPU::Swizzle;
1323 
1324   uint16_t Imm = MI->getOperand(OpNo).getImm();
1325   if (Imm == 0) {
1326     return;
1327   }
1328 
1329   O << " offset:";
1330 
1331   if ((Imm & QUAD_PERM_ENC_MASK) == QUAD_PERM_ENC) {
1332 
1333     O << "swizzle(" << IdSymbolic[ID_QUAD_PERM];
1334     for (unsigned I = 0; I < LANE_NUM; ++I) {
1335       O << ",";
1336       O << formatDec(Imm & LANE_MASK);
1337       Imm >>= LANE_SHIFT;
1338     }
1339     O << ")";
1340 
1341   } else if ((Imm & BITMASK_PERM_ENC_MASK) == BITMASK_PERM_ENC) {
1342 
1343     uint16_t AndMask = (Imm >> BITMASK_AND_SHIFT) & BITMASK_MASK;
1344     uint16_t OrMask  = (Imm >> BITMASK_OR_SHIFT)  & BITMASK_MASK;
1345     uint16_t XorMask = (Imm >> BITMASK_XOR_SHIFT) & BITMASK_MASK;
1346 
1347     if (AndMask == BITMASK_MAX &&
1348         OrMask == 0 &&
1349         countPopulation(XorMask) == 1) {
1350 
1351       O << "swizzle(" << IdSymbolic[ID_SWAP];
1352       O << ",";
1353       O << formatDec(XorMask);
1354       O << ")";
1355 
1356     } else if (AndMask == BITMASK_MAX &&
1357                OrMask == 0 && XorMask > 0 &&
1358                isPowerOf2_64(XorMask + 1)) {
1359 
1360       O << "swizzle(" << IdSymbolic[ID_REVERSE];
1361       O << ",";
1362       O << formatDec(XorMask + 1);
1363       O << ")";
1364 
1365     } else {
1366 
1367       uint16_t GroupSize = BITMASK_MAX - AndMask + 1;
1368       if (GroupSize > 1 &&
1369           isPowerOf2_64(GroupSize) &&
1370           OrMask < GroupSize &&
1371           XorMask == 0) {
1372 
1373         O << "swizzle(" << IdSymbolic[ID_BROADCAST];
1374         O << ",";
1375         O << formatDec(GroupSize);
1376         O << ",";
1377         O << formatDec(OrMask);
1378         O << ")";
1379 
1380       } else {
1381         O << "swizzle(" << IdSymbolic[ID_BITMASK_PERM];
1382         O << ",";
1383         printSwizzleBitmask(AndMask, OrMask, XorMask, O);
1384         O << ")";
1385       }
1386     }
1387   } else {
1388     printU16ImmDecOperand(MI, OpNo, O);
1389   }
1390 }
1391 
1392 void AMDGPUInstPrinter::printWaitFlag(const MCInst *MI, unsigned OpNo,
1393                                       const MCSubtargetInfo &STI,
1394                                       raw_ostream &O) {
1395   AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(STI.getCPU());
1396 
1397   unsigned SImm16 = MI->getOperand(OpNo).getImm();
1398   unsigned Vmcnt, Expcnt, Lgkmcnt;
1399   decodeWaitcnt(ISA, SImm16, Vmcnt, Expcnt, Lgkmcnt);
1400 
1401   bool NeedSpace = false;
1402 
1403   if (Vmcnt != getVmcntBitMask(ISA)) {
1404     O << "vmcnt(" << Vmcnt << ')';
1405     NeedSpace = true;
1406   }
1407 
1408   if (Expcnt != getExpcntBitMask(ISA)) {
1409     if (NeedSpace)
1410       O << ' ';
1411     O << "expcnt(" << Expcnt << ')';
1412     NeedSpace = true;
1413   }
1414 
1415   if (Lgkmcnt != getLgkmcntBitMask(ISA)) {
1416     if (NeedSpace)
1417       O << ' ';
1418     O << "lgkmcnt(" << Lgkmcnt << ')';
1419   }
1420 }
1421 
1422 void AMDGPUInstPrinter::printHwreg(const MCInst *MI, unsigned OpNo,
1423                                    const MCSubtargetInfo &STI, raw_ostream &O) {
1424   unsigned Id;
1425   unsigned Offset;
1426   unsigned Width;
1427 
1428   using namespace llvm::AMDGPU::Hwreg;
1429   unsigned Val = MI->getOperand(OpNo).getImm();
1430   decodeHwreg(Val, Id, Offset, Width);
1431   StringRef HwRegName = getHwreg(Id, STI);
1432 
1433   O << "hwreg(";
1434   if (!HwRegName.empty()) {
1435     O << HwRegName;
1436   } else {
1437     O << Id;
1438   }
1439   if (Width != WIDTH_DEFAULT_ || Offset != OFFSET_DEFAULT_) {
1440     O << ", " << Offset << ", " << Width;
1441   }
1442   O << ')';
1443 }
1444 
1445 void AMDGPUInstPrinter::printEndpgm(const MCInst *MI, unsigned OpNo,
1446                                     const MCSubtargetInfo &STI,
1447                                     raw_ostream &O) {
1448   uint16_t Imm = MI->getOperand(OpNo).getImm();
1449   if (Imm == 0) {
1450     return;
1451   }
1452 
1453   O << ' ' << formatDec(Imm);
1454 }
1455 
1456 #include "AMDGPUGenAsmWriter.inc"
1457 
1458 void R600InstPrinter::printInst(const MCInst *MI, uint64_t Address,
1459                                 StringRef Annot, const MCSubtargetInfo &STI,
1460                                 raw_ostream &O) {
1461   O.flush();
1462   printInstruction(MI, Address, O);
1463   printAnnotation(O, Annot);
1464 }
1465 
1466 void R600InstPrinter::printAbs(const MCInst *MI, unsigned OpNo,
1467                                raw_ostream &O) {
1468   AMDGPUInstPrinter::printIfSet(MI, OpNo, O, '|');
1469 }
1470 
1471 void R600InstPrinter::printBankSwizzle(const MCInst *MI, unsigned OpNo,
1472                                        raw_ostream &O) {
1473   int BankSwizzle = MI->getOperand(OpNo).getImm();
1474   switch (BankSwizzle) {
1475   case 1:
1476     O << "BS:VEC_021/SCL_122";
1477     break;
1478   case 2:
1479     O << "BS:VEC_120/SCL_212";
1480     break;
1481   case 3:
1482     O << "BS:VEC_102/SCL_221";
1483     break;
1484   case 4:
1485     O << "BS:VEC_201";
1486     break;
1487   case 5:
1488     O << "BS:VEC_210";
1489     break;
1490   default:
1491     break;
1492   }
1493 }
1494 
1495 void R600InstPrinter::printClamp(const MCInst *MI, unsigned OpNo,
1496                                  raw_ostream &O) {
1497   AMDGPUInstPrinter::printIfSet(MI, OpNo, O, "_SAT");
1498 }
1499 
1500 void R600InstPrinter::printCT(const MCInst *MI, unsigned OpNo,
1501                                 raw_ostream &O) {
1502   unsigned CT = MI->getOperand(OpNo).getImm();
1503   switch (CT) {
1504   case 0:
1505     O << 'U';
1506     break;
1507   case 1:
1508     O << 'N';
1509     break;
1510   default:
1511     break;
1512   }
1513 }
1514 
1515 void R600InstPrinter::printKCache(const MCInst *MI, unsigned OpNo,
1516                                   raw_ostream &O) {
1517   int KCacheMode = MI->getOperand(OpNo).getImm();
1518   if (KCacheMode > 0) {
1519     int KCacheBank = MI->getOperand(OpNo - 2).getImm();
1520     O << "CB" << KCacheBank << ':';
1521     int KCacheAddr = MI->getOperand(OpNo + 2).getImm();
1522     int LineSize = (KCacheMode == 1) ? 16 : 32;
1523     O << KCacheAddr * 16 << '-' << KCacheAddr * 16 + LineSize;
1524   }
1525 }
1526 
1527 void R600InstPrinter::printLast(const MCInst *MI, unsigned OpNo,
1528                                 raw_ostream &O) {
1529   AMDGPUInstPrinter::printIfSet(MI, OpNo, O, "*", " ");
1530 }
1531 
1532 void R600InstPrinter::printLiteral(const MCInst *MI, unsigned OpNo,
1533                                    raw_ostream &O) {
1534   const MCOperand &Op = MI->getOperand(OpNo);
1535   assert(Op.isImm() || Op.isExpr());
1536   if (Op.isImm()) {
1537     int64_t Imm = Op.getImm();
1538     O << Imm << '(' << BitsToFloat(Imm) << ')';
1539   }
1540   if (Op.isExpr()) {
1541     Op.getExpr()->print(O << '@', &MAI);
1542   }
1543 }
1544 
1545 void R600InstPrinter::printNeg(const MCInst *MI, unsigned OpNo,
1546                                raw_ostream &O) {
1547   AMDGPUInstPrinter::printIfSet(MI, OpNo, O, '-');
1548 }
1549 
1550 void R600InstPrinter::printOMOD(const MCInst *MI, unsigned OpNo,
1551                                 raw_ostream &O) {
1552   switch (MI->getOperand(OpNo).getImm()) {
1553   default: break;
1554   case 1:
1555     O << " * 2.0";
1556     break;
1557   case 2:
1558     O << " * 4.0";
1559     break;
1560   case 3:
1561     O << " / 2.0";
1562     break;
1563   }
1564 }
1565 
1566 void R600InstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo,
1567                                       raw_ostream &O) {
1568   printOperand(MI, OpNo, O);
1569   O  << ", ";
1570   printOperand(MI, OpNo + 1, O);
1571 }
1572 
1573 void R600InstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
1574                                    raw_ostream &O) {
1575   if (OpNo >= MI->getNumOperands()) {
1576     O << "/*Missing OP" << OpNo << "*/";
1577     return;
1578   }
1579 
1580   const MCOperand &Op = MI->getOperand(OpNo);
1581   if (Op.isReg()) {
1582     switch (Op.getReg()) {
1583     // This is the default predicate state, so we don't need to print it.
1584     case R600::PRED_SEL_OFF:
1585       break;
1586 
1587     default:
1588       O << getRegisterName(Op.getReg());
1589       break;
1590     }
1591   } else if (Op.isImm()) {
1592       O << Op.getImm();
1593   } else if (Op.isDFPImm()) {
1594     // We special case 0.0 because otherwise it will be printed as an integer.
1595     if (Op.getDFPImm() == 0.0)
1596       O << "0.0";
1597     else {
1598       O << bit_cast<double>(Op.getDFPImm());
1599     }
1600   } else if (Op.isExpr()) {
1601     const MCExpr *Exp = Op.getExpr();
1602     Exp->print(O, &MAI);
1603   } else {
1604     O << "/*INV_OP*/";
1605   }
1606 }
1607 
1608 void R600InstPrinter::printRel(const MCInst *MI, unsigned OpNo,
1609                                raw_ostream &O) {
1610   AMDGPUInstPrinter::printIfSet(MI, OpNo, O, '+');
1611 }
1612 
1613 void R600InstPrinter::printRSel(const MCInst *MI, unsigned OpNo,
1614                                   raw_ostream &O) {
1615   unsigned Sel = MI->getOperand(OpNo).getImm();
1616   switch (Sel) {
1617   case 0:
1618     O << 'X';
1619     break;
1620   case 1:
1621     O << 'Y';
1622     break;
1623   case 2:
1624     O << 'Z';
1625     break;
1626   case 3:
1627     O << 'W';
1628     break;
1629   case 4:
1630     O << '0';
1631     break;
1632   case 5:
1633     O << '1';
1634     break;
1635   case 7:
1636     O << '_';
1637     break;
1638   default:
1639     break;
1640   }
1641 }
1642 
1643 void R600InstPrinter::printUpdateExecMask(const MCInst *MI, unsigned OpNo,
1644                                           raw_ostream &O) {
1645   AMDGPUInstPrinter::printIfSet(MI, OpNo, O, "ExecMask,");
1646 }
1647 
1648 void R600InstPrinter::printUpdatePred(const MCInst *MI, unsigned OpNo,
1649                                       raw_ostream &O) {
1650   AMDGPUInstPrinter::printIfSet(MI, OpNo, O, "Pred,");
1651 }
1652 
1653 void R600InstPrinter::printWrite(const MCInst *MI, unsigned OpNo,
1654                                  raw_ostream &O) {
1655   const MCOperand &Op = MI->getOperand(OpNo);
1656   if (Op.getImm() == 0) {
1657     O << " (MASKED)";
1658   }
1659 }
1660 
1661 #include "R600GenAsmWriter.inc"
1662