1 //===-- AMDGPUInstPrinter.cpp - AMDGPU MC Inst -> ASM ---------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 // \file
8 //===----------------------------------------------------------------------===//
9 
10 #include "AMDGPUInstPrinter.h"
11 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
12 #include "SIDefines.h"
13 #include "Utils/AMDGPUAsmUtils.h"
14 #include "Utils/AMDGPUBaseInfo.h"
15 #include "llvm/MC/MCExpr.h"
16 #include "llvm/MC/MCInst.h"
17 #include "llvm/MC/MCInstrDesc.h"
18 #include "llvm/MC/MCInstrInfo.h"
19 #include "llvm/MC/MCRegisterInfo.h"
20 #include "llvm/MC/MCSubtargetInfo.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/MathExtras.h"
24 #include "llvm/Support/raw_ostream.h"
25 #include <cassert>
26 
27 using namespace llvm;
28 using namespace llvm::AMDGPU;
29 
30 static cl::opt<bool> Keep16BitSuffixes(
31   "amdgpu-keep-16-bit-reg-suffixes",
32   cl::desc("Keep .l and .h suffixes in asm for debugging purposes"),
33   cl::init(false),
34   cl::ReallyHidden);
35 
36 void AMDGPUInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
37   // FIXME: The current implementation of
38   // AsmParser::parseRegisterOrRegisterNumber in MC implies we either emit this
39   // as an integer or we provide a name which represents a physical register.
40   // For CFI instructions we really want to emit a name for the DWARF register
41   // instead, because there may be multiple DWARF registers corresponding to a
42   // single physical register. One case where this problem manifests is with
43   // wave32/wave64 where using the physical register name is ambiguous: if we
44   // write e.g. `.cfi_undefined v0` we lose information about the wavefront
45   // size which we need to encode the register in the final DWARF. Ideally we
46   // would extend MC to support parsing DWARF register names so we could do
47   // something like `.cfi_undefined dwarf_wave32_v0`. For now we just live with
48   // non-pretty DWARF register names in assembly text.
49   OS << RegNo;
50 }
51 
52 void AMDGPUInstPrinter::printInst(const MCInst *MI, uint64_t Address,
53                                   StringRef Annot, const MCSubtargetInfo &STI,
54                                   raw_ostream &OS) {
55   OS.flush();
56   printInstruction(MI, Address, STI, OS);
57   printAnnotation(OS, Annot);
58 }
59 
60 void AMDGPUInstPrinter::printU4ImmOperand(const MCInst *MI, unsigned OpNo,
61                                           const MCSubtargetInfo &STI,
62                                           raw_ostream &O) {
63   O << formatHex(MI->getOperand(OpNo).getImm() & 0xf);
64 }
65 
66 void AMDGPUInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo,
67                                           raw_ostream &O) {
68   O << formatHex(MI->getOperand(OpNo).getImm() & 0xff);
69 }
70 
71 void AMDGPUInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
72                                            const MCSubtargetInfo &STI,
73                                            raw_ostream &O) {
74   // It's possible to end up with a 32-bit literal used with a 16-bit operand
75   // with ignored high bits. Print as 32-bit anyway in that case.
76   int64_t Imm = MI->getOperand(OpNo).getImm();
77   if (isInt<16>(Imm) || isUInt<16>(Imm))
78     O << formatHex(static_cast<uint64_t>(Imm & 0xffff));
79   else
80     printU32ImmOperand(MI, OpNo, STI, O);
81 }
82 
83 void AMDGPUInstPrinter::printU4ImmDecOperand(const MCInst *MI, unsigned OpNo,
84                                              raw_ostream &O) {
85   O << formatDec(MI->getOperand(OpNo).getImm() & 0xf);
86 }
87 
88 void AMDGPUInstPrinter::printU8ImmDecOperand(const MCInst *MI, unsigned OpNo,
89                                              raw_ostream &O) {
90   O << formatDec(MI->getOperand(OpNo).getImm() & 0xff);
91 }
92 
93 void AMDGPUInstPrinter::printU16ImmDecOperand(const MCInst *MI, unsigned OpNo,
94                                               raw_ostream &O) {
95   O << formatDec(MI->getOperand(OpNo).getImm() & 0xffff);
96 }
97 
98 void AMDGPUInstPrinter::printU32ImmOperand(const MCInst *MI, unsigned OpNo,
99                                            const MCSubtargetInfo &STI,
100                                            raw_ostream &O) {
101   O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff);
102 }
103 
104 void AMDGPUInstPrinter::printNamedBit(const MCInst *MI, unsigned OpNo,
105                                       raw_ostream &O, StringRef BitName) {
106   if (MI->getOperand(OpNo).getImm()) {
107     O << ' ' << BitName;
108   }
109 }
110 
111 void AMDGPUInstPrinter::printOffen(const MCInst *MI, unsigned OpNo,
112                                    raw_ostream &O) {
113   printNamedBit(MI, OpNo, O, "offen");
114 }
115 
116 void AMDGPUInstPrinter::printIdxen(const MCInst *MI, unsigned OpNo,
117                                    raw_ostream &O) {
118   printNamedBit(MI, OpNo, O, "idxen");
119 }
120 
121 void AMDGPUInstPrinter::printAddr64(const MCInst *MI, unsigned OpNo,
122                                     raw_ostream &O) {
123   printNamedBit(MI, OpNo, O, "addr64");
124 }
125 
126 void AMDGPUInstPrinter::printMBUFOffset(const MCInst *MI, unsigned OpNo,
127                                         raw_ostream &O) {
128   if (MI->getOperand(OpNo).getImm()) {
129     O << " offset:";
130     printU16ImmDecOperand(MI, OpNo, O);
131   }
132 }
133 
134 void AMDGPUInstPrinter::printOffset(const MCInst *MI, unsigned OpNo,
135                                     const MCSubtargetInfo &STI,
136                                     raw_ostream &O) {
137   uint16_t Imm = MI->getOperand(OpNo).getImm();
138   if (Imm != 0) {
139     O << ((OpNo == 0)? "offset:" : " offset:");
140     printU16ImmDecOperand(MI, OpNo, O);
141   }
142 }
143 
144 void AMDGPUInstPrinter::printFlatOffset(const MCInst *MI, unsigned OpNo,
145                                         const MCSubtargetInfo &STI,
146                                         raw_ostream &O) {
147   uint16_t Imm = MI->getOperand(OpNo).getImm();
148   if (Imm != 0) {
149     O << ((OpNo == 0)? "offset:" : " offset:");
150 
151     const MCInstrDesc &Desc = MII.get(MI->getOpcode());
152     bool IsFlatSeg = !(Desc.TSFlags & SIInstrFlags::IsNonFlatSeg);
153 
154     if (IsFlatSeg) { // Unsigned offset
155       printU16ImmDecOperand(MI, OpNo, O);
156     } else {         // Signed offset
157       if (AMDGPU::isGFX10(STI)) {
158         O << formatDec(SignExtend32<12>(MI->getOperand(OpNo).getImm()));
159       } else {
160         O << formatDec(SignExtend32<13>(MI->getOperand(OpNo).getImm()));
161       }
162     }
163   }
164 }
165 
166 void AMDGPUInstPrinter::printOffset0(const MCInst *MI, unsigned OpNo,
167                                      const MCSubtargetInfo &STI,
168                                      raw_ostream &O) {
169   if (MI->getOperand(OpNo).getImm()) {
170     O << " offset0:";
171     printU8ImmDecOperand(MI, OpNo, O);
172   }
173 }
174 
175 void AMDGPUInstPrinter::printOffset1(const MCInst *MI, unsigned OpNo,
176                                      const MCSubtargetInfo &STI,
177                                      raw_ostream &O) {
178   if (MI->getOperand(OpNo).getImm()) {
179     O << " offset1:";
180     printU8ImmDecOperand(MI, OpNo, O);
181   }
182 }
183 
184 void AMDGPUInstPrinter::printSMRDOffset8(const MCInst *MI, unsigned OpNo,
185                                         const MCSubtargetInfo &STI,
186                                         raw_ostream &O) {
187   printU32ImmOperand(MI, OpNo, STI, O);
188 }
189 
190 void AMDGPUInstPrinter::printSMEMOffset(const MCInst *MI, unsigned OpNo,
191                                         const MCSubtargetInfo &STI,
192                                         raw_ostream &O) {
193   O << formatHex(MI->getOperand(OpNo).getImm());
194 }
195 
196 void AMDGPUInstPrinter::printSMRDLiteralOffset(const MCInst *MI, unsigned OpNo,
197                                                const MCSubtargetInfo &STI,
198                                                raw_ostream &O) {
199   printU32ImmOperand(MI, OpNo, STI, O);
200 }
201 
202 void AMDGPUInstPrinter::printGDS(const MCInst *MI, unsigned OpNo,
203                                  const MCSubtargetInfo &STI, raw_ostream &O) {
204   printNamedBit(MI, OpNo, O, "gds");
205 }
206 
207 void AMDGPUInstPrinter::printDLC(const MCInst *MI, unsigned OpNo,
208                                  const MCSubtargetInfo &STI, raw_ostream &O) {
209   if (AMDGPU::isGFX10(STI))
210     printNamedBit(MI, OpNo, O, "dlc");
211 }
212 
213 void AMDGPUInstPrinter::printGLC(const MCInst *MI, unsigned OpNo,
214                                  const MCSubtargetInfo &STI, raw_ostream &O) {
215   printNamedBit(MI, OpNo, O, "glc");
216 }
217 
218 void AMDGPUInstPrinter::printSLC(const MCInst *MI, unsigned OpNo,
219                                  const MCSubtargetInfo &STI, raw_ostream &O) {
220   printNamedBit(MI, OpNo, O, "slc");
221 }
222 
223 void AMDGPUInstPrinter::printSWZ(const MCInst *MI, unsigned OpNo,
224                                  const MCSubtargetInfo &STI, raw_ostream &O) {
225 }
226 
227 void AMDGPUInstPrinter::printTFE(const MCInst *MI, unsigned OpNo,
228                                  const MCSubtargetInfo &STI, raw_ostream &O) {
229   printNamedBit(MI, OpNo, O, "tfe");
230 }
231 
232 void AMDGPUInstPrinter::printDMask(const MCInst *MI, unsigned OpNo,
233                                    const MCSubtargetInfo &STI, raw_ostream &O) {
234   if (MI->getOperand(OpNo).getImm()) {
235     O << " dmask:";
236     printU16ImmOperand(MI, OpNo, STI, O);
237   }
238 }
239 
240 void AMDGPUInstPrinter::printDim(const MCInst *MI, unsigned OpNo,
241                                  const MCSubtargetInfo &STI, raw_ostream &O) {
242   unsigned Dim = MI->getOperand(OpNo).getImm();
243   O << " dim:SQ_RSRC_IMG_";
244 
245   const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfoByEncoding(Dim);
246   if (DimInfo)
247     O << DimInfo->AsmSuffix;
248   else
249     O << Dim;
250 }
251 
252 void AMDGPUInstPrinter::printUNorm(const MCInst *MI, unsigned OpNo,
253                                    const MCSubtargetInfo &STI, raw_ostream &O) {
254   printNamedBit(MI, OpNo, O, "unorm");
255 }
256 
257 void AMDGPUInstPrinter::printDA(const MCInst *MI, unsigned OpNo,
258                                 const MCSubtargetInfo &STI, raw_ostream &O) {
259   printNamedBit(MI, OpNo, O, "da");
260 }
261 
262 void AMDGPUInstPrinter::printR128A16(const MCInst *MI, unsigned OpNo,
263                                   const MCSubtargetInfo &STI, raw_ostream &O) {
264   if (STI.hasFeature(AMDGPU::FeatureR128A16))
265     printNamedBit(MI, OpNo, O, "a16");
266   else
267     printNamedBit(MI, OpNo, O, "r128");
268 }
269 
270 void AMDGPUInstPrinter::printGFX10A16(const MCInst *MI, unsigned OpNo,
271                                   const MCSubtargetInfo &STI, raw_ostream &O) {
272   printNamedBit(MI, OpNo, O, "a16");
273 }
274 
275 void AMDGPUInstPrinter::printLWE(const MCInst *MI, unsigned OpNo,
276                                  const MCSubtargetInfo &STI, raw_ostream &O) {
277   printNamedBit(MI, OpNo, O, "lwe");
278 }
279 
280 void AMDGPUInstPrinter::printD16(const MCInst *MI, unsigned OpNo,
281                                  const MCSubtargetInfo &STI, raw_ostream &O) {
282   printNamedBit(MI, OpNo, O, "d16");
283 }
284 
285 void AMDGPUInstPrinter::printExpCompr(const MCInst *MI, unsigned OpNo,
286                                       const MCSubtargetInfo &STI,
287                                       raw_ostream &O) {
288   printNamedBit(MI, OpNo, O, "compr");
289 }
290 
291 void AMDGPUInstPrinter::printExpVM(const MCInst *MI, unsigned OpNo,
292                                    const MCSubtargetInfo &STI,
293                                    raw_ostream &O) {
294   printNamedBit(MI, OpNo, O, "vm");
295 }
296 
297 void AMDGPUInstPrinter::printFORMAT(const MCInst *MI, unsigned OpNo,
298                                     const MCSubtargetInfo &STI,
299                                     raw_ostream &O) {
300 }
301 
302 void AMDGPUInstPrinter::printSymbolicFormat(const MCInst *MI,
303                                             const MCSubtargetInfo &STI,
304                                             raw_ostream &O) {
305   using namespace llvm::AMDGPU::MTBUFFormat;
306 
307   int OpNo =
308     AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::format);
309   assert(OpNo != -1);
310 
311   unsigned Val = MI->getOperand(OpNo).getImm();
312   if (AMDGPU::isGFX10(STI)) {
313     if (Val == UFMT_DEFAULT)
314       return;
315     if (isValidUnifiedFormat(Val)) {
316       O << " format:[" << getUnifiedFormatName(Val) << ']';
317     } else {
318       O << " format:" << Val;
319     }
320   } else {
321     if (Val == DFMT_NFMT_DEFAULT)
322       return;
323     if (isValidDfmtNfmt(Val, STI)) {
324       unsigned Dfmt;
325       unsigned Nfmt;
326       decodeDfmtNfmt(Val, Dfmt, Nfmt);
327       O << " format:[";
328       if (Dfmt != DFMT_DEFAULT) {
329         O << getDfmtName(Dfmt);
330         if (Nfmt != NFMT_DEFAULT) {
331           O << ',';
332         }
333       }
334       if (Nfmt != NFMT_DEFAULT) {
335         O << getNfmtName(Nfmt, STI);
336       }
337       O << ']';
338     } else {
339       O << " format:" << Val;
340     }
341   }
342 }
343 
344 void AMDGPUInstPrinter::printRegOperand(unsigned RegNo, raw_ostream &O,
345                                         const MCRegisterInfo &MRI) {
346 #if !defined(NDEBUG)
347   switch (RegNo) {
348   case AMDGPU::FP_REG:
349   case AMDGPU::SP_REG:
350   case AMDGPU::PRIVATE_RSRC_REG:
351     llvm_unreachable("pseudo-register should not ever be emitted");
352   case AMDGPU::SCC:
353     llvm_unreachable("pseudo scc should not ever be emitted");
354   default:
355     break;
356   }
357 #endif
358 
359   StringRef RegName(getRegisterName(RegNo));
360   if (!Keep16BitSuffixes)
361     if (!RegName.consume_back(".l"))
362       RegName.consume_back(".h");
363 
364   O << RegName;
365 }
366 
367 void AMDGPUInstPrinter::printVOPDst(const MCInst *MI, unsigned OpNo,
368                                     const MCSubtargetInfo &STI, raw_ostream &O) {
369   if (OpNo == 0) {
370     if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::VOP3)
371       O << "_e64 ";
372     else if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::DPP)
373       O << "_dpp ";
374     else if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::SDWA)
375       O << "_sdwa ";
376     else
377       O << "_e32 ";
378   }
379 
380   printOperand(MI, OpNo, STI, O);
381 
382   // Print default vcc/vcc_lo operand.
383   switch (MI->getOpcode()) {
384   default: break;
385 
386   case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10:
387   case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10:
388   case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10:
389   case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10:
390   case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10:
391   case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10:
392   case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10:
393   case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10:
394   case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10:
395   case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10:
396   case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10:
397   case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10:
398     printDefaultVccOperand(1, STI, O);
399     break;
400   }
401 }
402 
403 void AMDGPUInstPrinter::printVINTRPDst(const MCInst *MI, unsigned OpNo,
404                                        const MCSubtargetInfo &STI, raw_ostream &O) {
405   if (AMDGPU::isSI(STI) || AMDGPU::isCI(STI))
406     O << " ";
407   else
408     O << "_e32 ";
409 
410   printOperand(MI, OpNo, STI, O);
411 }
412 
413 void AMDGPUInstPrinter::printImmediateInt16(uint32_t Imm,
414                                             const MCSubtargetInfo &STI,
415                                             raw_ostream &O) {
416   int16_t SImm = static_cast<int16_t>(Imm);
417   if (isInlinableIntLiteral(SImm)) {
418     O << SImm;
419   } else {
420     uint64_t Imm16 = static_cast<uint16_t>(Imm);
421     O << formatHex(Imm16);
422   }
423 }
424 
425 void AMDGPUInstPrinter::printImmediate16(uint32_t Imm,
426                                          const MCSubtargetInfo &STI,
427                                          raw_ostream &O) {
428   int16_t SImm = static_cast<int16_t>(Imm);
429   if (isInlinableIntLiteral(SImm)) {
430     O << SImm;
431     return;
432   }
433 
434   if (Imm == 0x3C00)
435     O<< "1.0";
436   else if (Imm == 0xBC00)
437     O<< "-1.0";
438   else if (Imm == 0x3800)
439     O<< "0.5";
440   else if (Imm == 0xB800)
441     O<< "-0.5";
442   else if (Imm == 0x4000)
443     O<< "2.0";
444   else if (Imm == 0xC000)
445     O<< "-2.0";
446   else if (Imm == 0x4400)
447     O<< "4.0";
448   else if (Imm == 0xC400)
449     O<< "-4.0";
450   else if (Imm == 0x3118 &&
451            STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]) {
452     O << "0.15915494";
453   } else {
454     uint64_t Imm16 = static_cast<uint16_t>(Imm);
455     O << formatHex(Imm16);
456   }
457 }
458 
459 void AMDGPUInstPrinter::printImmediateV216(uint32_t Imm,
460                                            const MCSubtargetInfo &STI,
461                                            raw_ostream &O) {
462   uint16_t Lo16 = static_cast<uint16_t>(Imm);
463   printImmediate16(Lo16, STI, O);
464 }
465 
466 void AMDGPUInstPrinter::printImmediate32(uint32_t Imm,
467                                          const MCSubtargetInfo &STI,
468                                          raw_ostream &O) {
469   int32_t SImm = static_cast<int32_t>(Imm);
470   if (SImm >= -16 && SImm <= 64) {
471     O << SImm;
472     return;
473   }
474 
475   if (Imm == FloatToBits(0.0f))
476     O << "0.0";
477   else if (Imm == FloatToBits(1.0f))
478     O << "1.0";
479   else if (Imm == FloatToBits(-1.0f))
480     O << "-1.0";
481   else if (Imm == FloatToBits(0.5f))
482     O << "0.5";
483   else if (Imm == FloatToBits(-0.5f))
484     O << "-0.5";
485   else if (Imm == FloatToBits(2.0f))
486     O << "2.0";
487   else if (Imm == FloatToBits(-2.0f))
488     O << "-2.0";
489   else if (Imm == FloatToBits(4.0f))
490     O << "4.0";
491   else if (Imm == FloatToBits(-4.0f))
492     O << "-4.0";
493   else if (Imm == 0x3e22f983 &&
494            STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
495     O << "0.15915494";
496   else
497     O << formatHex(static_cast<uint64_t>(Imm));
498 }
499 
500 void AMDGPUInstPrinter::printImmediate64(uint64_t Imm,
501                                          const MCSubtargetInfo &STI,
502                                          raw_ostream &O) {
503   int64_t SImm = static_cast<int64_t>(Imm);
504   if (SImm >= -16 && SImm <= 64) {
505     O << SImm;
506     return;
507   }
508 
509   if (Imm == DoubleToBits(0.0))
510     O << "0.0";
511   else if (Imm == DoubleToBits(1.0))
512     O << "1.0";
513   else if (Imm == DoubleToBits(-1.0))
514     O << "-1.0";
515   else if (Imm == DoubleToBits(0.5))
516     O << "0.5";
517   else if (Imm == DoubleToBits(-0.5))
518     O << "-0.5";
519   else if (Imm == DoubleToBits(2.0))
520     O << "2.0";
521   else if (Imm == DoubleToBits(-2.0))
522     O << "-2.0";
523   else if (Imm == DoubleToBits(4.0))
524     O << "4.0";
525   else if (Imm == DoubleToBits(-4.0))
526     O << "-4.0";
527   else if (Imm == 0x3fc45f306dc9c882 &&
528            STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
529     O << "0.15915494309189532";
530   else {
531     assert(isUInt<32>(Imm) || Imm == 0x3fc45f306dc9c882);
532 
533     // In rare situations, we will have a 32-bit literal in a 64-bit
534     // operand. This is technically allowed for the encoding of s_mov_b64.
535     O << formatHex(static_cast<uint64_t>(Imm));
536   }
537 }
538 
539 void AMDGPUInstPrinter::printBLGP(const MCInst *MI, unsigned OpNo,
540                                   const MCSubtargetInfo &STI,
541                                   raw_ostream &O) {
542   unsigned Imm = MI->getOperand(OpNo).getImm();
543   if (!Imm)
544     return;
545 
546   O << " blgp:" << Imm;
547 }
548 
549 void AMDGPUInstPrinter::printCBSZ(const MCInst *MI, unsigned OpNo,
550                                   const MCSubtargetInfo &STI,
551                                   raw_ostream &O) {
552   unsigned Imm = MI->getOperand(OpNo).getImm();
553   if (!Imm)
554     return;
555 
556   O << " cbsz:" << Imm;
557 }
558 
559 void AMDGPUInstPrinter::printABID(const MCInst *MI, unsigned OpNo,
560                                   const MCSubtargetInfo &STI,
561                                   raw_ostream &O) {
562   unsigned Imm = MI->getOperand(OpNo).getImm();
563   if (!Imm)
564     return;
565 
566   O << " abid:" << Imm;
567 }
568 
569 void AMDGPUInstPrinter::printDefaultVccOperand(unsigned OpNo,
570                                                const MCSubtargetInfo &STI,
571                                                raw_ostream &O) {
572   if (OpNo > 0)
573     O << ", ";
574   printRegOperand(STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ?
575                   AMDGPU::VCC : AMDGPU::VCC_LO, O, MRI);
576   if (OpNo == 0)
577     O << ", ";
578 }
579 
580 void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
581                                      const MCSubtargetInfo &STI,
582                                      raw_ostream &O) {
583   // Print default vcc/vcc_lo operand of VOPC.
584   const MCInstrDesc &Desc = MII.get(MI->getOpcode());
585   if (OpNo == 0 && (Desc.TSFlags & SIInstrFlags::VOPC) &&
586       (Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC) ||
587        Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC_LO)))
588     printDefaultVccOperand(OpNo, STI, O);
589 
590   if (OpNo >= MI->getNumOperands()) {
591     O << "/*Missing OP" << OpNo << "*/";
592     return;
593   }
594 
595   const MCOperand &Op = MI->getOperand(OpNo);
596   if (Op.isReg()) {
597     printRegOperand(Op.getReg(), O, MRI);
598   } else if (Op.isImm()) {
599     const uint8_t OpTy = Desc.OpInfo[OpNo].OperandType;
600     switch (OpTy) {
601     case AMDGPU::OPERAND_REG_IMM_INT32:
602     case AMDGPU::OPERAND_REG_IMM_FP32:
603     case AMDGPU::OPERAND_REG_INLINE_C_INT32:
604     case AMDGPU::OPERAND_REG_INLINE_C_FP32:
605     case AMDGPU::OPERAND_REG_INLINE_AC_INT32:
606     case AMDGPU::OPERAND_REG_INLINE_AC_FP32:
607     case MCOI::OPERAND_IMMEDIATE:
608       printImmediate32(Op.getImm(), STI, O);
609       break;
610     case AMDGPU::OPERAND_REG_IMM_INT64:
611     case AMDGPU::OPERAND_REG_IMM_FP64:
612     case AMDGPU::OPERAND_REG_INLINE_C_INT64:
613     case AMDGPU::OPERAND_REG_INLINE_C_FP64:
614       printImmediate64(Op.getImm(), STI, O);
615       break;
616     case AMDGPU::OPERAND_REG_INLINE_C_INT16:
617     case AMDGPU::OPERAND_REG_INLINE_AC_INT16:
618     case AMDGPU::OPERAND_REG_IMM_INT16:
619       printImmediateInt16(Op.getImm(), STI, O);
620       break;
621     case AMDGPU::OPERAND_REG_INLINE_C_FP16:
622     case AMDGPU::OPERAND_REG_INLINE_AC_FP16:
623     case AMDGPU::OPERAND_REG_IMM_FP16:
624       printImmediate16(Op.getImm(), STI, O);
625       break;
626     case AMDGPU::OPERAND_REG_IMM_V2INT16:
627     case AMDGPU::OPERAND_REG_IMM_V2FP16:
628       if (!isUInt<16>(Op.getImm()) &&
629           STI.getFeatureBits()[AMDGPU::FeatureVOP3Literal]) {
630         printImmediate32(Op.getImm(), STI, O);
631         break;
632       }
633 
634       //  Deal with 16-bit FP inline immediates not working.
635       if (OpTy == AMDGPU::OPERAND_REG_IMM_V2FP16) {
636         printImmediate16(static_cast<uint16_t>(Op.getImm()), STI, O);
637         break;
638       }
639       LLVM_FALLTHROUGH;
640     case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
641     case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:
642       printImmediateInt16(static_cast<uint16_t>(Op.getImm()), STI, O);
643       break;
644     case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
645     case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16:
646       printImmediateV216(Op.getImm(), STI, O);
647       break;
648     case MCOI::OPERAND_UNKNOWN:
649     case MCOI::OPERAND_PCREL:
650       O << formatDec(Op.getImm());
651       break;
652     case MCOI::OPERAND_REGISTER:
653       // FIXME: This should be removed and handled somewhere else. Seems to come
654       // from a disassembler bug.
655       O << "/*invalid immediate*/";
656       break;
657     default:
658       // We hit this for the immediate instruction bits that don't yet have a
659       // custom printer.
660       llvm_unreachable("unexpected immediate operand type");
661     }
662   } else if (Op.isFPImm()) {
663     // We special case 0.0 because otherwise it will be printed as an integer.
664     if (Op.getFPImm() == 0.0)
665       O << "0.0";
666     else {
667       const MCInstrDesc &Desc = MII.get(MI->getOpcode());
668       int RCID = Desc.OpInfo[OpNo].RegClass;
669       unsigned RCBits = AMDGPU::getRegBitWidth(MRI.getRegClass(RCID));
670       if (RCBits == 32)
671         printImmediate32(FloatToBits(Op.getFPImm()), STI, O);
672       else if (RCBits == 64)
673         printImmediate64(DoubleToBits(Op.getFPImm()), STI, O);
674       else
675         llvm_unreachable("Invalid register class size");
676     }
677   } else if (Op.isExpr()) {
678     const MCExpr *Exp = Op.getExpr();
679     Exp->print(O, &MAI);
680   } else {
681     O << "/*INV_OP*/";
682   }
683 
684   // Print default vcc/vcc_lo operand of v_cndmask_b32_e32.
685   switch (MI->getOpcode()) {
686   default: break;
687 
688   case AMDGPU::V_CNDMASK_B32_e32_gfx10:
689   case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10:
690   case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10:
691   case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10:
692   case AMDGPU::V_CNDMASK_B32_dpp_gfx10:
693   case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10:
694   case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10:
695   case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10:
696   case AMDGPU::V_CNDMASK_B32_dpp8_gfx10:
697   case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10:
698   case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10:
699   case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10:
700 
701   case AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7:
702   case AMDGPU::V_CNDMASK_B32_e32_vi:
703     if ((int)OpNo == AMDGPU::getNamedOperandIdx(MI->getOpcode(),
704                                                 AMDGPU::OpName::src1))
705       printDefaultVccOperand(OpNo, STI, O);
706     break;
707   }
708 
709   if (Desc.TSFlags & SIInstrFlags::MTBUF) {
710     int SOffsetIdx =
711       AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::soffset);
712     assert(SOffsetIdx != -1);
713     if ((int)OpNo == SOffsetIdx)
714       printSymbolicFormat(MI, STI, O);
715   }
716 }
717 
718 void AMDGPUInstPrinter::printOperandAndFPInputMods(const MCInst *MI,
719                                                    unsigned OpNo,
720                                                    const MCSubtargetInfo &STI,
721                                                    raw_ostream &O) {
722   unsigned InputModifiers = MI->getOperand(OpNo).getImm();
723 
724   // Use 'neg(...)' instead of '-' to avoid ambiguity.
725   // This is important for integer literals because
726   // -1 is not the same value as neg(1).
727   bool NegMnemo = false;
728 
729   if (InputModifiers & SISrcMods::NEG) {
730     if (OpNo + 1 < MI->getNumOperands() &&
731         (InputModifiers & SISrcMods::ABS) == 0) {
732       const MCOperand &Op = MI->getOperand(OpNo + 1);
733       NegMnemo = Op.isImm() || Op.isFPImm();
734     }
735     if (NegMnemo) {
736       O << "neg(";
737     } else {
738       O << '-';
739     }
740   }
741 
742   if (InputModifiers & SISrcMods::ABS)
743     O << '|';
744   printOperand(MI, OpNo + 1, STI, O);
745   if (InputModifiers & SISrcMods::ABS)
746     O << '|';
747 
748   if (NegMnemo) {
749     O << ')';
750   }
751 }
752 
753 void AMDGPUInstPrinter::printOperandAndIntInputMods(const MCInst *MI,
754                                                     unsigned OpNo,
755                                                     const MCSubtargetInfo &STI,
756                                                     raw_ostream &O) {
757   unsigned InputModifiers = MI->getOperand(OpNo).getImm();
758   if (InputModifiers & SISrcMods::SEXT)
759     O << "sext(";
760   printOperand(MI, OpNo + 1, STI, O);
761   if (InputModifiers & SISrcMods::SEXT)
762     O << ')';
763 
764   // Print default vcc/vcc_lo operand of VOP2b.
765   switch (MI->getOpcode()) {
766   default: break;
767 
768   case AMDGPU::V_CNDMASK_B32_sdwa_gfx10:
769   case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10:
770   case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10:
771   case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10:
772     if ((int)OpNo + 1 == AMDGPU::getNamedOperandIdx(MI->getOpcode(),
773                                                     AMDGPU::OpName::src1))
774       printDefaultVccOperand(OpNo, STI, O);
775     break;
776   }
777 }
778 
779 void AMDGPUInstPrinter::printDPP8(const MCInst *MI, unsigned OpNo,
780                                   const MCSubtargetInfo &STI,
781                                   raw_ostream &O) {
782   if (!AMDGPU::isGFX10(STI))
783     llvm_unreachable("dpp8 is not supported on ASICs earlier than GFX10");
784 
785   unsigned Imm = MI->getOperand(OpNo).getImm();
786   O << " dpp8:[" << formatDec(Imm & 0x7);
787   for (size_t i = 1; i < 8; ++i) {
788     O << ',' << formatDec((Imm >> (3 * i)) & 0x7);
789   }
790   O << ']';
791 }
792 
793 void AMDGPUInstPrinter::printDPPCtrl(const MCInst *MI, unsigned OpNo,
794                                      const MCSubtargetInfo &STI,
795                                      raw_ostream &O) {
796   using namespace AMDGPU::DPP;
797 
798   unsigned Imm = MI->getOperand(OpNo).getImm();
799   if (Imm <= DppCtrl::QUAD_PERM_LAST) {
800     O << " quad_perm:[";
801     O << formatDec(Imm & 0x3)         << ',';
802     O << formatDec((Imm & 0xc)  >> 2) << ',';
803     O << formatDec((Imm & 0x30) >> 4) << ',';
804     O << formatDec((Imm & 0xc0) >> 6) << ']';
805   } else if ((Imm >= DppCtrl::ROW_SHL_FIRST) &&
806              (Imm <= DppCtrl::ROW_SHL_LAST)) {
807     O << " row_shl:";
808     printU4ImmDecOperand(MI, OpNo, O);
809   } else if ((Imm >= DppCtrl::ROW_SHR_FIRST) &&
810              (Imm <= DppCtrl::ROW_SHR_LAST)) {
811     O << " row_shr:";
812     printU4ImmDecOperand(MI, OpNo, O);
813   } else if ((Imm >= DppCtrl::ROW_ROR_FIRST) &&
814              (Imm <= DppCtrl::ROW_ROR_LAST)) {
815     O << " row_ror:";
816     printU4ImmDecOperand(MI, OpNo, O);
817   } else if (Imm == DppCtrl::WAVE_SHL1) {
818     if (!AMDGPU::isVI(STI) && !AMDGPU::isGFX9(STI)) {
819       O << " /* wave_shl is not supported starting from GFX10 */";
820       return;
821     }
822     O << " wave_shl:1";
823   } else if (Imm == DppCtrl::WAVE_ROL1) {
824     if (!AMDGPU::isVI(STI) && !AMDGPU::isGFX9(STI)) {
825       O << " /* wave_rol is not supported starting from GFX10 */";
826       return;
827     }
828     O << " wave_rol:1";
829   } else if (Imm == DppCtrl::WAVE_SHR1) {
830     if (!AMDGPU::isVI(STI) && !AMDGPU::isGFX9(STI)) {
831       O << " /* wave_shr is not supported starting from GFX10 */";
832       return;
833     }
834     O << " wave_shr:1";
835   } else if (Imm == DppCtrl::WAVE_ROR1) {
836     if (!AMDGPU::isVI(STI) && !AMDGPU::isGFX9(STI)) {
837       O << " /* wave_ror is not supported starting from GFX10 */";
838       return;
839     }
840     O << " wave_ror:1";
841   } else if (Imm == DppCtrl::ROW_MIRROR) {
842     O << " row_mirror";
843   } else if (Imm == DppCtrl::ROW_HALF_MIRROR) {
844     O << " row_half_mirror";
845   } else if (Imm == DppCtrl::BCAST15) {
846     if (!AMDGPU::isVI(STI) && !AMDGPU::isGFX9(STI)) {
847       O << " /* row_bcast is not supported starting from GFX10 */";
848       return;
849     }
850     O << " row_bcast:15";
851   } else if (Imm == DppCtrl::BCAST31) {
852     if (!AMDGPU::isVI(STI) && !AMDGPU::isGFX9(STI)) {
853       O << " /* row_bcast is not supported starting from GFX10 */";
854       return;
855     }
856     O << " row_bcast:31";
857   } else if ((Imm >= DppCtrl::ROW_SHARE_FIRST) &&
858              (Imm <= DppCtrl::ROW_SHARE_LAST)) {
859     if (!AMDGPU::isGFX10(STI)) {
860       O << " /* row_share is not supported on ASICs earlier than GFX10 */";
861       return;
862     }
863     O << " row_share:";
864     printU4ImmDecOperand(MI, OpNo, O);
865   } else if ((Imm >= DppCtrl::ROW_XMASK_FIRST) &&
866              (Imm <= DppCtrl::ROW_XMASK_LAST)) {
867     if (!AMDGPU::isGFX10(STI)) {
868       O << " /* row_xmask is not supported on ASICs earlier than GFX10 */";
869       return;
870     }
871     O << "row_xmask:";
872     printU4ImmDecOperand(MI, OpNo, O);
873   } else {
874     O << " /* Invalid dpp_ctrl value */";
875   }
876 }
877 
878 void AMDGPUInstPrinter::printRowMask(const MCInst *MI, unsigned OpNo,
879                                      const MCSubtargetInfo &STI,
880                                      raw_ostream &O) {
881   O << " row_mask:";
882   printU4ImmOperand(MI, OpNo, STI, O);
883 }
884 
885 void AMDGPUInstPrinter::printBankMask(const MCInst *MI, unsigned OpNo,
886                                       const MCSubtargetInfo &STI,
887                                       raw_ostream &O) {
888   O << " bank_mask:";
889   printU4ImmOperand(MI, OpNo, STI, O);
890 }
891 
892 void AMDGPUInstPrinter::printBoundCtrl(const MCInst *MI, unsigned OpNo,
893                                        const MCSubtargetInfo &STI,
894                                        raw_ostream &O) {
895   unsigned Imm = MI->getOperand(OpNo).getImm();
896   if (Imm) {
897     O << " bound_ctrl:0"; // XXX - this syntax is used in sp3
898   }
899 }
900 
901 void AMDGPUInstPrinter::printFI(const MCInst *MI, unsigned OpNo,
902                                 const MCSubtargetInfo &STI,
903                                 raw_ostream &O) {
904   using namespace llvm::AMDGPU::DPP;
905   unsigned Imm = MI->getOperand(OpNo).getImm();
906   if (Imm == DPP_FI_1 || Imm == DPP8_FI_1) {
907     O << " fi:1";
908   }
909 }
910 
911 void AMDGPUInstPrinter::printSDWASel(const MCInst *MI, unsigned OpNo,
912                                      raw_ostream &O) {
913   using namespace llvm::AMDGPU::SDWA;
914 
915   unsigned Imm = MI->getOperand(OpNo).getImm();
916   switch (Imm) {
917   case SdwaSel::BYTE_0: O << "BYTE_0"; break;
918   case SdwaSel::BYTE_1: O << "BYTE_1"; break;
919   case SdwaSel::BYTE_2: O << "BYTE_2"; break;
920   case SdwaSel::BYTE_3: O << "BYTE_3"; break;
921   case SdwaSel::WORD_0: O << "WORD_0"; break;
922   case SdwaSel::WORD_1: O << "WORD_1"; break;
923   case SdwaSel::DWORD: O << "DWORD"; break;
924   default: llvm_unreachable("Invalid SDWA data select operand");
925   }
926 }
927 
928 void AMDGPUInstPrinter::printSDWADstSel(const MCInst *MI, unsigned OpNo,
929                                         const MCSubtargetInfo &STI,
930                                         raw_ostream &O) {
931   O << "dst_sel:";
932   printSDWASel(MI, OpNo, O);
933 }
934 
935 void AMDGPUInstPrinter::printSDWASrc0Sel(const MCInst *MI, unsigned OpNo,
936                                          const MCSubtargetInfo &STI,
937                                          raw_ostream &O) {
938   O << "src0_sel:";
939   printSDWASel(MI, OpNo, O);
940 }
941 
942 void AMDGPUInstPrinter::printSDWASrc1Sel(const MCInst *MI, unsigned OpNo,
943                                          const MCSubtargetInfo &STI,
944                                          raw_ostream &O) {
945   O << "src1_sel:";
946   printSDWASel(MI, OpNo, O);
947 }
948 
949 void AMDGPUInstPrinter::printSDWADstUnused(const MCInst *MI, unsigned OpNo,
950                                            const MCSubtargetInfo &STI,
951                                            raw_ostream &O) {
952   using namespace llvm::AMDGPU::SDWA;
953 
954   O << "dst_unused:";
955   unsigned Imm = MI->getOperand(OpNo).getImm();
956   switch (Imm) {
957   case DstUnused::UNUSED_PAD: O << "UNUSED_PAD"; break;
958   case DstUnused::UNUSED_SEXT: O << "UNUSED_SEXT"; break;
959   case DstUnused::UNUSED_PRESERVE: O << "UNUSED_PRESERVE"; break;
960   default: llvm_unreachable("Invalid SDWA dest_unused operand");
961   }
962 }
963 
964 template <unsigned N>
965 void AMDGPUInstPrinter::printExpSrcN(const MCInst *MI, unsigned OpNo,
966                                      const MCSubtargetInfo &STI,
967                                      raw_ostream &O) {
968   unsigned Opc = MI->getOpcode();
969   int EnIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::en);
970   unsigned En = MI->getOperand(EnIdx).getImm();
971 
972   int ComprIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::compr);
973 
974   // If compr is set, print as src0, src0, src1, src1
975   if (MI->getOperand(ComprIdx).getImm()) {
976     if (N == 1 || N == 2)
977       --OpNo;
978     else if (N == 3)
979       OpNo -= 2;
980   }
981 
982   if (En & (1 << N))
983     printRegOperand(MI->getOperand(OpNo).getReg(), O, MRI);
984   else
985     O << "off";
986 }
987 
988 void AMDGPUInstPrinter::printExpSrc0(const MCInst *MI, unsigned OpNo,
989                                      const MCSubtargetInfo &STI,
990                                      raw_ostream &O) {
991   printExpSrcN<0>(MI, OpNo, STI, O);
992 }
993 
994 void AMDGPUInstPrinter::printExpSrc1(const MCInst *MI, unsigned OpNo,
995                                      const MCSubtargetInfo &STI,
996                                      raw_ostream &O) {
997   printExpSrcN<1>(MI, OpNo, STI, O);
998 }
999 
1000 void AMDGPUInstPrinter::printExpSrc2(const MCInst *MI, unsigned OpNo,
1001                                      const MCSubtargetInfo &STI,
1002                                      raw_ostream &O) {
1003   printExpSrcN<2>(MI, OpNo, STI, O);
1004 }
1005 
1006 void AMDGPUInstPrinter::printExpSrc3(const MCInst *MI, unsigned OpNo,
1007                                      const MCSubtargetInfo &STI,
1008                                      raw_ostream &O) {
1009   printExpSrcN<3>(MI, OpNo, STI, O);
1010 }
1011 
1012 void AMDGPUInstPrinter::printExpTgt(const MCInst *MI, unsigned OpNo,
1013                                     const MCSubtargetInfo &STI,
1014                                     raw_ostream &O) {
1015   // This is really a 6 bit field.
1016   uint32_t Tgt = MI->getOperand(OpNo).getImm() & ((1 << 6) - 1);
1017 
1018   if (Tgt <= 7)
1019     O << " mrt" << Tgt;
1020   else if (Tgt == 8)
1021     O << " mrtz";
1022   else if (Tgt == 9)
1023     O << " null";
1024   else if ((Tgt >= 12 && Tgt <= 15) || (Tgt == 16 && AMDGPU::isGFX10(STI)))
1025     O << " pos" << Tgt - 12;
1026   else if (AMDGPU::isGFX10(STI) && Tgt == 20)
1027     O << " prim";
1028   else if (Tgt >= 32 && Tgt <= 63)
1029     O << " param" << Tgt - 32;
1030   else {
1031     // Reserved values 10, 11
1032     O << " invalid_target_" << Tgt;
1033   }
1034 }
1035 
1036 static bool allOpsDefaultValue(const int* Ops, int NumOps, int Mod,
1037                                bool IsPacked, bool HasDstSel) {
1038   int DefaultValue = IsPacked && (Mod == SISrcMods::OP_SEL_1);
1039 
1040   for (int I = 0; I < NumOps; ++I) {
1041     if (!!(Ops[I] & Mod) != DefaultValue)
1042       return false;
1043   }
1044 
1045   if (HasDstSel && (Ops[0] & SISrcMods::DST_OP_SEL) != 0)
1046     return false;
1047 
1048   return true;
1049 }
1050 
1051 void AMDGPUInstPrinter::printPackedModifier(const MCInst *MI,
1052                                             StringRef Name,
1053                                             unsigned Mod,
1054                                             raw_ostream &O) {
1055   unsigned Opc = MI->getOpcode();
1056   int NumOps = 0;
1057   int Ops[3];
1058 
1059   for (int OpName : { AMDGPU::OpName::src0_modifiers,
1060                       AMDGPU::OpName::src1_modifiers,
1061                       AMDGPU::OpName::src2_modifiers }) {
1062     int Idx = AMDGPU::getNamedOperandIdx(Opc, OpName);
1063     if (Idx == -1)
1064       break;
1065 
1066     Ops[NumOps++] = MI->getOperand(Idx).getImm();
1067   }
1068 
1069   const bool HasDstSel =
1070     NumOps > 0 &&
1071     Mod == SISrcMods::OP_SEL_0 &&
1072     MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::VOP3_OPSEL;
1073 
1074   const bool IsPacked =
1075     MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::IsPacked;
1076 
1077   if (allOpsDefaultValue(Ops, NumOps, Mod, IsPacked, HasDstSel))
1078     return;
1079 
1080   O << Name;
1081   for (int I = 0; I < NumOps; ++I) {
1082     if (I != 0)
1083       O << ',';
1084 
1085     O << !!(Ops[I] & Mod);
1086   }
1087 
1088   if (HasDstSel) {
1089     O << ',' << !!(Ops[0] & SISrcMods::DST_OP_SEL);
1090   }
1091 
1092   O << ']';
1093 }
1094 
1095 void AMDGPUInstPrinter::printOpSel(const MCInst *MI, unsigned,
1096                                    const MCSubtargetInfo &STI,
1097                                    raw_ostream &O) {
1098   unsigned Opc = MI->getOpcode();
1099   if (Opc == AMDGPU::V_PERMLANE16_B32_gfx10 ||
1100       Opc == AMDGPU::V_PERMLANEX16_B32_gfx10) {
1101     auto FIN = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers);
1102     auto BCN = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers);
1103     unsigned FI = !!(MI->getOperand(FIN).getImm() & SISrcMods::OP_SEL_0);
1104     unsigned BC = !!(MI->getOperand(BCN).getImm() & SISrcMods::OP_SEL_0);
1105     if (FI || BC)
1106       O << " op_sel:[" << FI << ',' << BC << ']';
1107     return;
1108   }
1109 
1110   printPackedModifier(MI, " op_sel:[", SISrcMods::OP_SEL_0, O);
1111 }
1112 
1113 void AMDGPUInstPrinter::printOpSelHi(const MCInst *MI, unsigned OpNo,
1114                                      const MCSubtargetInfo &STI,
1115                                      raw_ostream &O) {
1116   printPackedModifier(MI, " op_sel_hi:[", SISrcMods::OP_SEL_1, O);
1117 }
1118 
1119 void AMDGPUInstPrinter::printNegLo(const MCInst *MI, unsigned OpNo,
1120                                    const MCSubtargetInfo &STI,
1121                                    raw_ostream &O) {
1122   printPackedModifier(MI, " neg_lo:[", SISrcMods::NEG, O);
1123 }
1124 
1125 void AMDGPUInstPrinter::printNegHi(const MCInst *MI, unsigned OpNo,
1126                                    const MCSubtargetInfo &STI,
1127                                    raw_ostream &O) {
1128   printPackedModifier(MI, " neg_hi:[", SISrcMods::NEG_HI, O);
1129 }
1130 
1131 void AMDGPUInstPrinter::printInterpSlot(const MCInst *MI, unsigned OpNum,
1132                                         const MCSubtargetInfo &STI,
1133                                         raw_ostream &O) {
1134   unsigned Imm = MI->getOperand(OpNum).getImm();
1135   switch (Imm) {
1136   case 0:
1137     O << "p10";
1138     break;
1139   case 1:
1140     O << "p20";
1141     break;
1142   case 2:
1143     O << "p0";
1144     break;
1145   default:
1146     O << "invalid_param_" << Imm;
1147   }
1148 }
1149 
1150 void AMDGPUInstPrinter::printInterpAttr(const MCInst *MI, unsigned OpNum,
1151                                         const MCSubtargetInfo &STI,
1152                                         raw_ostream &O) {
1153   unsigned Attr = MI->getOperand(OpNum).getImm();
1154   O << "attr" << Attr;
1155 }
1156 
1157 void AMDGPUInstPrinter::printInterpAttrChan(const MCInst *MI, unsigned OpNum,
1158                                         const MCSubtargetInfo &STI,
1159                                         raw_ostream &O) {
1160   unsigned Chan = MI->getOperand(OpNum).getImm();
1161   O << '.' << "xyzw"[Chan & 0x3];
1162 }
1163 
1164 void AMDGPUInstPrinter::printVGPRIndexMode(const MCInst *MI, unsigned OpNo,
1165                                            const MCSubtargetInfo &STI,
1166                                            raw_ostream &O) {
1167   using namespace llvm::AMDGPU::VGPRIndexMode;
1168   unsigned Val = MI->getOperand(OpNo).getImm();
1169 
1170   if ((Val & ~ENABLE_MASK) != 0) {
1171     O << " " << formatHex(static_cast<uint64_t>(Val));
1172   } else {
1173     O << " gpr_idx(";
1174     bool NeedComma = false;
1175     for (unsigned ModeId = ID_MIN; ModeId <= ID_MAX; ++ModeId) {
1176       if (Val & (1 << ModeId)) {
1177         if (NeedComma)
1178           O << ',';
1179         O << IdSymbolic[ModeId];
1180         NeedComma = true;
1181       }
1182     }
1183     O << ')';
1184   }
1185 }
1186 
1187 void AMDGPUInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo,
1188                                         const MCSubtargetInfo &STI,
1189                                         raw_ostream &O) {
1190   printOperand(MI, OpNo, STI, O);
1191   O  << ", ";
1192   printOperand(MI, OpNo + 1, STI, O);
1193 }
1194 
1195 void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
1196                                    raw_ostream &O, StringRef Asm,
1197                                    StringRef Default) {
1198   const MCOperand &Op = MI->getOperand(OpNo);
1199   assert(Op.isImm());
1200   if (Op.getImm() == 1) {
1201     O << Asm;
1202   } else {
1203     O << Default;
1204   }
1205 }
1206 
1207 void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
1208                                    raw_ostream &O, char Asm) {
1209   const MCOperand &Op = MI->getOperand(OpNo);
1210   assert(Op.isImm());
1211   if (Op.getImm() == 1)
1212     O << Asm;
1213 }
1214 
1215 void AMDGPUInstPrinter::printHigh(const MCInst *MI, unsigned OpNo,
1216                                   const MCSubtargetInfo &STI,
1217                                   raw_ostream &O) {
1218   printNamedBit(MI, OpNo, O, "high");
1219 }
1220 
1221 void AMDGPUInstPrinter::printClampSI(const MCInst *MI, unsigned OpNo,
1222                                      const MCSubtargetInfo &STI,
1223                                      raw_ostream &O) {
1224   printNamedBit(MI, OpNo, O, "clamp");
1225 }
1226 
1227 void AMDGPUInstPrinter::printOModSI(const MCInst *MI, unsigned OpNo,
1228                                     const MCSubtargetInfo &STI,
1229                                     raw_ostream &O) {
1230   int Imm = MI->getOperand(OpNo).getImm();
1231   if (Imm == SIOutMods::MUL2)
1232     O << " mul:2";
1233   else if (Imm == SIOutMods::MUL4)
1234     O << " mul:4";
1235   else if (Imm == SIOutMods::DIV2)
1236     O << " div:2";
1237 }
1238 
1239 void AMDGPUInstPrinter::printSendMsg(const MCInst *MI, unsigned OpNo,
1240                                      const MCSubtargetInfo &STI,
1241                                      raw_ostream &O) {
1242   using namespace llvm::AMDGPU::SendMsg;
1243 
1244   const unsigned Imm16 = MI->getOperand(OpNo).getImm();
1245 
1246   uint16_t MsgId;
1247   uint16_t OpId;
1248   uint16_t StreamId;
1249   decodeMsg(Imm16, MsgId, OpId, StreamId);
1250 
1251   if (isValidMsgId(MsgId, STI) &&
1252       isValidMsgOp(MsgId, OpId) &&
1253       isValidMsgStream(MsgId, OpId, StreamId)) {
1254     O << "sendmsg(" << getMsgName(MsgId);
1255     if (msgRequiresOp(MsgId)) {
1256       O << ", " << getMsgOpName(MsgId, OpId);
1257       if (msgSupportsStream(MsgId, OpId)) {
1258         O << ", " << StreamId;
1259       }
1260     }
1261     O << ')';
1262   } else if (encodeMsg(MsgId, OpId, StreamId) == Imm16) {
1263     O << "sendmsg(" << MsgId << ", " << OpId << ", " << StreamId << ')';
1264   } else {
1265     O << Imm16; // Unknown imm16 code.
1266   }
1267 }
1268 
1269 static void printSwizzleBitmask(const uint16_t AndMask,
1270                                 const uint16_t OrMask,
1271                                 const uint16_t XorMask,
1272                                 raw_ostream &O) {
1273   using namespace llvm::AMDGPU::Swizzle;
1274 
1275   uint16_t Probe0 = ((0            & AndMask) | OrMask) ^ XorMask;
1276   uint16_t Probe1 = ((BITMASK_MASK & AndMask) | OrMask) ^ XorMask;
1277 
1278   O << "\"";
1279 
1280   for (unsigned Mask = 1 << (BITMASK_WIDTH - 1); Mask > 0; Mask >>= 1) {
1281     uint16_t p0 = Probe0 & Mask;
1282     uint16_t p1 = Probe1 & Mask;
1283 
1284     if (p0 == p1) {
1285       if (p0 == 0) {
1286         O << "0";
1287       } else {
1288         O << "1";
1289       }
1290     } else {
1291       if (p0 == 0) {
1292         O << "p";
1293       } else {
1294         O << "i";
1295       }
1296     }
1297   }
1298 
1299   O << "\"";
1300 }
1301 
1302 void AMDGPUInstPrinter::printSwizzle(const MCInst *MI, unsigned OpNo,
1303                                      const MCSubtargetInfo &STI,
1304                                      raw_ostream &O) {
1305   using namespace llvm::AMDGPU::Swizzle;
1306 
1307   uint16_t Imm = MI->getOperand(OpNo).getImm();
1308   if (Imm == 0) {
1309     return;
1310   }
1311 
1312   O << " offset:";
1313 
1314   if ((Imm & QUAD_PERM_ENC_MASK) == QUAD_PERM_ENC) {
1315 
1316     O << "swizzle(" << IdSymbolic[ID_QUAD_PERM];
1317     for (unsigned I = 0; I < LANE_NUM; ++I) {
1318       O << ",";
1319       O << formatDec(Imm & LANE_MASK);
1320       Imm >>= LANE_SHIFT;
1321     }
1322     O << ")";
1323 
1324   } else if ((Imm & BITMASK_PERM_ENC_MASK) == BITMASK_PERM_ENC) {
1325 
1326     uint16_t AndMask = (Imm >> BITMASK_AND_SHIFT) & BITMASK_MASK;
1327     uint16_t OrMask  = (Imm >> BITMASK_OR_SHIFT)  & BITMASK_MASK;
1328     uint16_t XorMask = (Imm >> BITMASK_XOR_SHIFT) & BITMASK_MASK;
1329 
1330     if (AndMask == BITMASK_MAX &&
1331         OrMask == 0 &&
1332         countPopulation(XorMask) == 1) {
1333 
1334       O << "swizzle(" << IdSymbolic[ID_SWAP];
1335       O << ",";
1336       O << formatDec(XorMask);
1337       O << ")";
1338 
1339     } else if (AndMask == BITMASK_MAX &&
1340                OrMask == 0 && XorMask > 0 &&
1341                isPowerOf2_64(XorMask + 1)) {
1342 
1343       O << "swizzle(" << IdSymbolic[ID_REVERSE];
1344       O << ",";
1345       O << formatDec(XorMask + 1);
1346       O << ")";
1347 
1348     } else {
1349 
1350       uint16_t GroupSize = BITMASK_MAX - AndMask + 1;
1351       if (GroupSize > 1 &&
1352           isPowerOf2_64(GroupSize) &&
1353           OrMask < GroupSize &&
1354           XorMask == 0) {
1355 
1356         O << "swizzle(" << IdSymbolic[ID_BROADCAST];
1357         O << ",";
1358         O << formatDec(GroupSize);
1359         O << ",";
1360         O << formatDec(OrMask);
1361         O << ")";
1362 
1363       } else {
1364         O << "swizzle(" << IdSymbolic[ID_BITMASK_PERM];
1365         O << ",";
1366         printSwizzleBitmask(AndMask, OrMask, XorMask, O);
1367         O << ")";
1368       }
1369     }
1370   } else {
1371     printU16ImmDecOperand(MI, OpNo, O);
1372   }
1373 }
1374 
1375 void AMDGPUInstPrinter::printWaitFlag(const MCInst *MI, unsigned OpNo,
1376                                       const MCSubtargetInfo &STI,
1377                                       raw_ostream &O) {
1378   AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(STI.getCPU());
1379 
1380   unsigned SImm16 = MI->getOperand(OpNo).getImm();
1381   unsigned Vmcnt, Expcnt, Lgkmcnt;
1382   decodeWaitcnt(ISA, SImm16, Vmcnt, Expcnt, Lgkmcnt);
1383 
1384   bool NeedSpace = false;
1385 
1386   if (Vmcnt != getVmcntBitMask(ISA)) {
1387     O << "vmcnt(" << Vmcnt << ')';
1388     NeedSpace = true;
1389   }
1390 
1391   if (Expcnt != getExpcntBitMask(ISA)) {
1392     if (NeedSpace)
1393       O << ' ';
1394     O << "expcnt(" << Expcnt << ')';
1395     NeedSpace = true;
1396   }
1397 
1398   if (Lgkmcnt != getLgkmcntBitMask(ISA)) {
1399     if (NeedSpace)
1400       O << ' ';
1401     O << "lgkmcnt(" << Lgkmcnt << ')';
1402   }
1403 }
1404 
1405 void AMDGPUInstPrinter::printHwreg(const MCInst *MI, unsigned OpNo,
1406                                    const MCSubtargetInfo &STI, raw_ostream &O) {
1407   unsigned Id;
1408   unsigned Offset;
1409   unsigned Width;
1410 
1411   using namespace llvm::AMDGPU::Hwreg;
1412   unsigned Val = MI->getOperand(OpNo).getImm();
1413   decodeHwreg(Val, Id, Offset, Width);
1414   StringRef HwRegName = getHwreg(Id, STI);
1415 
1416   O << "hwreg(";
1417   if (!HwRegName.empty()) {
1418     O << HwRegName;
1419   } else {
1420     O << Id;
1421   }
1422   if (Width != WIDTH_DEFAULT_ || Offset != OFFSET_DEFAULT_) {
1423     O << ", " << Offset << ", " << Width;
1424   }
1425   O << ')';
1426 }
1427 
1428 void AMDGPUInstPrinter::printEndpgm(const MCInst *MI, unsigned OpNo,
1429                                     const MCSubtargetInfo &STI,
1430                                     raw_ostream &O) {
1431   uint16_t Imm = MI->getOperand(OpNo).getImm();
1432   if (Imm == 0) {
1433     return;
1434   }
1435 
1436   O << ' ' << formatDec(Imm);
1437 }
1438 
1439 #include "AMDGPUGenAsmWriter.inc"
1440 
1441 void R600InstPrinter::printInst(const MCInst *MI, uint64_t Address,
1442                                 StringRef Annot, const MCSubtargetInfo &STI,
1443                                 raw_ostream &O) {
1444   O.flush();
1445   printInstruction(MI, Address, O);
1446   printAnnotation(O, Annot);
1447 }
1448 
1449 void R600InstPrinter::printAbs(const MCInst *MI, unsigned OpNo,
1450                                raw_ostream &O) {
1451   AMDGPUInstPrinter::printIfSet(MI, OpNo, O, '|');
1452 }
1453 
1454 void R600InstPrinter::printBankSwizzle(const MCInst *MI, unsigned OpNo,
1455                                        raw_ostream &O) {
1456   int BankSwizzle = MI->getOperand(OpNo).getImm();
1457   switch (BankSwizzle) {
1458   case 1:
1459     O << "BS:VEC_021/SCL_122";
1460     break;
1461   case 2:
1462     O << "BS:VEC_120/SCL_212";
1463     break;
1464   case 3:
1465     O << "BS:VEC_102/SCL_221";
1466     break;
1467   case 4:
1468     O << "BS:VEC_201";
1469     break;
1470   case 5:
1471     O << "BS:VEC_210";
1472     break;
1473   default:
1474     break;
1475   }
1476 }
1477 
1478 void R600InstPrinter::printClamp(const MCInst *MI, unsigned OpNo,
1479                                  raw_ostream &O) {
1480   AMDGPUInstPrinter::printIfSet(MI, OpNo, O, "_SAT");
1481 }
1482 
1483 void R600InstPrinter::printCT(const MCInst *MI, unsigned OpNo,
1484                                 raw_ostream &O) {
1485   unsigned CT = MI->getOperand(OpNo).getImm();
1486   switch (CT) {
1487   case 0:
1488     O << 'U';
1489     break;
1490   case 1:
1491     O << 'N';
1492     break;
1493   default:
1494     break;
1495   }
1496 }
1497 
1498 void R600InstPrinter::printKCache(const MCInst *MI, unsigned OpNo,
1499                                   raw_ostream &O) {
1500   int KCacheMode = MI->getOperand(OpNo).getImm();
1501   if (KCacheMode > 0) {
1502     int KCacheBank = MI->getOperand(OpNo - 2).getImm();
1503     O << "CB" << KCacheBank << ':';
1504     int KCacheAddr = MI->getOperand(OpNo + 2).getImm();
1505     int LineSize = (KCacheMode == 1) ? 16 : 32;
1506     O << KCacheAddr * 16 << '-' << KCacheAddr * 16 + LineSize;
1507   }
1508 }
1509 
1510 void R600InstPrinter::printLast(const MCInst *MI, unsigned OpNo,
1511                                 raw_ostream &O) {
1512   AMDGPUInstPrinter::printIfSet(MI, OpNo, O, "*", " ");
1513 }
1514 
1515 void R600InstPrinter::printLiteral(const MCInst *MI, unsigned OpNo,
1516                                    raw_ostream &O) {
1517   const MCOperand &Op = MI->getOperand(OpNo);
1518   assert(Op.isImm() || Op.isExpr());
1519   if (Op.isImm()) {
1520     int64_t Imm = Op.getImm();
1521     O << Imm << '(' << BitsToFloat(Imm) << ')';
1522   }
1523   if (Op.isExpr()) {
1524     Op.getExpr()->print(O << '@', &MAI);
1525   }
1526 }
1527 
1528 void R600InstPrinter::printNeg(const MCInst *MI, unsigned OpNo,
1529                                raw_ostream &O) {
1530   AMDGPUInstPrinter::printIfSet(MI, OpNo, O, '-');
1531 }
1532 
1533 void R600InstPrinter::printOMOD(const MCInst *MI, unsigned OpNo,
1534                                 raw_ostream &O) {
1535   switch (MI->getOperand(OpNo).getImm()) {
1536   default: break;
1537   case 1:
1538     O << " * 2.0";
1539     break;
1540   case 2:
1541     O << " * 4.0";
1542     break;
1543   case 3:
1544     O << " / 2.0";
1545     break;
1546   }
1547 }
1548 
1549 void R600InstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo,
1550                                       raw_ostream &O) {
1551   printOperand(MI, OpNo, O);
1552   O  << ", ";
1553   printOperand(MI, OpNo + 1, O);
1554 }
1555 
1556 void R600InstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
1557                                    raw_ostream &O) {
1558   if (OpNo >= MI->getNumOperands()) {
1559     O << "/*Missing OP" << OpNo << "*/";
1560     return;
1561   }
1562 
1563   const MCOperand &Op = MI->getOperand(OpNo);
1564   if (Op.isReg()) {
1565     switch (Op.getReg()) {
1566     // This is the default predicate state, so we don't need to print it.
1567     case R600::PRED_SEL_OFF:
1568       break;
1569 
1570     default:
1571       O << getRegisterName(Op.getReg());
1572       break;
1573     }
1574   } else if (Op.isImm()) {
1575       O << Op.getImm();
1576   } else if (Op.isFPImm()) {
1577     // We special case 0.0 because otherwise it will be printed as an integer.
1578     if (Op.getFPImm() == 0.0)
1579       O << "0.0";
1580     else {
1581       O << Op.getFPImm();
1582     }
1583   } else if (Op.isExpr()) {
1584     const MCExpr *Exp = Op.getExpr();
1585     Exp->print(O, &MAI);
1586   } else {
1587     O << "/*INV_OP*/";
1588   }
1589 }
1590 
1591 void R600InstPrinter::printRel(const MCInst *MI, unsigned OpNo,
1592                                raw_ostream &O) {
1593   AMDGPUInstPrinter::printIfSet(MI, OpNo, O, '+');
1594 }
1595 
1596 void R600InstPrinter::printRSel(const MCInst *MI, unsigned OpNo,
1597                                   raw_ostream &O) {
1598   unsigned Sel = MI->getOperand(OpNo).getImm();
1599   switch (Sel) {
1600   case 0:
1601     O << 'X';
1602     break;
1603   case 1:
1604     O << 'Y';
1605     break;
1606   case 2:
1607     O << 'Z';
1608     break;
1609   case 3:
1610     O << 'W';
1611     break;
1612   case 4:
1613     O << '0';
1614     break;
1615   case 5:
1616     O << '1';
1617     break;
1618   case 7:
1619     O << '_';
1620     break;
1621   default:
1622     break;
1623   }
1624 }
1625 
1626 void R600InstPrinter::printUpdateExecMask(const MCInst *MI, unsigned OpNo,
1627                                           raw_ostream &O) {
1628   AMDGPUInstPrinter::printIfSet(MI, OpNo, O, "ExecMask,");
1629 }
1630 
1631 void R600InstPrinter::printUpdatePred(const MCInst *MI, unsigned OpNo,
1632                                       raw_ostream &O) {
1633   AMDGPUInstPrinter::printIfSet(MI, OpNo, O, "Pred,");
1634 }
1635 
1636 void R600InstPrinter::printWrite(const MCInst *MI, unsigned OpNo,
1637                                  raw_ostream &O) {
1638   const MCOperand &Op = MI->getOperand(OpNo);
1639   if (Op.getImm() == 0) {
1640     O << " (MASKED)";
1641   }
1642 }
1643 
1644 #include "R600GenAsmWriter.inc"
1645