1 //===-- AMDGPUAsmBackend.cpp - AMDGPU Assembler Backend -------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 /// \file
9 //===----------------------------------------------------------------------===//
10 
11 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
12 #include "MCTargetDesc/AMDGPUFixupKinds.h"
13 #include "llvm/ADT/StringRef.h"
14 #include "llvm/MC/MCAsmBackend.h"
15 #include "llvm/MC/MCAssembler.h"
16 #include "llvm/MC/MCFixupKindInfo.h"
17 #include "llvm/MC/MCObjectWriter.h"
18 #include "llvm/MC/MCValue.h"
19 #include "llvm/Support/TargetRegistry.h"
20 
21 using namespace llvm;
22 
23 namespace {
24 
25 class AMDGPUMCObjectWriter : public MCObjectWriter {
26 public:
27   AMDGPUMCObjectWriter(raw_pwrite_stream &OS) : MCObjectWriter(OS, true) {}
28   void executePostLayoutBinding(MCAssembler &Asm,
29                                 const MCAsmLayout &Layout) override {
30     //XXX: Implement if necessary.
31   }
32   void recordRelocation(MCAssembler &Asm, const MCAsmLayout &Layout,
33                         const MCFragment *Fragment, const MCFixup &Fixup,
34                         MCValue Target, bool &IsPCRel,
35                         uint64_t &FixedValue) override {
36     assert(!"Not implemented");
37   }
38 
39   void writeObject(MCAssembler &Asm, const MCAsmLayout &Layout) override;
40 
41 };
42 
43 class AMDGPUAsmBackend : public MCAsmBackend {
44 public:
45   AMDGPUAsmBackend(const Target &T)
46     : MCAsmBackend() {}
47 
48   unsigned getNumFixupKinds() const override { return AMDGPU::NumTargetFixupKinds; };
49   void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
50                   uint64_t Value, bool IsPCRel) const override;
51   bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
52                             const MCRelaxableFragment *DF,
53                             const MCAsmLayout &Layout) const override {
54     return false;
55   }
56   void relaxInstruction(const MCInst &Inst, MCInst &Res) const override {
57     assert(!"Not implemented");
58   }
59   bool mayNeedRelaxation(const MCInst &Inst) const override { return false; }
60   bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
61 
62   const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
63 };
64 
65 } //End anonymous namespace
66 
67 void AMDGPUMCObjectWriter::writeObject(MCAssembler &Asm,
68                                        const MCAsmLayout &Layout) {
69   for (MCAssembler::iterator I = Asm.begin(), E = Asm.end(); I != E; ++I) {
70     Asm.writeSectionData(&*I, Layout);
71   }
72 }
73 
74 static unsigned getFixupKindNumBytes(unsigned Kind) {
75   switch (Kind) {
76   case FK_Data_1:
77     return 1;
78   case FK_Data_2:
79     return 2;
80   case FK_Data_4:
81     return 4;
82   case FK_Data_8:
83     return 8;
84   default:
85     llvm_unreachable("Unknown fixup kind!");
86   }
87 }
88 
89 void AMDGPUAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
90                                   unsigned DataSize, uint64_t Value,
91                                   bool IsPCRel) const {
92 
93   switch ((unsigned)Fixup.getKind()) {
94     case AMDGPU::fixup_si_sopp_br: {
95       uint16_t *Dst = (uint16_t*)(Data + Fixup.getOffset());
96       *Dst = (Value - 4) / 4;
97       break;
98     }
99 
100     case AMDGPU::fixup_si_rodata: {
101       uint32_t *Dst = (uint32_t*)(Data + Fixup.getOffset());
102       *Dst = Value;
103       break;
104     }
105 
106     case AMDGPU::fixup_si_end_of_text: {
107       uint32_t *Dst = (uint32_t*)(Data + Fixup.getOffset());
108       // The value points to the last instruction in the text section, so we
109       // need to add 4 bytes to get to the start of the constants.
110       *Dst = Value + 4;
111       break;
112     }
113     default: {
114       // FIXME: Copied from AArch64
115       unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
116       if (!Value)
117         return; // Doesn't change encoding.
118       MCFixupKindInfo Info = getFixupKindInfo(Fixup.getKind());
119 
120       // Shift the value into position.
121       Value <<= Info.TargetOffset;
122 
123       unsigned Offset = Fixup.getOffset();
124       assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!");
125 
126       // For each byte of the fragment that the fixup touches, mask in the
127       // bits from the fixup value.
128       for (unsigned i = 0; i != NumBytes; ++i)
129         Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
130     }
131   }
132 }
133 
134 const MCFixupKindInfo &AMDGPUAsmBackend::getFixupKindInfo(
135                                                        MCFixupKind Kind) const {
136   const static MCFixupKindInfo Infos[AMDGPU::NumTargetFixupKinds] = {
137     // name                   offset bits  flags
138     { "fixup_si_sopp_br",     0,     16,   MCFixupKindInfo::FKF_IsPCRel },
139     { "fixup_si_rodata",      0,     32,   0 },
140     { "fixup_si_end_of_text", 0,     32,   MCFixupKindInfo::FKF_IsPCRel }
141   };
142 
143   if (Kind < FirstTargetFixupKind)
144     return MCAsmBackend::getFixupKindInfo(Kind);
145 
146   return Infos[Kind - FirstTargetFixupKind];
147 }
148 
149 bool AMDGPUAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
150   OW->WriteZeros(Count);
151 
152   return true;
153 }
154 
155 //===----------------------------------------------------------------------===//
156 // ELFAMDGPUAsmBackend class
157 //===----------------------------------------------------------------------===//
158 
159 namespace {
160 
161 class ELFAMDGPUAsmBackend : public AMDGPUAsmBackend {
162   bool Is64Bit;
163 
164 public:
165   ELFAMDGPUAsmBackend(const Target &T, bool Is64Bit) :
166       AMDGPUAsmBackend(T), Is64Bit(Is64Bit) { }
167 
168   MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
169     return createAMDGPUELFObjectWriter(Is64Bit, OS);
170   }
171 };
172 
173 } // end anonymous namespace
174 
175 MCAsmBackend *llvm::createAMDGPUAsmBackend(const Target &T,
176                                            const MCRegisterInfo &MRI,
177                                            const Triple &TT, StringRef CPU) {
178   Triple TargetTriple(TT);
179 
180   // Use 64-bit ELF for amdgcn
181   return new ELFAMDGPUAsmBackend(T, TargetTriple.getArch() == Triple::amdgcn);
182 }
183