1 //===-- AMDGPUAsmBackend.cpp - AMDGPU Assembler Backend -------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 /// \file
9 //===----------------------------------------------------------------------===//
10 
11 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
12 #include "MCTargetDesc/AMDGPUFixupKinds.h"
13 #include "llvm/ADT/StringRef.h"
14 #include "llvm/MC/MCAsmBackend.h"
15 #include "llvm/MC/MCAssembler.h"
16 #include "llvm/MC/MCFixupKindInfo.h"
17 #include "llvm/MC/MCObjectWriter.h"
18 #include "llvm/MC/MCValue.h"
19 #include "llvm/Support/TargetRegistry.h"
20 
21 using namespace llvm;
22 
23 namespace {
24 
25 class AMDGPUMCObjectWriter : public MCObjectWriter {
26 public:
27   AMDGPUMCObjectWriter(raw_pwrite_stream &OS) : MCObjectWriter(OS, true) {}
28   void executePostLayoutBinding(MCAssembler &Asm,
29                                 const MCAsmLayout &Layout) override {
30     //XXX: Implement if necessary.
31   }
32   void recordRelocation(MCAssembler &Asm, const MCAsmLayout &Layout,
33                         const MCFragment *Fragment, const MCFixup &Fixup,
34                         MCValue Target, bool &IsPCRel,
35                         uint64_t &FixedValue) override {
36     assert(!"Not implemented");
37   }
38 
39   void writeObject(MCAssembler &Asm, const MCAsmLayout &Layout) override;
40 
41 };
42 
43 class AMDGPUAsmBackend : public MCAsmBackend {
44 public:
45   AMDGPUAsmBackend(const Target &T)
46     : MCAsmBackend() {}
47 
48   unsigned getNumFixupKinds() const override { return AMDGPU::NumTargetFixupKinds; };
49   void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
50                   uint64_t Value, bool IsPCRel) const override;
51   bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
52                             const MCRelaxableFragment *DF,
53                             const MCAsmLayout &Layout) const override {
54     return false;
55   }
56   void relaxInstruction(const MCInst &Inst, MCInst &Res) const override {
57     assert(!"Not implemented");
58   }
59   bool mayNeedRelaxation(const MCInst &Inst) const override { return false; }
60   bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
61 
62   const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
63 };
64 
65 } //End anonymous namespace
66 
67 void AMDGPUMCObjectWriter::writeObject(MCAssembler &Asm,
68                                        const MCAsmLayout &Layout) {
69   for (MCAssembler::iterator I = Asm.begin(), E = Asm.end(); I != E; ++I) {
70     Asm.writeSectionData(&*I, Layout);
71   }
72 }
73 
74 static unsigned getFixupKindNumBytes(unsigned Kind) {
75   switch (Kind) {
76   case FK_SecRel_1:
77   case FK_Data_1:
78     return 1;
79   case FK_SecRel_2:
80   case FK_Data_2:
81     return 2;
82   case FK_SecRel_4:
83   case FK_Data_4:
84     return 4;
85   case FK_SecRel_8:
86   case FK_Data_8:
87     return 8;
88   default:
89     llvm_unreachable("Unknown fixup kind!");
90   }
91 }
92 
93 void AMDGPUAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
94                                   unsigned DataSize, uint64_t Value,
95                                   bool IsPCRel) const {
96 
97   switch ((unsigned)Fixup.getKind()) {
98     case AMDGPU::fixup_si_sopp_br: {
99       uint16_t *Dst = (uint16_t*)(Data + Fixup.getOffset());
100       *Dst = (Value - 4) / 4;
101       break;
102     }
103 
104     case AMDGPU::fixup_si_rodata: {
105       uint32_t *Dst = (uint32_t*)(Data + Fixup.getOffset());
106       // We emit constant data at the end of the text section and generate its
107       // address using the following code sequence:
108       // s_getpc_b64 s[0:1]
109       // s_add_u32 s0, s0, $symbol
110       // s_addc_u32 s1, s1, 0
111       //
112       // s_getpc_b64 returns the address of the s_add_u32 instruction and then
113       // the fixup replaces $symbol with a literal constant, which is a
114       // pc-relative  offset from the encoding of the $symbol operand to the
115       // constant data.
116       //
117       // What we want here is an offset from the start of the s_add_u32
118       // instruction to the constant data, but since the encoding of $symbol
119       // starts 4 bytes after the start of the add instruction, we end up
120       // with an offset that is 4 bytes too small.  This requires us to
121       // add 4 to the fixup value before applying it.
122       *Dst = Value + 4;
123       break;
124     }
125     default: {
126       // FIXME: Copied from AArch64
127       unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
128       if (!Value)
129         return; // Doesn't change encoding.
130       MCFixupKindInfo Info = getFixupKindInfo(Fixup.getKind());
131 
132       // Shift the value into position.
133       Value <<= Info.TargetOffset;
134 
135       unsigned Offset = Fixup.getOffset();
136       assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!");
137 
138       // For each byte of the fragment that the fixup touches, mask in the
139       // bits from the fixup value.
140       for (unsigned i = 0; i != NumBytes; ++i)
141         Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
142     }
143   }
144 }
145 
146 const MCFixupKindInfo &AMDGPUAsmBackend::getFixupKindInfo(
147                                                        MCFixupKind Kind) const {
148   const static MCFixupKindInfo Infos[AMDGPU::NumTargetFixupKinds] = {
149     // name                   offset bits  flags
150     { "fixup_si_sopp_br",     0,     16,   MCFixupKindInfo::FKF_IsPCRel },
151     { "fixup_si_rodata",      0,     32,   MCFixupKindInfo::FKF_IsPCRel }
152   };
153 
154   if (Kind < FirstTargetFixupKind)
155     return MCAsmBackend::getFixupKindInfo(Kind);
156 
157   return Infos[Kind - FirstTargetFixupKind];
158 }
159 
160 bool AMDGPUAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
161   OW->WriteZeros(Count);
162 
163   return true;
164 }
165 
166 //===----------------------------------------------------------------------===//
167 // ELFAMDGPUAsmBackend class
168 //===----------------------------------------------------------------------===//
169 
170 namespace {
171 
172 class ELFAMDGPUAsmBackend : public AMDGPUAsmBackend {
173   bool Is64Bit;
174 
175 public:
176   ELFAMDGPUAsmBackend(const Target &T, bool Is64Bit) :
177       AMDGPUAsmBackend(T), Is64Bit(Is64Bit) { }
178 
179   MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
180     return createAMDGPUELFObjectWriter(Is64Bit, OS);
181   }
182 };
183 
184 } // end anonymous namespace
185 
186 MCAsmBackend *llvm::createAMDGPUAsmBackend(const Target &T,
187                                            const MCRegisterInfo &MRI,
188                                            const Triple &TT, StringRef CPU) {
189   Triple TargetTriple(TT);
190 
191   // Use 64-bit ELF for amdgcn
192   return new ELFAMDGPUAsmBackend(T, TargetTriple.getArch() == Triple::amdgcn);
193 }
194