1 //===-- GCNHazardRecognizers.h - GCN Hazard Recognizers ---------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines hazard recognizers for scheduling on GCN processors.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AMDGPUHAZARDRECOGNIZERS_H
15 #define LLVM_LIB_TARGET_AMDGPUHAZARDRECOGNIZERS_H
16 
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
19 #include <list>
20 
21 namespace llvm {
22 
23 class MachineFunction;
24 class MachineInstr;
25 class ScheduleDAG;
26 class SIInstrInfo;
27 class SISubtarget;
28 
29 class GCNHazardRecognizer final : public ScheduleHazardRecognizer {
30   // This variable stores the instruction that has been emitted this cycle. It
31   // will be added to EmittedInstrs, when AdvanceCycle() or RecedeCycle() is
32   // called.
33   MachineInstr *CurrCycleInstr;
34   std::list<MachineInstr*> EmittedInstrs;
35   const MachineFunction &MF;
36   const SISubtarget &ST;
37 
38   int getWaitStatesSinceDef(unsigned Reg,
39                             function_ref<bool(MachineInstr *)> IsHazardDef =
40                                 [](MachineInstr *) { return true; });
41   int getWaitStatesSinceSetReg(function_ref<bool(MachineInstr *)> IsHazard);
42 
43   int checkSMEMSoftClauseHazards(MachineInstr *SMEM);
44   int checkSMRDHazards(MachineInstr *SMRD);
45   int checkVMEMHazards(MachineInstr* VMEM);
46   int checkDPPHazards(MachineInstr *DPP);
47   int checkDivFMasHazards(MachineInstr *DivFMas);
48   int checkGetRegHazards(MachineInstr *GetRegInstr);
49 public:
50   GCNHazardRecognizer(const MachineFunction &MF);
51   // We can only issue one instruction per cycle.
52   bool atIssueLimit() const override { return true; }
53   void EmitInstruction(SUnit *SU) override;
54   void EmitInstruction(MachineInstr *MI) override;
55   HazardType getHazardType(SUnit *SU, int Stalls) override;
56   void EmitNoop() override;
57   unsigned PreEmitNoops(SUnit *SU) override;
58   unsigned PreEmitNoops(MachineInstr *) override;
59   void AdvanceCycle() override;
60   void RecedeCycle() override;
61 };
62 
63 } // end namespace llvm
64 
65 #endif //LLVM_LIB_TARGET_AMDGPUHAZARDRECOGNIZERS_H
66