1 //=======- GCNDPPCombine.cpp - optimization for DPP instructions ---==========//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 // The pass combines V_MOV_B32_dpp instruction with its VALU uses as a DPP src0
9 // operand. If any of the use instruction cannot be combined with the mov the
10 // whole sequence is reverted.
11 //
12 // $old = ...
13 // $dpp_value = V_MOV_B32_dpp $old, $vgpr_to_be_read_from_other_lane,
14 //                            dpp_controls..., $row_mask, $bank_mask, $bound_ctrl
15 // $res = VALU $dpp_value [, src1]
16 //
17 // to
18 //
19 // $res = VALU_DPP $combined_old, $vgpr_to_be_read_from_other_lane, [src1,]
20 //                 dpp_controls..., $row_mask, $bank_mask, $combined_bound_ctrl
21 //
22 // Combining rules :
23 //
24 // if $row_mask and $bank_mask are fully enabled (0xF) and
25 //    $bound_ctrl==DPP_BOUND_ZERO or $old==0
26 // -> $combined_old = undef,
27 //    $combined_bound_ctrl = DPP_BOUND_ZERO
28 //
29 // if the VALU op is binary and
30 //    $bound_ctrl==DPP_BOUND_OFF and
31 //    $old==identity value (immediate) for the VALU op
32 // -> $combined_old = src1,
33 //    $combined_bound_ctrl = DPP_BOUND_OFF
34 //
35 // Otherwise cancel.
36 //
37 // The mov_dpp instruction should reside in the same BB as all its uses
38 //===----------------------------------------------------------------------===//
39 
40 #include "AMDGPU.h"
41 #include "GCNSubtarget.h"
42 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
43 #include "llvm/ADT/Statistic.h"
44 #include "llvm/CodeGen/MachineFunctionPass.h"
45 
46 using namespace llvm;
47 
48 #define DEBUG_TYPE "gcn-dpp-combine"
49 
50 STATISTIC(NumDPPMovsCombined, "Number of DPP moves combined.");
51 
52 namespace {
53 
54 class GCNDPPCombine : public MachineFunctionPass {
55   MachineRegisterInfo *MRI;
56   const SIInstrInfo *TII;
57   const GCNSubtarget *ST;
58 
59   using RegSubRegPair = TargetInstrInfo::RegSubRegPair;
60 
61   MachineOperand *getOldOpndValue(MachineOperand &OldOpnd) const;
62 
63   MachineInstr *createDPPInst(MachineInstr &OrigMI, MachineInstr &MovMI,
64                               RegSubRegPair CombOldVGPR,
65                               MachineOperand *OldOpnd, bool CombBCZ,
66                               bool IsShrinkable) const;
67 
68   MachineInstr *createDPPInst(MachineInstr &OrigMI, MachineInstr &MovMI,
69                               RegSubRegPair CombOldVGPR, bool CombBCZ,
70                               bool IsShrinkable) const;
71 
72   bool hasNoImmOrEqual(MachineInstr &MI,
73                        unsigned OpndName,
74                        int64_t Value,
75                        int64_t Mask = -1) const;
76 
77   bool combineDPPMov(MachineInstr &MI) const;
78 
79 public:
80   static char ID;
81 
82   GCNDPPCombine() : MachineFunctionPass(ID) {
83     initializeGCNDPPCombinePass(*PassRegistry::getPassRegistry());
84   }
85 
86   bool runOnMachineFunction(MachineFunction &MF) override;
87 
88   StringRef getPassName() const override { return "GCN DPP Combine"; }
89 
90   void getAnalysisUsage(AnalysisUsage &AU) const override {
91     AU.setPreservesCFG();
92     MachineFunctionPass::getAnalysisUsage(AU);
93   }
94 
95   MachineFunctionProperties getRequiredProperties() const override {
96     return MachineFunctionProperties()
97       .set(MachineFunctionProperties::Property::IsSSA);
98   }
99 
100 private:
101   int getDPPOp(unsigned Op, bool IsShrinkable) const;
102   bool isShrinkable(MachineInstr &MI) const;
103 };
104 
105 } // end anonymous namespace
106 
107 INITIALIZE_PASS(GCNDPPCombine, DEBUG_TYPE, "GCN DPP Combine", false, false)
108 
109 char GCNDPPCombine::ID = 0;
110 
111 char &llvm::GCNDPPCombineID = GCNDPPCombine::ID;
112 
113 FunctionPass *llvm::createGCNDPPCombinePass() {
114   return new GCNDPPCombine();
115 }
116 
117 bool GCNDPPCombine::isShrinkable(MachineInstr &MI) const {
118   unsigned Op = MI.getOpcode();
119   if (!TII->isVOP3(Op)) {
120     return false;
121   }
122   if (!TII->hasVALU32BitEncoding(Op)) {
123     LLVM_DEBUG(dbgs() << "  Inst hasn't e32 equivalent\n");
124     return false;
125   }
126   if (const auto *SDst = TII->getNamedOperand(MI, AMDGPU::OpName::sdst)) {
127     // Give up if there are any uses of the carry-out from instructions like
128     // V_ADD_CO_U32. The shrunken form of the instruction would write it to vcc
129     // instead of to a virtual register.
130     if (!MRI->use_nodbg_empty(SDst->getReg()))
131       return false;
132   }
133   // check if other than abs|neg modifiers are set (opsel for example)
134   const int64_t Mask = ~(SISrcMods::ABS | SISrcMods::NEG);
135   if (!hasNoImmOrEqual(MI, AMDGPU::OpName::src0_modifiers, 0, Mask) ||
136       !hasNoImmOrEqual(MI, AMDGPU::OpName::src1_modifiers, 0, Mask) ||
137       !hasNoImmOrEqual(MI, AMDGPU::OpName::clamp, 0) ||
138       !hasNoImmOrEqual(MI, AMDGPU::OpName::omod, 0)) {
139     LLVM_DEBUG(dbgs() << "  Inst has non-default modifiers\n");
140     return false;
141   }
142   return true;
143 }
144 
145 int GCNDPPCombine::getDPPOp(unsigned Op, bool IsShrinkable) const {
146   int DPP32 = AMDGPU::getDPPOp32(Op);
147   if (IsShrinkable) {
148     assert(DPP32 == -1);
149     int E32 = AMDGPU::getVOPe32(Op);
150     DPP32 = (E32 == -1) ? -1 : AMDGPU::getDPPOp32(E32);
151   }
152   if (DPP32 != -1 && TII->pseudoToMCOpcode(DPP32) != -1)
153     return DPP32;
154   int DPP64 = -1;
155   if (ST->hasVOP3DPP())
156     DPP64 = AMDGPU::getDPPOp64(Op);
157   if (DPP64 != -1 && TII->pseudoToMCOpcode(DPP64) != -1)
158     return DPP64;
159   return -1;
160 }
161 
162 // tracks the register operand definition and returns:
163 //   1. immediate operand used to initialize the register if found
164 //   2. nullptr if the register operand is undef
165 //   3. the operand itself otherwise
166 MachineOperand *GCNDPPCombine::getOldOpndValue(MachineOperand &OldOpnd) const {
167   auto *Def = getVRegSubRegDef(getRegSubRegPair(OldOpnd), *MRI);
168   if (!Def)
169     return nullptr;
170 
171   switch(Def->getOpcode()) {
172   default: break;
173   case AMDGPU::IMPLICIT_DEF:
174     return nullptr;
175   case AMDGPU::COPY:
176   case AMDGPU::V_MOV_B32_e32:
177   case AMDGPU::V_MOV_B64_PSEUDO:
178   case AMDGPU::V_MOV_B64_e32:
179   case AMDGPU::V_MOV_B64_e64: {
180     auto &Op1 = Def->getOperand(1);
181     if (Op1.isImm())
182       return &Op1;
183     break;
184   }
185   }
186   return &OldOpnd;
187 }
188 
189 MachineInstr *GCNDPPCombine::createDPPInst(MachineInstr &OrigMI,
190                                            MachineInstr &MovMI,
191                                            RegSubRegPair CombOldVGPR,
192                                            bool CombBCZ,
193                                            bool IsShrinkable) const {
194   assert(MovMI.getOpcode() == AMDGPU::V_MOV_B32_dpp ||
195          MovMI.getOpcode() == AMDGPU::V_MOV_B64_dpp ||
196          MovMI.getOpcode() == AMDGPU::V_MOV_B64_DPP_PSEUDO);
197 
198   bool HasVOP3DPP = ST->hasVOP3DPP();
199   auto OrigOp = OrigMI.getOpcode();
200   auto DPPOp = getDPPOp(OrigOp, IsShrinkable);
201   if (DPPOp == -1) {
202     LLVM_DEBUG(dbgs() << "  failed: no DPP opcode\n");
203     return nullptr;
204   }
205 
206   auto DPPInst = BuildMI(*OrigMI.getParent(), OrigMI,
207                          OrigMI.getDebugLoc(), TII->get(DPPOp))
208     .setMIFlags(OrigMI.getFlags());
209 
210   bool Fail = false;
211   do {
212     int NumOperands = 0;
213     if (auto *Dst = TII->getNamedOperand(OrigMI, AMDGPU::OpName::vdst)) {
214       DPPInst.add(*Dst);
215       ++NumOperands;
216     }
217     if (auto *SDst = TII->getNamedOperand(OrigMI, AMDGPU::OpName::sdst)) {
218       if (TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, SDst)) {
219         DPPInst.add(*SDst);
220         ++NumOperands;
221       }
222       // If we shrunk a 64bit vop3b to 32bits, just ignore the sdst
223     }
224 
225     const int OldIdx = AMDGPU::getNamedOperandIdx(DPPOp, AMDGPU::OpName::old);
226     if (OldIdx != -1) {
227       assert(OldIdx == NumOperands);
228       assert(isOfRegClass(
229           CombOldVGPR,
230           *MRI->getRegClass(
231               TII->getNamedOperand(MovMI, AMDGPU::OpName::vdst)->getReg()),
232           *MRI));
233       auto *Def = getVRegSubRegDef(CombOldVGPR, *MRI);
234       DPPInst.addReg(CombOldVGPR.Reg, Def ? 0 : RegState::Undef,
235                      CombOldVGPR.SubReg);
236       ++NumOperands;
237     } else {
238       // TODO: this discards MAC/FMA instructions for now, let's add it later
239       LLVM_DEBUG(dbgs() << "  failed: no old operand in DPP instruction,"
240                            " TBD\n");
241       Fail = true;
242       break;
243     }
244 
245     if (auto *Mod0 = TII->getNamedOperand(OrigMI,
246                                           AMDGPU::OpName::src0_modifiers)) {
247       assert(NumOperands == AMDGPU::getNamedOperandIdx(DPPOp,
248                                           AMDGPU::OpName::src0_modifiers));
249       assert(HasVOP3DPP ||
250              (0LL == (Mod0->getImm() & ~(SISrcMods::ABS | SISrcMods::NEG))));
251       DPPInst.addImm(Mod0->getImm());
252       ++NumOperands;
253     } else if (AMDGPU::getNamedOperandIdx(DPPOp,
254                    AMDGPU::OpName::src0_modifiers) != -1) {
255       DPPInst.addImm(0);
256       ++NumOperands;
257     }
258     auto *Src0 = TII->getNamedOperand(MovMI, AMDGPU::OpName::src0);
259     assert(Src0);
260     if (!TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src0)) {
261       LLVM_DEBUG(dbgs() << "  failed: src0 is illegal\n");
262       Fail = true;
263       break;
264     }
265     DPPInst.add(*Src0);
266     DPPInst->getOperand(NumOperands).setIsKill(false);
267     ++NumOperands;
268 
269     if (auto *Mod1 = TII->getNamedOperand(OrigMI,
270                                           AMDGPU::OpName::src1_modifiers)) {
271       assert(NumOperands == AMDGPU::getNamedOperandIdx(DPPOp,
272                                           AMDGPU::OpName::src1_modifiers));
273       assert(HasVOP3DPP ||
274              (0LL == (Mod1->getImm() & ~(SISrcMods::ABS | SISrcMods::NEG))));
275       DPPInst.addImm(Mod1->getImm());
276       ++NumOperands;
277     } else if (AMDGPU::getNamedOperandIdx(DPPOp,
278                    AMDGPU::OpName::src1_modifiers) != -1) {
279       DPPInst.addImm(0);
280       ++NumOperands;
281     }
282     auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1);
283     if (Src1) {
284       if (!TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src1)) {
285         LLVM_DEBUG(dbgs() << "  failed: src1 is illegal\n");
286         Fail = true;
287         break;
288       }
289       DPPInst.add(*Src1);
290       ++NumOperands;
291     }
292     if (auto *Mod2 =
293             TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2_modifiers)) {
294       assert(NumOperands ==
295              AMDGPU::getNamedOperandIdx(DPPOp, AMDGPU::OpName::src2_modifiers));
296       assert(HasVOP3DPP ||
297              (0LL == (Mod2->getImm() & ~(SISrcMods::ABS | SISrcMods::NEG))));
298       DPPInst.addImm(Mod2->getImm());
299       ++NumOperands;
300     }
301     auto *Src2 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2);
302     if (Src2) {
303       if (!TII->getNamedOperand(*DPPInst.getInstr(), AMDGPU::OpName::src2) ||
304           !TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src2)) {
305         LLVM_DEBUG(dbgs() << "  failed: src2 is illegal\n");
306         Fail = true;
307         break;
308       }
309       DPPInst.add(*Src2);
310       ++NumOperands;
311     }
312     if (HasVOP3DPP) {
313       auto *ClampOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::clamp);
314       if (ClampOpr &&
315           AMDGPU::getNamedOperandIdx(DPPOp, AMDGPU::OpName::clamp) != -1) {
316         DPPInst.addImm(ClampOpr->getImm());
317       }
318       auto *VdstInOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::vdst_in);
319       if (VdstInOpr &&
320           AMDGPU::getNamedOperandIdx(DPPOp, AMDGPU::OpName::vdst_in) != -1) {
321         DPPInst.add(*VdstInOpr);
322       }
323       auto *OmodOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::omod);
324       if (OmodOpr &&
325           AMDGPU::getNamedOperandIdx(DPPOp, AMDGPU::OpName::omod) != -1) {
326         DPPInst.addImm(OmodOpr->getImm());
327       }
328       // Validate OP_SEL has to be set to all 0 and OP_SEL_HI has to be set to
329       // all 1.
330       if (auto *OpSelOpr =
331               TII->getNamedOperand(OrigMI, AMDGPU::OpName::op_sel)) {
332         auto OpSel = OpSelOpr->getImm();
333         if (OpSel != 0) {
334           LLVM_DEBUG(dbgs() << "  failed: op_sel must be zero\n");
335           Fail = true;
336           break;
337         }
338         if (AMDGPU::getNamedOperandIdx(DPPOp, AMDGPU::OpName::op_sel) != -1)
339           DPPInst.addImm(OpSel);
340       }
341       if (auto *OpSelHiOpr =
342               TII->getNamedOperand(OrigMI, AMDGPU::OpName::op_sel_hi)) {
343         auto OpSelHi = OpSelHiOpr->getImm();
344         // Only vop3p has op_sel_hi, and all vop3p have 3 operands, so check
345         // the bitmask for 3 op_sel_hi bits set
346         assert(Src2 && "Expected vop3p with 3 operands");
347         if (OpSelHi != 7) {
348           LLVM_DEBUG(dbgs() << "  failed: op_sel_hi must be all set to one\n");
349           Fail = true;
350           break;
351         }
352         if (AMDGPU::getNamedOperandIdx(DPPOp, AMDGPU::OpName::op_sel_hi) != -1)
353           DPPInst.addImm(OpSelHi);
354       }
355       auto *NegOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::neg_lo);
356       if (NegOpr &&
357           AMDGPU::getNamedOperandIdx(DPPOp, AMDGPU::OpName::neg_lo) != -1) {
358         DPPInst.addImm(NegOpr->getImm());
359       }
360       auto *NegHiOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::neg_hi);
361       if (NegHiOpr &&
362           AMDGPU::getNamedOperandIdx(DPPOp, AMDGPU::OpName::neg_hi) != -1) {
363         DPPInst.addImm(NegHiOpr->getImm());
364       }
365     }
366     DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::dpp_ctrl));
367     DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::row_mask));
368     DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::bank_mask));
369     DPPInst.addImm(CombBCZ ? 1 : 0);
370   } while (false);
371 
372   if (Fail) {
373     DPPInst.getInstr()->eraseFromParent();
374     return nullptr;
375   }
376   LLVM_DEBUG(dbgs() << "  combined:  " << *DPPInst.getInstr());
377   return DPPInst.getInstr();
378 }
379 
380 static bool isIdentityValue(unsigned OrigMIOp, MachineOperand *OldOpnd) {
381   assert(OldOpnd->isImm());
382   switch (OrigMIOp) {
383   default: break;
384   case AMDGPU::V_ADD_U32_e32:
385   case AMDGPU::V_ADD_U32_e64:
386   case AMDGPU::V_ADD_CO_U32_e32:
387   case AMDGPU::V_ADD_CO_U32_e64:
388   case AMDGPU::V_OR_B32_e32:
389   case AMDGPU::V_OR_B32_e64:
390   case AMDGPU::V_SUBREV_U32_e32:
391   case AMDGPU::V_SUBREV_U32_e64:
392   case AMDGPU::V_SUBREV_CO_U32_e32:
393   case AMDGPU::V_SUBREV_CO_U32_e64:
394   case AMDGPU::V_MAX_U32_e32:
395   case AMDGPU::V_MAX_U32_e64:
396   case AMDGPU::V_XOR_B32_e32:
397   case AMDGPU::V_XOR_B32_e64:
398     if (OldOpnd->getImm() == 0)
399       return true;
400     break;
401   case AMDGPU::V_AND_B32_e32:
402   case AMDGPU::V_AND_B32_e64:
403   case AMDGPU::V_MIN_U32_e32:
404   case AMDGPU::V_MIN_U32_e64:
405     if (static_cast<uint32_t>(OldOpnd->getImm()) ==
406         std::numeric_limits<uint32_t>::max())
407       return true;
408     break;
409   case AMDGPU::V_MIN_I32_e32:
410   case AMDGPU::V_MIN_I32_e64:
411     if (static_cast<int32_t>(OldOpnd->getImm()) ==
412         std::numeric_limits<int32_t>::max())
413       return true;
414     break;
415   case AMDGPU::V_MAX_I32_e32:
416   case AMDGPU::V_MAX_I32_e64:
417     if (static_cast<int32_t>(OldOpnd->getImm()) ==
418         std::numeric_limits<int32_t>::min())
419       return true;
420     break;
421   case AMDGPU::V_MUL_I32_I24_e32:
422   case AMDGPU::V_MUL_I32_I24_e64:
423   case AMDGPU::V_MUL_U32_U24_e32:
424   case AMDGPU::V_MUL_U32_U24_e64:
425     if (OldOpnd->getImm() == 1)
426       return true;
427     break;
428   }
429   return false;
430 }
431 
432 MachineInstr *GCNDPPCombine::createDPPInst(
433     MachineInstr &OrigMI, MachineInstr &MovMI, RegSubRegPair CombOldVGPR,
434     MachineOperand *OldOpndValue, bool CombBCZ, bool IsShrinkable) const {
435   assert(CombOldVGPR.Reg);
436   if (!CombBCZ && OldOpndValue && OldOpndValue->isImm()) {
437     auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1);
438     if (!Src1 || !Src1->isReg()) {
439       LLVM_DEBUG(dbgs() << "  failed: no src1 or it isn't a register\n");
440       return nullptr;
441     }
442     if (!isIdentityValue(OrigMI.getOpcode(), OldOpndValue)) {
443       LLVM_DEBUG(dbgs() << "  failed: old immediate isn't an identity\n");
444       return nullptr;
445     }
446     CombOldVGPR = getRegSubRegPair(*Src1);
447     auto MovDst = TII->getNamedOperand(MovMI, AMDGPU::OpName::vdst);
448     const TargetRegisterClass *RC = MRI->getRegClass(MovDst->getReg());
449     if (!isOfRegClass(CombOldVGPR, *RC, *MRI)) {
450       LLVM_DEBUG(dbgs() << "  failed: src1 has wrong register class\n");
451       return nullptr;
452     }
453   }
454   return createDPPInst(OrigMI, MovMI, CombOldVGPR, CombBCZ, IsShrinkable);
455 }
456 
457 // returns true if MI doesn't have OpndName immediate operand or the
458 // operand has Value
459 bool GCNDPPCombine::hasNoImmOrEqual(MachineInstr &MI, unsigned OpndName,
460                                     int64_t Value, int64_t Mask) const {
461   auto *Imm = TII->getNamedOperand(MI, OpndName);
462   if (!Imm)
463     return true;
464 
465   assert(Imm->isImm());
466   return (Imm->getImm() & Mask) == Value;
467 }
468 
469 bool GCNDPPCombine::combineDPPMov(MachineInstr &MovMI) const {
470   assert(MovMI.getOpcode() == AMDGPU::V_MOV_B32_dpp ||
471          MovMI.getOpcode() == AMDGPU::V_MOV_B64_dpp ||
472          MovMI.getOpcode() == AMDGPU::V_MOV_B64_DPP_PSEUDO);
473   LLVM_DEBUG(dbgs() << "\nDPP combine: " << MovMI);
474 
475   auto *DstOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::vdst);
476   assert(DstOpnd && DstOpnd->isReg());
477   auto DPPMovReg = DstOpnd->getReg();
478   if (DPPMovReg.isPhysical()) {
479     LLVM_DEBUG(dbgs() << "  failed: dpp move writes physreg\n");
480     return false;
481   }
482   if (execMayBeModifiedBeforeAnyUse(*MRI, DPPMovReg, MovMI)) {
483     LLVM_DEBUG(dbgs() << "  failed: EXEC mask should remain the same"
484                          " for all uses\n");
485     return false;
486   }
487 
488   if (MovMI.getOpcode() == AMDGPU::V_MOV_B64_DPP_PSEUDO ||
489       MovMI.getOpcode() == AMDGPU::V_MOV_B64_dpp) {
490     auto *DppCtrl = TII->getNamedOperand(MovMI, AMDGPU::OpName::dpp_ctrl);
491     assert(DppCtrl && DppCtrl->isImm());
492     if (!AMDGPU::isLegal64BitDPPControl(DppCtrl->getImm())) {
493       LLVM_DEBUG(dbgs() << "  failed: 64 bit dpp move uses unsupported"
494                            " control value\n");
495       // Let it split, then control may become legal.
496       return false;
497     }
498   }
499 
500   auto *RowMaskOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::row_mask);
501   assert(RowMaskOpnd && RowMaskOpnd->isImm());
502   auto *BankMaskOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::bank_mask);
503   assert(BankMaskOpnd && BankMaskOpnd->isImm());
504   const bool MaskAllLanes = RowMaskOpnd->getImm() == 0xF &&
505                             BankMaskOpnd->getImm() == 0xF;
506 
507   auto *BCZOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::bound_ctrl);
508   assert(BCZOpnd && BCZOpnd->isImm());
509   bool BoundCtrlZero = BCZOpnd->getImm();
510 
511   auto *OldOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::old);
512   auto *SrcOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::src0);
513   assert(OldOpnd && OldOpnd->isReg());
514   assert(SrcOpnd && SrcOpnd->isReg());
515   if (OldOpnd->getReg().isPhysical() || SrcOpnd->getReg().isPhysical()) {
516     LLVM_DEBUG(dbgs() << "  failed: dpp move reads physreg\n");
517     return false;
518   }
519 
520   auto * const OldOpndValue = getOldOpndValue(*OldOpnd);
521   // OldOpndValue is either undef (IMPLICIT_DEF) or immediate or something else
522   // We could use: assert(!OldOpndValue || OldOpndValue->isImm())
523   // but the third option is used to distinguish undef from non-immediate
524   // to reuse IMPLICIT_DEF instruction later
525   assert(!OldOpndValue || OldOpndValue->isImm() || OldOpndValue == OldOpnd);
526 
527   bool CombBCZ = false;
528 
529   if (MaskAllLanes && BoundCtrlZero) { // [1]
530     CombBCZ = true;
531   } else {
532     if (!OldOpndValue || !OldOpndValue->isImm()) {
533       LLVM_DEBUG(dbgs() << "  failed: the DPP mov isn't combinable\n");
534       return false;
535     }
536 
537     if (OldOpndValue->getImm() == 0) {
538       if (MaskAllLanes) {
539         assert(!BoundCtrlZero); // by check [1]
540         CombBCZ = true;
541       }
542     } else if (BoundCtrlZero) {
543       assert(!MaskAllLanes); // by check [1]
544       LLVM_DEBUG(dbgs() <<
545         "  failed: old!=0 and bctrl:0 and not all lanes isn't combinable\n");
546       return false;
547     }
548   }
549 
550   LLVM_DEBUG(dbgs() << "  old=";
551     if (!OldOpndValue)
552       dbgs() << "undef";
553     else
554       dbgs() << *OldOpndValue;
555     dbgs() << ", bound_ctrl=" << CombBCZ << '\n');
556 
557   SmallVector<MachineInstr*, 4> OrigMIs, DPPMIs;
558   DenseMap<MachineInstr*, SmallVector<unsigned, 4>> RegSeqWithOpNos;
559   auto CombOldVGPR = getRegSubRegPair(*OldOpnd);
560   // try to reuse previous old reg if its undefined (IMPLICIT_DEF)
561   if (CombBCZ && OldOpndValue) { // CombOldVGPR should be undef
562     const TargetRegisterClass *RC = MRI->getRegClass(DPPMovReg);
563     CombOldVGPR = RegSubRegPair(
564       MRI->createVirtualRegister(RC));
565     auto UndefInst = BuildMI(*MovMI.getParent(), MovMI, MovMI.getDebugLoc(),
566                              TII->get(AMDGPU::IMPLICIT_DEF), CombOldVGPR.Reg);
567     DPPMIs.push_back(UndefInst.getInstr());
568   }
569 
570   OrigMIs.push_back(&MovMI);
571   bool Rollback = true;
572   SmallVector<MachineOperand*, 16> Uses;
573 
574   for (auto &Use : MRI->use_nodbg_operands(DPPMovReg)) {
575     Uses.push_back(&Use);
576   }
577 
578   while (!Uses.empty()) {
579     MachineOperand *Use = Uses.pop_back_val();
580     Rollback = true;
581 
582     auto &OrigMI = *Use->getParent();
583     LLVM_DEBUG(dbgs() << "  try: " << OrigMI);
584 
585     auto OrigOp = OrigMI.getOpcode();
586     if (OrigOp == AMDGPU::REG_SEQUENCE) {
587       Register FwdReg = OrigMI.getOperand(0).getReg();
588       unsigned FwdSubReg = 0;
589 
590       if (execMayBeModifiedBeforeAnyUse(*MRI, FwdReg, OrigMI)) {
591         LLVM_DEBUG(dbgs() << "  failed: EXEC mask should remain the same"
592                              " for all uses\n");
593         break;
594       }
595 
596       unsigned OpNo, E = OrigMI.getNumOperands();
597       for (OpNo = 1; OpNo < E; OpNo += 2) {
598         if (OrigMI.getOperand(OpNo).getReg() == DPPMovReg) {
599           FwdSubReg = OrigMI.getOperand(OpNo + 1).getImm();
600           break;
601         }
602       }
603 
604       if (!FwdSubReg)
605         break;
606 
607       for (auto &Op : MRI->use_nodbg_operands(FwdReg)) {
608         if (Op.getSubReg() == FwdSubReg)
609           Uses.push_back(&Op);
610       }
611       RegSeqWithOpNos[&OrigMI].push_back(OpNo);
612       continue;
613     }
614 
615     bool IsShrinkable = isShrinkable(OrigMI);
616     if (!(IsShrinkable ||
617           ((TII->isVOP3P(OrigOp) || TII->isVOPC(OrigOp) ||
618             TII->isVOP3(OrigOp)) &&
619            ST->hasVOP3DPP()) ||
620           TII->isVOP1(OrigOp) || TII->isVOP2(OrigOp))) {
621       LLVM_DEBUG(dbgs() << "  failed: not VOP1/2/3/3P/C\n");
622       break;
623     }
624     if (OrigMI.modifiesRegister(AMDGPU::EXEC, ST->getRegisterInfo())) {
625       LLVM_DEBUG(dbgs() << "  failed: can't combine v_cmpx\n");
626       break;
627     }
628 
629     auto *Src0 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src0);
630     auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1);
631     if (Use != Src0 && !(Use == Src1 && OrigMI.isCommutable())) { // [1]
632       LLVM_DEBUG(dbgs() << "  failed: no suitable operands\n");
633       break;
634     }
635 
636     auto *Src2 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2);
637     assert(Src0 && "Src1 without Src0?");
638     if ((Use == Src0 && ((Src1 && Src1->isIdenticalTo(*Src0)) ||
639                          (Src2 && Src2->isIdenticalTo(*Src0)))) ||
640         (Use == Src1 && (Src1->isIdenticalTo(*Src0) ||
641                          (Src2 && Src2->isIdenticalTo(*Src1))))) {
642       LLVM_DEBUG(
643           dbgs()
644           << "  " << OrigMI
645           << "  failed: DPP register is used more than once per instruction\n");
646       break;
647     }
648 
649     LLVM_DEBUG(dbgs() << "  combining: " << OrigMI);
650     if (Use == Src0) {
651       if (auto *DPPInst = createDPPInst(OrigMI, MovMI, CombOldVGPR,
652                                         OldOpndValue, CombBCZ, IsShrinkable)) {
653         DPPMIs.push_back(DPPInst);
654         Rollback = false;
655       }
656     } else {
657       assert(Use == Src1 && OrigMI.isCommutable()); // by check [1]
658       auto *BB = OrigMI.getParent();
659       auto *NewMI = BB->getParent()->CloneMachineInstr(&OrigMI);
660       BB->insert(OrigMI, NewMI);
661       if (TII->commuteInstruction(*NewMI)) {
662         LLVM_DEBUG(dbgs() << "  commuted:  " << *NewMI);
663         if (auto *DPPInst =
664                 createDPPInst(*NewMI, MovMI, CombOldVGPR, OldOpndValue, CombBCZ,
665                               IsShrinkable)) {
666           DPPMIs.push_back(DPPInst);
667           Rollback = false;
668         }
669       } else
670         LLVM_DEBUG(dbgs() << "  failed: cannot be commuted\n");
671       NewMI->eraseFromParent();
672     }
673     if (Rollback)
674       break;
675     OrigMIs.push_back(&OrigMI);
676   }
677 
678   Rollback |= !Uses.empty();
679 
680   for (auto *MI : *(Rollback? &DPPMIs : &OrigMIs))
681     MI->eraseFromParent();
682 
683   if (!Rollback) {
684     for (auto &S : RegSeqWithOpNos) {
685       if (MRI->use_nodbg_empty(S.first->getOperand(0).getReg())) {
686         S.first->eraseFromParent();
687         continue;
688       }
689       while (!S.second.empty())
690         S.first->getOperand(S.second.pop_back_val()).setIsUndef(true);
691     }
692   }
693 
694   return !Rollback;
695 }
696 
697 bool GCNDPPCombine::runOnMachineFunction(MachineFunction &MF) {
698   ST = &MF.getSubtarget<GCNSubtarget>();
699   if (!ST->hasDPP() || skipFunction(MF.getFunction()))
700     return false;
701 
702   MRI = &MF.getRegInfo();
703   TII = ST->getInstrInfo();
704 
705   bool Changed = false;
706   for (auto &MBB : MF) {
707     for (MachineInstr &MI : llvm::make_early_inc_range(llvm::reverse(MBB))) {
708       if (MI.getOpcode() == AMDGPU::V_MOV_B32_dpp && combineDPPMov(MI)) {
709         Changed = true;
710         ++NumDPPMovsCombined;
711       } else if (MI.getOpcode() == AMDGPU::V_MOV_B64_DPP_PSEUDO ||
712                  MI.getOpcode() == AMDGPU::V_MOV_B64_dpp) {
713         if (ST->has64BitDPP() && combineDPPMov(MI)) {
714           Changed = true;
715           ++NumDPPMovsCombined;
716         } else {
717           auto Split = TII->expandMovDPP64(MI);
718           for (auto M : { Split.first, Split.second }) {
719             if (M && combineDPPMov(*M))
720               ++NumDPPMovsCombined;
721           }
722           Changed = true;
723         }
724       }
725     }
726   }
727   return Changed;
728 }
729