1//===-- EvergreenInstructions.td - EG Instruction defs ----*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// TableGen definitions for instructions which are: 11// - Available to Evergreen and newer VLIW4/VLIW5 GPUs 12// - Available only on Evergreen family GPUs. 13// 14//===----------------------------------------------------------------------===// 15 16def isEG : Predicate< 17 "Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && " 18 "Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && " 19 "!Subtarget->hasCaymanISA()" 20>; 21 22def isEGorCayman : Predicate< 23 "Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||" 24 "Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS" 25>; 26 27//===----------------------------------------------------------------------===// 28// Evergreen / Cayman store instructions 29//===----------------------------------------------------------------------===// 30 31let Predicates = [isEGorCayman] in { 32 33class CF_MEM_RAT_CACHELESS <bits<6> rat_inst, bits<4> rat_id, bits<4> mask, dag ins, 34 string name, list<dag> pattern> 35 : EG_CF_RAT <0x57, rat_inst, rat_id, mask, (outs), ins, 36 "MEM_RAT_CACHELESS "#name, pattern>; 37 38class CF_MEM_RAT <bits<6> rat_inst, bits<4> rat_id, dag ins, string name, 39 list<dag> pattern> 40 : EG_CF_RAT <0x56, rat_inst, rat_id, 0xf /* mask */, (outs), ins, 41 "MEM_RAT "#name, pattern>; 42 43class CF_MEM_RAT_STORE_TYPED<bits<1> has_eop> 44 : CF_MEM_RAT <0x1, ?, (ins R600_Reg128:$rw_gpr, R600_Reg128:$index_gpr, 45 i32imm:$rat_id, InstFlag:$eop), 46 "STORE_TYPED RAT($rat_id) $rw_gpr, $index_gpr" 47 #!if(has_eop, ", $eop", ""), 48 [(int_r600_rat_store_typed R600_Reg128:$rw_gpr, 49 R600_Reg128:$index_gpr, 50 (i32 imm:$rat_id))]>; 51 52def RAT_MSKOR : CF_MEM_RAT <0x11, 0, 53 (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr), 54 "MSKOR $rw_gpr.XW, $index_gpr", 55 [(mskor_global v4i32:$rw_gpr, i32:$index_gpr)] 56> { 57 let eop = 0; 58} 59 60} // End let Predicates = [isEGorCayman] 61 62//===----------------------------------------------------------------------===// 63// Evergreen Only instructions 64//===----------------------------------------------------------------------===// 65 66let Predicates = [isEG] in { 67 68def RECIP_IEEE_eg : RECIP_IEEE_Common<0x86>; 69defm DIV_eg : DIV_Common<RECIP_IEEE_eg>; 70 71def MULLO_INT_eg : MULLO_INT_Common<0x8F>; 72def MULHI_INT_eg : MULHI_INT_Common<0x90>; 73def MULLO_UINT_eg : MULLO_UINT_Common<0x91>; 74def MULHI_UINT_eg : MULHI_UINT_Common<0x92>; 75def RECIP_UINT_eg : RECIP_UINT_Common<0x94>; 76def RECIPSQRT_CLAMPED_eg : RECIPSQRT_CLAMPED_Common<0x87>; 77def EXP_IEEE_eg : EXP_IEEE_Common<0x81>; 78def LOG_IEEE_eg : LOG_IEEE_Common<0x83>; 79def RECIP_CLAMPED_eg : RECIP_CLAMPED_Common<0x84>; 80def RECIPSQRT_IEEE_eg : RECIPSQRT_IEEE_Common<0x89>; 81def : RsqPat<RECIPSQRT_IEEE_eg, f32>; 82def SIN_eg : SIN_Common<0x8D>; 83def COS_eg : COS_Common<0x8E>; 84 85def : POW_Common <LOG_IEEE_eg, EXP_IEEE_eg, MUL>; 86def : Pat<(fsqrt f32:$src), (MUL $src, (RECIPSQRT_CLAMPED_eg $src))>; 87 88//===----------------------------------------------------------------------===// 89// Memory read/write instructions 90//===----------------------------------------------------------------------===// 91 92let usesCustomInserter = 1 in { 93 94// 32-bit store 95def RAT_WRITE_CACHELESS_32_eg : CF_MEM_RAT_CACHELESS <0x2, 0, 0x1, 96 (ins R600_TReg32_X:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop), 97 "STORE_RAW $rw_gpr, $index_gpr, $eop", 98 [(global_store i32:$rw_gpr, i32:$index_gpr)] 99>; 100 101// 64-bit store 102def RAT_WRITE_CACHELESS_64_eg : CF_MEM_RAT_CACHELESS <0x2, 0, 0x3, 103 (ins R600_Reg64:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop), 104 "STORE_RAW $rw_gpr.XY, $index_gpr, $eop", 105 [(global_store v2i32:$rw_gpr, i32:$index_gpr)] 106>; 107 108//128-bit store 109def RAT_WRITE_CACHELESS_128_eg : CF_MEM_RAT_CACHELESS <0x2, 0, 0xf, 110 (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop), 111 "STORE_RAW $rw_gpr.XYZW, $index_gpr, $eop", 112 [(global_store v4i32:$rw_gpr, i32:$index_gpr)] 113>; 114 115def RAT_STORE_TYPED_eg: CF_MEM_RAT_STORE_TYPED<1>; 116 117} // End usesCustomInserter = 1 118 119class VTX_READ_eg <string name, bits<8> buffer_id, dag outs, list<dag> pattern> 120 : VTX_WORD0_eg, VTX_READ<name, buffer_id, outs, pattern> { 121 122 // Static fields 123 let VC_INST = 0; 124 let FETCH_TYPE = 2; 125 let FETCH_WHOLE_QUAD = 0; 126 let BUFFER_ID = buffer_id; 127 let SRC_REL = 0; 128 // XXX: We can infer this field based on the SRC_GPR. This would allow us 129 // to store vertex addresses in any channel, not just X. 130 let SRC_SEL_X = 0; 131 132 let Inst{31-0} = Word0; 133} 134 135class VTX_READ_8_eg <bits<8> buffer_id, list<dag> pattern> 136 : VTX_READ_eg <"VTX_READ_8 $dst_gpr, $src_gpr", buffer_id, 137 (outs R600_TReg32_X:$dst_gpr), pattern> { 138 139 let MEGA_FETCH_COUNT = 1; 140 let DST_SEL_X = 0; 141 let DST_SEL_Y = 7; // Masked 142 let DST_SEL_Z = 7; // Masked 143 let DST_SEL_W = 7; // Masked 144 let DATA_FORMAT = 1; // FMT_8 145} 146 147class VTX_READ_16_eg <bits<8> buffer_id, list<dag> pattern> 148 : VTX_READ_eg <"VTX_READ_16 $dst_gpr, $src_gpr", buffer_id, 149 (outs R600_TReg32_X:$dst_gpr), pattern> { 150 let MEGA_FETCH_COUNT = 2; 151 let DST_SEL_X = 0; 152 let DST_SEL_Y = 7; // Masked 153 let DST_SEL_Z = 7; // Masked 154 let DST_SEL_W = 7; // Masked 155 let DATA_FORMAT = 5; // FMT_16 156 157} 158 159class VTX_READ_32_eg <bits<8> buffer_id, list<dag> pattern> 160 : VTX_READ_eg <"VTX_READ_32 $dst_gpr, $src_gpr", buffer_id, 161 (outs R600_TReg32_X:$dst_gpr), pattern> { 162 163 let MEGA_FETCH_COUNT = 4; 164 let DST_SEL_X = 0; 165 let DST_SEL_Y = 7; // Masked 166 let DST_SEL_Z = 7; // Masked 167 let DST_SEL_W = 7; // Masked 168 let DATA_FORMAT = 0xD; // COLOR_32 169 170 // This is not really necessary, but there were some GPU hangs that appeared 171 // to be caused by ALU instructions in the next instruction group that wrote 172 // to the $src_gpr registers of the VTX_READ. 173 // e.g. 174 // %T3_X<def> = VTX_READ_PARAM_32_eg %T2_X<kill>, 24 175 // %T2_X<def> = MOV %ZERO 176 //Adding this constraint prevents this from happening. 177 let Constraints = "$src_gpr.ptr = $dst_gpr"; 178} 179 180class VTX_READ_64_eg <bits<8> buffer_id, list<dag> pattern> 181 : VTX_READ_eg <"VTX_READ_64 $dst_gpr.XY, $src_gpr", buffer_id, 182 (outs R600_Reg64:$dst_gpr), pattern> { 183 184 let MEGA_FETCH_COUNT = 8; 185 let DST_SEL_X = 0; 186 let DST_SEL_Y = 1; 187 let DST_SEL_Z = 7; 188 let DST_SEL_W = 7; 189 let DATA_FORMAT = 0x1D; // COLOR_32_32 190} 191 192class VTX_READ_128_eg <bits<8> buffer_id, list<dag> pattern> 193 : VTX_READ_eg <"VTX_READ_128 $dst_gpr.XYZW, $src_gpr", buffer_id, 194 (outs R600_Reg128:$dst_gpr), pattern> { 195 196 let MEGA_FETCH_COUNT = 16; 197 let DST_SEL_X = 0; 198 let DST_SEL_Y = 1; 199 let DST_SEL_Z = 2; 200 let DST_SEL_W = 3; 201 let DATA_FORMAT = 0x22; // COLOR_32_32_32_32 202 203 // XXX: Need to force VTX_READ_128 instructions to write to the same register 204 // that holds its buffer address to avoid potential hangs. We can't use 205 // the same constraint as VTX_READ_32_eg, because the $src_gpr.ptr and $dst 206 // registers are different sizes. 207} 208 209//===----------------------------------------------------------------------===// 210// VTX Read from parameter memory space 211//===----------------------------------------------------------------------===// 212 213def VTX_READ_PARAM_8_eg : VTX_READ_8_eg <0, 214 [(set i32:$dst_gpr, (load_param_exti8 ADDRVTX_READ:$src_gpr))] 215>; 216 217def VTX_READ_PARAM_16_eg : VTX_READ_16_eg <0, 218 [(set i32:$dst_gpr, (load_param_exti16 ADDRVTX_READ:$src_gpr))] 219>; 220 221def VTX_READ_PARAM_32_eg : VTX_READ_32_eg <0, 222 [(set i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))] 223>; 224 225def VTX_READ_PARAM_64_eg : VTX_READ_64_eg <0, 226 [(set v2i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))] 227>; 228 229def VTX_READ_PARAM_128_eg : VTX_READ_128_eg <0, 230 [(set v4i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))] 231>; 232 233//===----------------------------------------------------------------------===// 234// VTX Read from global memory space 235//===----------------------------------------------------------------------===// 236 237// 8-bit reads 238def VTX_READ_GLOBAL_8_eg : VTX_READ_8_eg <1, 239 [(set i32:$dst_gpr, (az_extloadi8_global ADDRVTX_READ:$src_gpr))] 240>; 241 242def VTX_READ_GLOBAL_16_eg : VTX_READ_16_eg <1, 243 [(set i32:$dst_gpr, (az_extloadi16_global ADDRVTX_READ:$src_gpr))] 244>; 245 246// 32-bit reads 247def VTX_READ_GLOBAL_32_eg : VTX_READ_32_eg <1, 248 [(set i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))] 249>; 250 251// 64-bit reads 252def VTX_READ_GLOBAL_64_eg : VTX_READ_64_eg <1, 253 [(set v2i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))] 254>; 255 256// 128-bit reads 257def VTX_READ_GLOBAL_128_eg : VTX_READ_128_eg <1, 258 [(set v4i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))] 259>; 260 261} // End Predicates = [isEG] 262 263//===----------------------------------------------------------------------===// 264// Evergreen / Cayman Instructions 265//===----------------------------------------------------------------------===// 266 267let Predicates = [isEGorCayman] in { 268 269// Should be predicated on FeatureFP64 270// def FMA_64 : R600_3OP < 271// 0xA, "FMA_64", 272// [(set f64:$dst, (fma f64:$src0, f64:$src1, f64:$src2))] 273// >; 274 275// BFE_UINT - bit_extract, an optimization for mask and shift 276// Src0 = Input 277// Src1 = Offset 278// Src2 = Width 279// 280// bit_extract = (Input << (32 - Offset - Width)) >> (32 - Width) 281// 282// Example Usage: 283// (Offset, Width) 284// 285// (0, 8) = (Input << 24) >> 24 = (Input & 0xff) >> 0 286// (8, 8) = (Input << 16) >> 24 = (Input & 0xffff) >> 8 287// (16, 8) = (Input << 8) >> 24 = (Input & 0xffffff) >> 16 288// (24, 8) = (Input << 0) >> 24 = (Input & 0xffffffff) >> 24 289def BFE_UINT_eg : R600_3OP <0x4, "BFE_UINT", 290 [(set i32:$dst, (AMDGPUbfe_u32 i32:$src0, i32:$src1, i32:$src2))], 291 VecALU 292>; 293 294def BFE_INT_eg : R600_3OP <0x5, "BFE_INT", 295 [(set i32:$dst, (AMDGPUbfe_i32 i32:$src0, i32:$src1, i32:$src2))], 296 VecALU 297>; 298 299def : BFEPattern <BFE_UINT_eg, MOV_IMM_I32>; 300 301def BFI_INT_eg : R600_3OP <0x06, "BFI_INT", 302 [(set i32:$dst, (AMDGPUbfi i32:$src0, i32:$src1, i32:$src2))], 303 VecALU 304>; 305 306def : Pat<(i32 (sext_inreg i32:$src, i1)), 307 (BFE_INT_eg i32:$src, (i32 ZERO), (i32 ONE_INT))>; 308def : Pat<(i32 (sext_inreg i32:$src, i8)), 309 (BFE_INT_eg i32:$src, (i32 ZERO), (MOV_IMM_I32 8))>; 310def : Pat<(i32 (sext_inreg i32:$src, i16)), 311 (BFE_INT_eg i32:$src, (i32 ZERO), (MOV_IMM_I32 16))>; 312 313defm : BFIPatterns <BFI_INT_eg, MOV_IMM_I32, R600_Reg64>; 314 315def BFM_INT_eg : R600_2OP <0xA0, "BFM_INT", 316 [(set i32:$dst, (AMDGPUbfm i32:$src0, i32:$src1))], 317 VecALU 318>; 319 320def MULADD_UINT24_eg : R600_3OP <0x10, "MULADD_UINT24", 321 [(set i32:$dst, (AMDGPUmad_u24 i32:$src0, i32:$src1, i32:$src2))], VecALU 322>; 323 324def : UMad24Pat<MULADD_UINT24_eg>; 325 326def BIT_ALIGN_INT_eg : R600_3OP <0xC, "BIT_ALIGN_INT", [], VecALU>; 327def : ROTRPattern <BIT_ALIGN_INT_eg>; 328def MULADD_eg : MULADD_Common<0x14>; 329def MULADD_IEEE_eg : MULADD_IEEE_Common<0x18>; 330def FMA_eg : FMA_Common<0x7>; 331def ASHR_eg : ASHR_Common<0x15>; 332def LSHR_eg : LSHR_Common<0x16>; 333def LSHL_eg : LSHL_Common<0x17>; 334def CNDE_eg : CNDE_Common<0x19>; 335def CNDGT_eg : CNDGT_Common<0x1A>; 336def CNDGE_eg : CNDGE_Common<0x1B>; 337def MUL_LIT_eg : MUL_LIT_Common<0x1F>; 338def LOG_CLAMPED_eg : LOG_CLAMPED_Common<0x82>; 339def MUL_UINT24_eg : R600_2OP <0xB5, "MUL_UINT24", 340 [(set i32:$dst, (AMDGPUmul_u24 i32:$src0, i32:$src1))], VecALU 341>; 342def DOT4_eg : DOT4_Common<0xBE>; 343defm CUBE_eg : CUBE_Common<0xC0>; 344 345def BCNT_INT : R600_1OP_Helper <0xAA, "BCNT_INT", ctpop, VecALU>; 346 347def ADDC_UINT : R600_2OP_Helper <0x52, "ADDC_UINT", AMDGPUcarry>; 348def SUBB_UINT : R600_2OP_Helper <0x53, "SUBB_UINT", AMDGPUborrow>; 349 350def FFBH_UINT : R600_1OP_Helper <0xAB, "FFBH_UINT", AMDGPUffbh_u32, VecALU>; 351def FFBL_INT : R600_1OP_Helper <0xAC, "FFBL_INT", cttz_zero_undef, VecALU>; 352 353let hasSideEffects = 1 in { 354 def MOVA_INT_eg : R600_1OP <0xCC, "MOVA_INT", [], VecALU>; 355} 356 357def FLT_TO_INT_eg : FLT_TO_INT_Common<0x50> { 358 let Pattern = []; 359 let Itinerary = AnyALU; 360} 361 362def INT_TO_FLT_eg : INT_TO_FLT_Common<0x9B>; 363 364def FLT_TO_UINT_eg : FLT_TO_UINT_Common<0x9A> { 365 let Pattern = []; 366} 367 368def UINT_TO_FLT_eg : UINT_TO_FLT_Common<0x9C>; 369 370def GROUP_BARRIER : InstR600 < 371 (outs), (ins), " GROUP_BARRIER", [(int_AMDGPU_barrier_local), (int_AMDGPU_barrier_global)], AnyALU>, 372 R600ALU_Word0, 373 R600ALU_Word1_OP2 <0x54> { 374 375 let dst = 0; 376 let dst_rel = 0; 377 let src0 = 0; 378 let src0_rel = 0; 379 let src0_neg = 0; 380 let src0_abs = 0; 381 let src1 = 0; 382 let src1_rel = 0; 383 let src1_neg = 0; 384 let src1_abs = 0; 385 let write = 0; 386 let omod = 0; 387 let clamp = 0; 388 let last = 1; 389 let bank_swizzle = 0; 390 let pred_sel = 0; 391 let update_exec_mask = 0; 392 let update_pred = 0; 393 394 let Inst{31-0} = Word0; 395 let Inst{63-32} = Word1; 396 397 let ALUInst = 1; 398} 399 400def : Pat < 401 (int_AMDGPU_barrier_global), 402 (GROUP_BARRIER) 403>; 404 405//===----------------------------------------------------------------------===// 406// LDS Instructions 407//===----------------------------------------------------------------------===// 408class R600_LDS <bits<6> op, dag outs, dag ins, string asm, 409 list<dag> pattern = []> : 410 411 InstR600 <outs, ins, asm, pattern, XALU>, 412 R600_ALU_LDS_Word0, 413 R600LDS_Word1 { 414 415 bits<6> offset = 0; 416 let lds_op = op; 417 418 let Word1{27} = offset{0}; 419 let Word1{12} = offset{1}; 420 let Word1{28} = offset{2}; 421 let Word1{31} = offset{3}; 422 let Word0{12} = offset{4}; 423 let Word0{25} = offset{5}; 424 425 426 let Inst{31-0} = Word0; 427 let Inst{63-32} = Word1; 428 429 let ALUInst = 1; 430 let HasNativeOperands = 1; 431 let UseNamedOperandTable = 1; 432} 433 434class R600_LDS_1A <bits<6> lds_op, string name, list<dag> pattern> : R600_LDS < 435 lds_op, 436 (outs R600_Reg32:$dst), 437 (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel, 438 LAST:$last, R600_Pred:$pred_sel, 439 BANK_SWIZZLE:$bank_swizzle), 440 " "#name#" $last OQAP, $src0$src0_rel $pred_sel", 441 pattern 442 > { 443 444 let src1 = 0; 445 let src1_rel = 0; 446 let src2 = 0; 447 let src2_rel = 0; 448 449 let usesCustomInserter = 1; 450 let LDS_1A = 1; 451 let DisableEncoding = "$dst"; 452} 453 454class R600_LDS_1A1D <bits<6> lds_op, dag outs, string name, list<dag> pattern, 455 string dst =""> : 456 R600_LDS < 457 lds_op, outs, 458 (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel, 459 R600_Reg32:$src1, REL:$src1_rel, SEL:$src1_sel, 460 LAST:$last, R600_Pred:$pred_sel, 461 BANK_SWIZZLE:$bank_swizzle), 462 " "#name#" $last "#dst#"$src0$src0_rel, $src1$src1_rel, $pred_sel", 463 pattern 464 > { 465 466 field string BaseOp; 467 468 let src2 = 0; 469 let src2_rel = 0; 470 let LDS_1A1D = 1; 471} 472 473class R600_LDS_1A1D_NORET <bits<6> lds_op, string name, list<dag> pattern> : 474 R600_LDS_1A1D <lds_op, (outs), name, pattern> { 475 let BaseOp = name; 476} 477 478class R600_LDS_1A1D_RET <bits<6> lds_op, string name, list<dag> pattern> : 479 R600_LDS_1A1D <lds_op, (outs R600_Reg32:$dst), name##"_RET", pattern, "OQAP, "> { 480 481 let BaseOp = name; 482 let usesCustomInserter = 1; 483 let DisableEncoding = "$dst"; 484} 485 486class R600_LDS_1A2D <bits<6> lds_op, dag outs, string name, list<dag> pattern, 487 string dst =""> : 488 R600_LDS < 489 lds_op, outs, 490 (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel, 491 R600_Reg32:$src1, REL:$src1_rel, SEL:$src1_sel, 492 R600_Reg32:$src2, REL:$src2_rel, SEL:$src2_sel, 493 LAST:$last, R600_Pred:$pred_sel, BANK_SWIZZLE:$bank_swizzle), 494 " "#name# "$last "#dst#"$src0$src0_rel, $src1$src1_rel, $src2$src2_rel, $pred_sel", 495 pattern> { 496 497 field string BaseOp; 498 499 let LDS_1A1D = 0; 500 let LDS_1A2D = 1; 501} 502 503class R600_LDS_1A2D_NORET <bits<6> lds_op, string name, list<dag> pattern> : 504 R600_LDS_1A2D <lds_op, (outs), name, pattern> { 505 let BaseOp = name; 506} 507 508class R600_LDS_1A2D_RET <bits<6> lds_op, string name, list<dag> pattern> : 509 R600_LDS_1A2D <lds_op, (outs R600_Reg32:$dst), name, pattern> { 510 511 let BaseOp = name; 512 let usesCustomInserter = 1; 513 let DisableEncoding = "$dst"; 514} 515 516def LDS_ADD : R600_LDS_1A1D_NORET <0x0, "LDS_ADD", [] >; 517def LDS_SUB : R600_LDS_1A1D_NORET <0x1, "LDS_SUB", [] >; 518def LDS_AND : R600_LDS_1A1D_NORET <0x9, "LDS_AND", [] >; 519def LDS_OR : R600_LDS_1A1D_NORET <0xa, "LDS_OR", [] >; 520def LDS_XOR : R600_LDS_1A1D_NORET <0xb, "LDS_XOR", [] >; 521def LDS_WRXCHG: R600_LDS_1A1D_NORET <0xd, "LDS_WRXCHG", [] >; 522def LDS_CMPST: R600_LDS_1A2D_NORET <0x10, "LDS_CMPST", [] >; 523def LDS_MIN_INT : R600_LDS_1A1D_NORET <0x5, "LDS_MIN_INT", [] >; 524def LDS_MAX_INT : R600_LDS_1A1D_NORET <0x6, "LDS_MAX_INT", [] >; 525def LDS_MIN_UINT : R600_LDS_1A1D_NORET <0x7, "LDS_MIN_UINT", [] >; 526def LDS_MAX_UINT : R600_LDS_1A1D_NORET <0x8, "LDS_MAX_UINT", [] >; 527def LDS_WRITE : R600_LDS_1A1D_NORET <0xD, "LDS_WRITE", 528 [(local_store (i32 R600_Reg32:$src1), R600_Reg32:$src0)] 529>; 530def LDS_BYTE_WRITE : R600_LDS_1A1D_NORET<0x12, "LDS_BYTE_WRITE", 531 [(truncstorei8_local i32:$src1, i32:$src0)] 532>; 533def LDS_SHORT_WRITE : R600_LDS_1A1D_NORET<0x13, "LDS_SHORT_WRITE", 534 [(truncstorei16_local i32:$src1, i32:$src0)] 535>; 536def LDS_ADD_RET : R600_LDS_1A1D_RET <0x20, "LDS_ADD", 537 [(set i32:$dst, (atomic_load_add_local i32:$src0, i32:$src1))] 538>; 539def LDS_SUB_RET : R600_LDS_1A1D_RET <0x21, "LDS_SUB", 540 [(set i32:$dst, (atomic_load_sub_local i32:$src0, i32:$src1))] 541>; 542def LDS_AND_RET : R600_LDS_1A1D_RET <0x29, "LDS_AND", 543 [(set i32:$dst, (atomic_load_and_local i32:$src0, i32:$src1))] 544>; 545def LDS_OR_RET : R600_LDS_1A1D_RET <0x2a, "LDS_OR", 546 [(set i32:$dst, (atomic_load_or_local i32:$src0, i32:$src1))] 547>; 548def LDS_XOR_RET : R600_LDS_1A1D_RET <0x2b, "LDS_XOR", 549 [(set i32:$dst, (atomic_load_xor_local i32:$src0, i32:$src1))] 550>; 551def LDS_MIN_INT_RET : R600_LDS_1A1D_RET <0x25, "LDS_MIN_INT", 552 [(set i32:$dst, (atomic_load_min_local i32:$src0, i32:$src1))] 553>; 554def LDS_MAX_INT_RET : R600_LDS_1A1D_RET <0x26, "LDS_MAX_INT", 555 [(set i32:$dst, (atomic_load_max_local i32:$src0, i32:$src1))] 556>; 557def LDS_MIN_UINT_RET : R600_LDS_1A1D_RET <0x27, "LDS_MIN_UINT", 558 [(set i32:$dst, (atomic_load_umin_local i32:$src0, i32:$src1))] 559>; 560def LDS_MAX_UINT_RET : R600_LDS_1A1D_RET <0x28, "LDS_MAX_UINT", 561 [(set i32:$dst, (atomic_load_umax_local i32:$src0, i32:$src1))] 562>; 563def LDS_WRXCHG_RET : R600_LDS_1A1D_RET <0x2d, "LDS_WRXCHG", 564 [(set i32:$dst, (atomic_swap_local i32:$src0, i32:$src1))] 565>; 566def LDS_CMPST_RET : R600_LDS_1A2D_RET <0x30, "LDS_CMPST", 567 [(set i32:$dst, (atomic_cmp_swap_32_local i32:$src0, i32:$src1, i32:$src2))] 568>; 569def LDS_READ_RET : R600_LDS_1A <0x32, "LDS_READ_RET", 570 [(set (i32 R600_Reg32:$dst), (local_load R600_Reg32:$src0))] 571>; 572def LDS_BYTE_READ_RET : R600_LDS_1A <0x36, "LDS_BYTE_READ_RET", 573 [(set i32:$dst, (sextloadi8_local i32:$src0))] 574>; 575def LDS_UBYTE_READ_RET : R600_LDS_1A <0x37, "LDS_UBYTE_READ_RET", 576 [(set i32:$dst, (az_extloadi8_local i32:$src0))] 577>; 578def LDS_SHORT_READ_RET : R600_LDS_1A <0x38, "LDS_SHORT_READ_RET", 579 [(set i32:$dst, (sextloadi16_local i32:$src0))] 580>; 581def LDS_USHORT_READ_RET : R600_LDS_1A <0x39, "LDS_USHORT_READ_RET", 582 [(set i32:$dst, (az_extloadi16_local i32:$src0))] 583>; 584 585// TRUNC is used for the FLT_TO_INT instructions to work around a 586// perceived problem where the rounding modes are applied differently 587// depending on the instruction and the slot they are in. 588// See: 589// https://bugs.freedesktop.org/show_bug.cgi?id=50232 590// Mesa commit: a1a0974401c467cb86ef818f22df67c21774a38c 591// 592// XXX: Lowering SELECT_CC will sometimes generate fp_to_[su]int nodes, 593// which do not need to be truncated since the fp values are 0.0f or 1.0f. 594// We should look into handling these cases separately. 595def : Pat<(fp_to_sint f32:$src0), (FLT_TO_INT_eg (TRUNC $src0))>; 596 597def : Pat<(fp_to_uint f32:$src0), (FLT_TO_UINT_eg (TRUNC $src0))>; 598 599// SHA-256 Patterns 600def : SHA256MaPattern <BFI_INT_eg, XOR_INT>; 601 602def EG_ExportSwz : ExportSwzInst { 603 let Word1{19-16} = 0; // BURST_COUNT 604 let Word1{20} = 0; // VALID_PIXEL_MODE 605 let Word1{21} = eop; 606 let Word1{29-22} = inst; 607 let Word1{30} = 0; // MARK 608 let Word1{31} = 1; // BARRIER 609} 610defm : ExportPattern<EG_ExportSwz, 83>; 611 612def EG_ExportBuf : ExportBufInst { 613 let Word1{19-16} = 0; // BURST_COUNT 614 let Word1{20} = 0; // VALID_PIXEL_MODE 615 let Word1{21} = eop; 616 let Word1{29-22} = inst; 617 let Word1{30} = 0; // MARK 618 let Word1{31} = 1; // BARRIER 619} 620defm : SteamOutputExportPattern<EG_ExportBuf, 0x40, 0x41, 0x42, 0x43>; 621 622def CF_TC_EG : CF_CLAUSE_EG<1, (ins i32imm:$ADDR, i32imm:$COUNT), 623 "TEX $COUNT @$ADDR"> { 624 let POP_COUNT = 0; 625} 626def CF_VC_EG : CF_CLAUSE_EG<2, (ins i32imm:$ADDR, i32imm:$COUNT), 627 "VTX $COUNT @$ADDR"> { 628 let POP_COUNT = 0; 629} 630def WHILE_LOOP_EG : CF_CLAUSE_EG<6, (ins i32imm:$ADDR), 631 "LOOP_START_DX10 @$ADDR"> { 632 let POP_COUNT = 0; 633 let COUNT = 0; 634} 635def END_LOOP_EG : CF_CLAUSE_EG<5, (ins i32imm:$ADDR), "END_LOOP @$ADDR"> { 636 let POP_COUNT = 0; 637 let COUNT = 0; 638} 639def LOOP_BREAK_EG : CF_CLAUSE_EG<9, (ins i32imm:$ADDR), 640 "LOOP_BREAK @$ADDR"> { 641 let POP_COUNT = 0; 642 let COUNT = 0; 643} 644def CF_CONTINUE_EG : CF_CLAUSE_EG<8, (ins i32imm:$ADDR), 645 "CONTINUE @$ADDR"> { 646 let POP_COUNT = 0; 647 let COUNT = 0; 648} 649def CF_JUMP_EG : CF_CLAUSE_EG<10, (ins i32imm:$ADDR, i32imm:$POP_COUNT), 650 "JUMP @$ADDR POP:$POP_COUNT"> { 651 let COUNT = 0; 652} 653def CF_PUSH_EG : CF_CLAUSE_EG<11, (ins i32imm:$ADDR, i32imm:$POP_COUNT), 654 "PUSH @$ADDR POP:$POP_COUNT"> { 655 let COUNT = 0; 656} 657def CF_ELSE_EG : CF_CLAUSE_EG<13, (ins i32imm:$ADDR, i32imm:$POP_COUNT), 658 "ELSE @$ADDR POP:$POP_COUNT"> { 659 let COUNT = 0; 660} 661def CF_CALL_FS_EG : CF_CLAUSE_EG<19, (ins), "CALL_FS"> { 662 let ADDR = 0; 663 let COUNT = 0; 664 let POP_COUNT = 0; 665} 666def POP_EG : CF_CLAUSE_EG<14, (ins i32imm:$ADDR, i32imm:$POP_COUNT), 667 "POP @$ADDR POP:$POP_COUNT"> { 668 let COUNT = 0; 669} 670def CF_END_EG : CF_CLAUSE_EG<0, (ins), "CF_END"> { 671 let COUNT = 0; 672 let POP_COUNT = 0; 673 let ADDR = 0; 674 let END_OF_PROGRAM = 1; 675} 676 677} // End Predicates = [isEGorCayman] 678