1//===-- EvergreenInstructions.td - EG Instruction defs ----*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// TableGen definitions for instructions which are: 11// - Available to Evergreen and newer VLIW4/VLIW5 GPUs 12// - Available only on Evergreen family GPUs. 13// 14//===----------------------------------------------------------------------===// 15 16def isEG : Predicate< 17 "Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && " 18 "Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && " 19 "!Subtarget->hasCaymanISA()" 20>; 21 22def isEGorCayman : Predicate< 23 "Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||" 24 "Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS" 25>; 26 27//===----------------------------------------------------------------------===// 28// Evergreen / Cayman store instructions 29//===----------------------------------------------------------------------===// 30 31let Predicates = [isEGorCayman] in { 32 33class CF_MEM_RAT_CACHELESS <bits<6> rat_inst, bits<4> rat_id, bits<4> mask, dag ins, 34 string name, list<dag> pattern> 35 : EG_CF_RAT <0x57, rat_inst, rat_id, mask, (outs), ins, 36 "MEM_RAT_CACHELESS "#name, pattern>; 37 38class CF_MEM_RAT <bits<6> rat_inst, bits<4> rat_id, dag ins, string name, 39 list<dag> pattern> 40 : EG_CF_RAT <0x56, rat_inst, rat_id, 0xf /* mask */, (outs), ins, 41 "MEM_RAT "#name, pattern>; 42 43class CF_MEM_RAT_STORE_TYPED<bits<1> has_eop> 44 : CF_MEM_RAT <0x1, ?, (ins R600_Reg128:$rw_gpr, R600_Reg128:$index_gpr, 45 i32imm:$rat_id, InstFlag:$eop), 46 "STORE_TYPED RAT($rat_id) $rw_gpr, $index_gpr" 47 #!if(has_eop, ", $eop", ""), 48 [(int_r600_rat_store_typed R600_Reg128:$rw_gpr, 49 R600_Reg128:$index_gpr, 50 (i32 imm:$rat_id))]>; 51 52def RAT_MSKOR : CF_MEM_RAT <0x11, 0, 53 (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr), 54 "MSKOR $rw_gpr.XW, $index_gpr", 55 [(mskor_global v4i32:$rw_gpr, i32:$index_gpr)] 56> { 57 let eop = 0; 58} 59 60} // End let Predicates = [isEGorCayman] 61 62//===----------------------------------------------------------------------===// 63// Evergreen Only instructions 64//===----------------------------------------------------------------------===// 65 66let Predicates = [isEG] in { 67 68def RECIP_IEEE_eg : RECIP_IEEE_Common<0x86>; 69defm DIV_eg : DIV_Common<RECIP_IEEE_eg>; 70 71def MULLO_INT_eg : MULLO_INT_Common<0x8F>; 72def MULHI_INT_eg : MULHI_INT_Common<0x90>; 73def MULLO_UINT_eg : MULLO_UINT_Common<0x91>; 74def MULHI_UINT_eg : MULHI_UINT_Common<0x92>; 75def MULHI_UINT24_eg : MULHI_UINT24_Common<0xb2>; 76 77def RECIP_UINT_eg : RECIP_UINT_Common<0x94>; 78def RECIPSQRT_CLAMPED_eg : RECIPSQRT_CLAMPED_Common<0x87>; 79def EXP_IEEE_eg : EXP_IEEE_Common<0x81>; 80def LOG_IEEE_eg : LOG_IEEE_Common<0x83>; 81def RECIP_CLAMPED_eg : RECIP_CLAMPED_Common<0x84>; 82def RECIPSQRT_IEEE_eg : RECIPSQRT_IEEE_Common<0x89>; 83def : RsqPat<RECIPSQRT_IEEE_eg, f32>; 84def SIN_eg : SIN_Common<0x8D>; 85def COS_eg : COS_Common<0x8E>; 86 87def : POW_Common <LOG_IEEE_eg, EXP_IEEE_eg, MUL>; 88def : Pat<(fsqrt f32:$src), (MUL $src, (RECIPSQRT_CLAMPED_eg $src))>; 89 90//===----------------------------------------------------------------------===// 91// Memory read/write instructions 92//===----------------------------------------------------------------------===// 93 94let usesCustomInserter = 1 in { 95 96// 32-bit store 97def RAT_WRITE_CACHELESS_32_eg : CF_MEM_RAT_CACHELESS <0x2, 0, 0x1, 98 (ins R600_TReg32_X:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop), 99 "STORE_RAW $rw_gpr, $index_gpr, $eop", 100 [(global_store i32:$rw_gpr, i32:$index_gpr)] 101>; 102 103// 64-bit store 104def RAT_WRITE_CACHELESS_64_eg : CF_MEM_RAT_CACHELESS <0x2, 0, 0x3, 105 (ins R600_Reg64:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop), 106 "STORE_RAW $rw_gpr.XY, $index_gpr, $eop", 107 [(global_store v2i32:$rw_gpr, i32:$index_gpr)] 108>; 109 110//128-bit store 111def RAT_WRITE_CACHELESS_128_eg : CF_MEM_RAT_CACHELESS <0x2, 0, 0xf, 112 (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop), 113 "STORE_RAW $rw_gpr.XYZW, $index_gpr, $eop", 114 [(global_store v4i32:$rw_gpr, i32:$index_gpr)] 115>; 116 117def RAT_STORE_TYPED_eg: CF_MEM_RAT_STORE_TYPED<1>; 118 119} // End usesCustomInserter = 1 120 121class VTX_READ_eg <string name, dag outs> 122 : VTX_WORD0_eg, VTX_READ<name, outs, []> { 123 124 // Static fields 125 let VC_INST = 0; 126 let FETCH_TYPE = 2; 127 let FETCH_WHOLE_QUAD = 0; 128 let SRC_REL = 0; 129 // XXX: We can infer this field based on the SRC_GPR. This would allow us 130 // to store vertex addresses in any channel, not just X. 131 let SRC_SEL_X = 0; 132 133 let Inst{31-0} = Word0; 134} 135 136def VTX_READ_8_eg 137 : VTX_READ_eg <"VTX_READ_8 $dst_gpr, $src_gpr", 138 (outs R600_TReg32_X:$dst_gpr)> { 139 140 let MEGA_FETCH_COUNT = 1; 141 let DST_SEL_X = 0; 142 let DST_SEL_Y = 7; // Masked 143 let DST_SEL_Z = 7; // Masked 144 let DST_SEL_W = 7; // Masked 145 let DATA_FORMAT = 1; // FMT_8 146} 147 148def VTX_READ_16_eg 149 : VTX_READ_eg <"VTX_READ_16 $dst_gpr, $src_gpr", 150 (outs R600_TReg32_X:$dst_gpr)> { 151 let MEGA_FETCH_COUNT = 2; 152 let DST_SEL_X = 0; 153 let DST_SEL_Y = 7; // Masked 154 let DST_SEL_Z = 7; // Masked 155 let DST_SEL_W = 7; // Masked 156 let DATA_FORMAT = 5; // FMT_16 157 158} 159 160def VTX_READ_32_eg 161 : VTX_READ_eg <"VTX_READ_32 $dst_gpr, $src_gpr", 162 (outs R600_TReg32_X:$dst_gpr)> { 163 164 let MEGA_FETCH_COUNT = 4; 165 let DST_SEL_X = 0; 166 let DST_SEL_Y = 7; // Masked 167 let DST_SEL_Z = 7; // Masked 168 let DST_SEL_W = 7; // Masked 169 let DATA_FORMAT = 0xD; // COLOR_32 170 171 // This is not really necessary, but there were some GPU hangs that appeared 172 // to be caused by ALU instructions in the next instruction group that wrote 173 // to the $src_gpr registers of the VTX_READ. 174 // e.g. 175 // %T3_X<def> = VTX_READ_PARAM_32_eg %T2_X<kill>, 24 176 // %T2_X<def> = MOV %ZERO 177 //Adding this constraint prevents this from happening. 178 let Constraints = "$src_gpr.ptr = $dst_gpr"; 179} 180 181def VTX_READ_64_eg 182 : VTX_READ_eg <"VTX_READ_64 $dst_gpr.XY, $src_gpr", 183 (outs R600_Reg64:$dst_gpr)> { 184 185 let MEGA_FETCH_COUNT = 8; 186 let DST_SEL_X = 0; 187 let DST_SEL_Y = 1; 188 let DST_SEL_Z = 7; 189 let DST_SEL_W = 7; 190 let DATA_FORMAT = 0x1D; // COLOR_32_32 191} 192 193def VTX_READ_128_eg 194 : VTX_READ_eg <"VTX_READ_128 $dst_gpr.XYZW, $src_gpr", 195 (outs R600_Reg128:$dst_gpr)> { 196 197 let MEGA_FETCH_COUNT = 16; 198 let DST_SEL_X = 0; 199 let DST_SEL_Y = 1; 200 let DST_SEL_Z = 2; 201 let DST_SEL_W = 3; 202 let DATA_FORMAT = 0x22; // COLOR_32_32_32_32 203 204 // XXX: Need to force VTX_READ_128 instructions to write to the same register 205 // that holds its buffer address to avoid potential hangs. We can't use 206 // the same constraint as VTX_READ_32_eg, because the $src_gpr.ptr and $dst 207 // registers are different sizes. 208} 209 210//===----------------------------------------------------------------------===// 211// VTX Read from parameter memory space 212//===----------------------------------------------------------------------===// 213def : Pat<(i32:$dst_gpr (vtx_id3_az_extloadi8 ADDRVTX_READ:$src_gpr)), 214 (VTX_READ_8_eg MEMxi:$src_gpr, 3)>; 215def : Pat<(i32:$dst_gpr (vtx_id3_az_extloadi16 ADDRVTX_READ:$src_gpr)), 216 (VTX_READ_16_eg MEMxi:$src_gpr, 3)>; 217def : Pat<(i32:$dst_gpr (vtx_id3_load ADDRVTX_READ:$src_gpr)), 218 (VTX_READ_32_eg MEMxi:$src_gpr, 3)>; 219def : Pat<(v2i32:$dst_gpr (vtx_id3_load ADDRVTX_READ:$src_gpr)), 220 (VTX_READ_64_eg MEMxi:$src_gpr, 3)>; 221def : Pat<(v4i32:$dst_gpr (vtx_id3_load ADDRVTX_READ:$src_gpr)), 222 (VTX_READ_128_eg MEMxi:$src_gpr, 3)>; 223 224//===----------------------------------------------------------------------===// 225// VTX Read from constant memory space 226//===----------------------------------------------------------------------===// 227def : Pat<(i32:$dst_gpr (vtx_id2_az_extloadi8 ADDRVTX_READ:$src_gpr)), 228 (VTX_READ_8_eg MEMxi:$src_gpr, 2)>; 229def : Pat<(i32:$dst_gpr (vtx_id2_az_extloadi16 ADDRVTX_READ:$src_gpr)), 230 (VTX_READ_16_eg MEMxi:$src_gpr, 2)>; 231def : Pat<(i32:$dst_gpr (vtx_id2_load ADDRVTX_READ:$src_gpr)), 232 (VTX_READ_32_eg MEMxi:$src_gpr, 2)>; 233def : Pat<(v2i32:$dst_gpr (vtx_id2_load ADDRVTX_READ:$src_gpr)), 234 (VTX_READ_64_eg MEMxi:$src_gpr, 2)>; 235def : Pat<(v4i32:$dst_gpr (vtx_id2_load ADDRVTX_READ:$src_gpr)), 236 (VTX_READ_128_eg MEMxi:$src_gpr, 2)>; 237 238//===----------------------------------------------------------------------===// 239// VTX Read from global memory space 240//===----------------------------------------------------------------------===// 241def : Pat<(i32:$dst_gpr (vtx_id1_az_extloadi8 ADDRVTX_READ:$src_gpr)), 242 (VTX_READ_8_eg MEMxi:$src_gpr, 1)>; 243def : Pat<(i32:$dst_gpr (vtx_id1_az_extloadi16 ADDRVTX_READ:$src_gpr)), 244 (VTX_READ_16_eg MEMxi:$src_gpr, 1)>; 245def : Pat<(i32:$dst_gpr (vtx_id1_load ADDRVTX_READ:$src_gpr)), 246 (VTX_READ_32_eg MEMxi:$src_gpr, 1)>; 247def : Pat<(v2i32:$dst_gpr (vtx_id1_load ADDRVTX_READ:$src_gpr)), 248 (VTX_READ_64_eg MEMxi:$src_gpr, 1)>; 249def : Pat<(v4i32:$dst_gpr (vtx_id1_load ADDRVTX_READ:$src_gpr)), 250 (VTX_READ_128_eg MEMxi:$src_gpr, 1)>; 251 252} // End Predicates = [isEG] 253 254//===----------------------------------------------------------------------===// 255// Evergreen / Cayman Instructions 256//===----------------------------------------------------------------------===// 257 258let Predicates = [isEGorCayman] in { 259 260// Should be predicated on FeatureFP64 261// def FMA_64 : R600_3OP < 262// 0xA, "FMA_64", 263// [(set f64:$dst, (fma f64:$src0, f64:$src1, f64:$src2))] 264// >; 265 266// BFE_UINT - bit_extract, an optimization for mask and shift 267// Src0 = Input 268// Src1 = Offset 269// Src2 = Width 270// 271// bit_extract = (Input << (32 - Offset - Width)) >> (32 - Width) 272// 273// Example Usage: 274// (Offset, Width) 275// 276// (0, 8) = (Input << 24) >> 24 = (Input & 0xff) >> 0 277// (8, 8) = (Input << 16) >> 24 = (Input & 0xffff) >> 8 278// (16, 8) = (Input << 8) >> 24 = (Input & 0xffffff) >> 16 279// (24, 8) = (Input << 0) >> 24 = (Input & 0xffffffff) >> 24 280def BFE_UINT_eg : R600_3OP <0x4, "BFE_UINT", 281 [(set i32:$dst, (AMDGPUbfe_u32 i32:$src0, i32:$src1, i32:$src2))], 282 VecALU 283>; 284 285def BFE_INT_eg : R600_3OP <0x5, "BFE_INT", 286 [(set i32:$dst, (AMDGPUbfe_i32 i32:$src0, i32:$src1, i32:$src2))], 287 VecALU 288>; 289 290def : BFEPattern <BFE_UINT_eg, MOV_IMM_I32>; 291 292def BFI_INT_eg : R600_3OP <0x06, "BFI_INT", 293 [(set i32:$dst, (AMDGPUbfi i32:$src0, i32:$src1, i32:$src2))], 294 VecALU 295>; 296 297def : Pat<(i32 (sext_inreg i32:$src, i1)), 298 (BFE_INT_eg i32:$src, (i32 ZERO), (i32 ONE_INT))>; 299def : Pat<(i32 (sext_inreg i32:$src, i8)), 300 (BFE_INT_eg i32:$src, (i32 ZERO), (MOV_IMM_I32 8))>; 301def : Pat<(i32 (sext_inreg i32:$src, i16)), 302 (BFE_INT_eg i32:$src, (i32 ZERO), (MOV_IMM_I32 16))>; 303 304defm : BFIPatterns <BFI_INT_eg, MOV_IMM_I32, R600_Reg64>; 305 306def BFM_INT_eg : R600_2OP <0xA0, "BFM_INT", 307 [(set i32:$dst, (AMDGPUbfm i32:$src0, i32:$src1))], 308 VecALU 309>; 310 311def MULADD_UINT24_eg : R600_3OP <0x10, "MULADD_UINT24", 312 [(set i32:$dst, (AMDGPUmad_u24 i32:$src0, i32:$src1, i32:$src2))], VecALU 313>; 314 315def : UMad24Pat<MULADD_UINT24_eg>; 316 317def BIT_ALIGN_INT_eg : R600_3OP <0xC, "BIT_ALIGN_INT", [], VecALU>; 318def : ROTRPattern <BIT_ALIGN_INT_eg>; 319def MULADD_eg : MULADD_Common<0x14>; 320def MULADD_IEEE_eg : MULADD_IEEE_Common<0x18>; 321def FMA_eg : FMA_Common<0x7>; 322def ASHR_eg : ASHR_Common<0x15>; 323def LSHR_eg : LSHR_Common<0x16>; 324def LSHL_eg : LSHL_Common<0x17>; 325def CNDE_eg : CNDE_Common<0x19>; 326def CNDGT_eg : CNDGT_Common<0x1A>; 327def CNDGE_eg : CNDGE_Common<0x1B>; 328def MUL_LIT_eg : MUL_LIT_Common<0x1F>; 329def LOG_CLAMPED_eg : LOG_CLAMPED_Common<0x82>; 330def MUL_UINT24_eg : R600_2OP <0xB5, "MUL_UINT24", 331 [(set i32:$dst, (AMDGPUmul_u24 i32:$src0, i32:$src1))], VecALU 332>; 333def DOT4_eg : DOT4_Common<0xBE>; 334defm CUBE_eg : CUBE_Common<0xC0>; 335 336 337def ADDC_UINT : R600_2OP_Helper <0x52, "ADDC_UINT", AMDGPUcarry>; 338def SUBB_UINT : R600_2OP_Helper <0x53, "SUBB_UINT", AMDGPUborrow>; 339 340def FLT32_TO_FLT16 : R600_1OP_Helper <0xA2, "FLT32_TO_FLT16", fp_to_f16, VecALU>; 341def FLT16_TO_FLT32 : R600_1OP_Helper <0xA3, "FLT16_TO_FLT32", f16_to_fp, VecALU>; 342def BCNT_INT : R600_1OP_Helper <0xAA, "BCNT_INT", ctpop, VecALU>; 343def FFBH_UINT : R600_1OP_Helper <0xAB, "FFBH_UINT", AMDGPUffbh_u32, VecALU>; 344def FFBL_INT : R600_1OP_Helper <0xAC, "FFBL_INT", cttz_zero_undef, VecALU>; 345 346let hasSideEffects = 1 in { 347 def MOVA_INT_eg : R600_1OP <0xCC, "MOVA_INT", [], VecALU>; 348} 349 350def FLT_TO_INT_eg : FLT_TO_INT_Common<0x50> { 351 let Pattern = []; 352 let Itinerary = AnyALU; 353} 354 355def INT_TO_FLT_eg : INT_TO_FLT_Common<0x9B>; 356 357def FLT_TO_UINT_eg : FLT_TO_UINT_Common<0x9A> { 358 let Pattern = []; 359} 360 361def UINT_TO_FLT_eg : UINT_TO_FLT_Common<0x9C>; 362 363def GROUP_BARRIER : InstR600 < 364 (outs), (ins), " GROUP_BARRIER", [(int_r600_group_barrier)], AnyALU>, 365 R600ALU_Word0, 366 R600ALU_Word1_OP2 <0x54> { 367 368 let dst = 0; 369 let dst_rel = 0; 370 let src0 = 0; 371 let src0_rel = 0; 372 let src0_neg = 0; 373 let src0_abs = 0; 374 let src1 = 0; 375 let src1_rel = 0; 376 let src1_neg = 0; 377 let src1_abs = 0; 378 let write = 0; 379 let omod = 0; 380 let clamp = 0; 381 let last = 1; 382 let bank_swizzle = 0; 383 let pred_sel = 0; 384 let update_exec_mask = 0; 385 let update_pred = 0; 386 387 let Inst{31-0} = Word0; 388 let Inst{63-32} = Word1; 389 390 let ALUInst = 1; 391} 392 393//===----------------------------------------------------------------------===// 394// LDS Instructions 395//===----------------------------------------------------------------------===// 396class R600_LDS <bits<6> op, dag outs, dag ins, string asm, 397 list<dag> pattern = []> : 398 399 InstR600 <outs, ins, asm, pattern, XALU>, 400 R600_ALU_LDS_Word0, 401 R600LDS_Word1 { 402 403 bits<6> offset = 0; 404 let lds_op = op; 405 406 let Word1{27} = offset{0}; 407 let Word1{12} = offset{1}; 408 let Word1{28} = offset{2}; 409 let Word1{31} = offset{3}; 410 let Word0{12} = offset{4}; 411 let Word0{25} = offset{5}; 412 413 414 let Inst{31-0} = Word0; 415 let Inst{63-32} = Word1; 416 417 let ALUInst = 1; 418 let HasNativeOperands = 1; 419 let UseNamedOperandTable = 1; 420} 421 422class R600_LDS_1A <bits<6> lds_op, string name, list<dag> pattern> : R600_LDS < 423 lds_op, 424 (outs R600_Reg32:$dst), 425 (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel, 426 LAST:$last, R600_Pred:$pred_sel, 427 BANK_SWIZZLE:$bank_swizzle), 428 " "#name#" $last OQAP, $src0$src0_rel $pred_sel", 429 pattern 430 > { 431 432 let src1 = 0; 433 let src1_rel = 0; 434 let src2 = 0; 435 let src2_rel = 0; 436 437 let usesCustomInserter = 1; 438 let LDS_1A = 1; 439 let DisableEncoding = "$dst"; 440} 441 442class R600_LDS_1A1D <bits<6> lds_op, dag outs, string name, list<dag> pattern, 443 string dst =""> : 444 R600_LDS < 445 lds_op, outs, 446 (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel, 447 R600_Reg32:$src1, REL:$src1_rel, SEL:$src1_sel, 448 LAST:$last, R600_Pred:$pred_sel, 449 BANK_SWIZZLE:$bank_swizzle), 450 " "#name#" $last "#dst#"$src0$src0_rel, $src1$src1_rel, $pred_sel", 451 pattern 452 > { 453 454 field string BaseOp; 455 456 let src2 = 0; 457 let src2_rel = 0; 458 let LDS_1A1D = 1; 459} 460 461class R600_LDS_1A1D_NORET <bits<6> lds_op, string name, list<dag> pattern> : 462 R600_LDS_1A1D <lds_op, (outs), name, pattern> { 463 let BaseOp = name; 464} 465 466class R600_LDS_1A1D_RET <bits<6> lds_op, string name, list<dag> pattern> : 467 R600_LDS_1A1D <lds_op, (outs R600_Reg32:$dst), name##"_RET", pattern, "OQAP, "> { 468 469 let BaseOp = name; 470 let usesCustomInserter = 1; 471 let DisableEncoding = "$dst"; 472} 473 474class R600_LDS_1A2D <bits<6> lds_op, dag outs, string name, list<dag> pattern, 475 string dst =""> : 476 R600_LDS < 477 lds_op, outs, 478 (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel, 479 R600_Reg32:$src1, REL:$src1_rel, SEL:$src1_sel, 480 R600_Reg32:$src2, REL:$src2_rel, SEL:$src2_sel, 481 LAST:$last, R600_Pred:$pred_sel, BANK_SWIZZLE:$bank_swizzle), 482 " "#name# "$last "#dst#"$src0$src0_rel, $src1$src1_rel, $src2$src2_rel, $pred_sel", 483 pattern> { 484 485 field string BaseOp; 486 487 let LDS_1A1D = 0; 488 let LDS_1A2D = 1; 489} 490 491class R600_LDS_1A2D_NORET <bits<6> lds_op, string name, list<dag> pattern> : 492 R600_LDS_1A2D <lds_op, (outs), name, pattern> { 493 let BaseOp = name; 494} 495 496class R600_LDS_1A2D_RET <bits<6> lds_op, string name, list<dag> pattern> : 497 R600_LDS_1A2D <lds_op, (outs R600_Reg32:$dst), name, pattern> { 498 499 let BaseOp = name; 500 let usesCustomInserter = 1; 501 let DisableEncoding = "$dst"; 502} 503 504def LDS_ADD : R600_LDS_1A1D_NORET <0x0, "LDS_ADD", [] >; 505def LDS_SUB : R600_LDS_1A1D_NORET <0x1, "LDS_SUB", [] >; 506def LDS_AND : R600_LDS_1A1D_NORET <0x9, "LDS_AND", [] >; 507def LDS_OR : R600_LDS_1A1D_NORET <0xa, "LDS_OR", [] >; 508def LDS_XOR : R600_LDS_1A1D_NORET <0xb, "LDS_XOR", [] >; 509def LDS_WRXCHG: R600_LDS_1A1D_NORET <0xd, "LDS_WRXCHG", [] >; 510def LDS_CMPST: R600_LDS_1A2D_NORET <0x10, "LDS_CMPST", [] >; 511def LDS_MIN_INT : R600_LDS_1A1D_NORET <0x5, "LDS_MIN_INT", [] >; 512def LDS_MAX_INT : R600_LDS_1A1D_NORET <0x6, "LDS_MAX_INT", [] >; 513def LDS_MIN_UINT : R600_LDS_1A1D_NORET <0x7, "LDS_MIN_UINT", [] >; 514def LDS_MAX_UINT : R600_LDS_1A1D_NORET <0x8, "LDS_MAX_UINT", [] >; 515def LDS_WRITE : R600_LDS_1A1D_NORET <0xD, "LDS_WRITE", 516 [(local_store (i32 R600_Reg32:$src1), R600_Reg32:$src0)] 517>; 518def LDS_BYTE_WRITE : R600_LDS_1A1D_NORET<0x12, "LDS_BYTE_WRITE", 519 [(truncstorei8_local i32:$src1, i32:$src0)] 520>; 521def LDS_SHORT_WRITE : R600_LDS_1A1D_NORET<0x13, "LDS_SHORT_WRITE", 522 [(truncstorei16_local i32:$src1, i32:$src0)] 523>; 524def LDS_ADD_RET : R600_LDS_1A1D_RET <0x20, "LDS_ADD", 525 [(set i32:$dst, (atomic_load_add_local i32:$src0, i32:$src1))] 526>; 527def LDS_SUB_RET : R600_LDS_1A1D_RET <0x21, "LDS_SUB", 528 [(set i32:$dst, (atomic_load_sub_local i32:$src0, i32:$src1))] 529>; 530def LDS_AND_RET : R600_LDS_1A1D_RET <0x29, "LDS_AND", 531 [(set i32:$dst, (atomic_load_and_local i32:$src0, i32:$src1))] 532>; 533def LDS_OR_RET : R600_LDS_1A1D_RET <0x2a, "LDS_OR", 534 [(set i32:$dst, (atomic_load_or_local i32:$src0, i32:$src1))] 535>; 536def LDS_XOR_RET : R600_LDS_1A1D_RET <0x2b, "LDS_XOR", 537 [(set i32:$dst, (atomic_load_xor_local i32:$src0, i32:$src1))] 538>; 539def LDS_MIN_INT_RET : R600_LDS_1A1D_RET <0x25, "LDS_MIN_INT", 540 [(set i32:$dst, (atomic_load_min_local i32:$src0, i32:$src1))] 541>; 542def LDS_MAX_INT_RET : R600_LDS_1A1D_RET <0x26, "LDS_MAX_INT", 543 [(set i32:$dst, (atomic_load_max_local i32:$src0, i32:$src1))] 544>; 545def LDS_MIN_UINT_RET : R600_LDS_1A1D_RET <0x27, "LDS_MIN_UINT", 546 [(set i32:$dst, (atomic_load_umin_local i32:$src0, i32:$src1))] 547>; 548def LDS_MAX_UINT_RET : R600_LDS_1A1D_RET <0x28, "LDS_MAX_UINT", 549 [(set i32:$dst, (atomic_load_umax_local i32:$src0, i32:$src1))] 550>; 551def LDS_WRXCHG_RET : R600_LDS_1A1D_RET <0x2d, "LDS_WRXCHG", 552 [(set i32:$dst, (atomic_swap_local i32:$src0, i32:$src1))] 553>; 554def LDS_CMPST_RET : R600_LDS_1A2D_RET <0x30, "LDS_CMPST", 555 [(set i32:$dst, (atomic_cmp_swap_32_local i32:$src0, i32:$src1, i32:$src2))] 556>; 557def LDS_READ_RET : R600_LDS_1A <0x32, "LDS_READ_RET", 558 [(set (i32 R600_Reg32:$dst), (local_load R600_Reg32:$src0))] 559>; 560def LDS_BYTE_READ_RET : R600_LDS_1A <0x36, "LDS_BYTE_READ_RET", 561 [(set i32:$dst, (sextloadi8_local i32:$src0))] 562>; 563def LDS_UBYTE_READ_RET : R600_LDS_1A <0x37, "LDS_UBYTE_READ_RET", 564 [(set i32:$dst, (az_extloadi8_local i32:$src0))] 565>; 566def LDS_SHORT_READ_RET : R600_LDS_1A <0x38, "LDS_SHORT_READ_RET", 567 [(set i32:$dst, (sextloadi16_local i32:$src0))] 568>; 569def LDS_USHORT_READ_RET : R600_LDS_1A <0x39, "LDS_USHORT_READ_RET", 570 [(set i32:$dst, (az_extloadi16_local i32:$src0))] 571>; 572 573// TRUNC is used for the FLT_TO_INT instructions to work around a 574// perceived problem where the rounding modes are applied differently 575// depending on the instruction and the slot they are in. 576// See: 577// https://bugs.freedesktop.org/show_bug.cgi?id=50232 578// Mesa commit: a1a0974401c467cb86ef818f22df67c21774a38c 579// 580// XXX: Lowering SELECT_CC will sometimes generate fp_to_[su]int nodes, 581// which do not need to be truncated since the fp values are 0.0f or 1.0f. 582// We should look into handling these cases separately. 583def : Pat<(fp_to_sint f32:$src0), (FLT_TO_INT_eg (TRUNC $src0))>; 584 585def : Pat<(fp_to_uint f32:$src0), (FLT_TO_UINT_eg (TRUNC $src0))>; 586 587// SHA-256 Patterns 588def : SHA256MaPattern <BFI_INT_eg, XOR_INT>; 589 590def EG_ExportSwz : ExportSwzInst { 591 let Word1{19-16} = 0; // BURST_COUNT 592 let Word1{20} = 0; // VALID_PIXEL_MODE 593 let Word1{21} = eop; 594 let Word1{29-22} = inst; 595 let Word1{30} = 0; // MARK 596 let Word1{31} = 1; // BARRIER 597} 598defm : ExportPattern<EG_ExportSwz, 83>; 599 600def EG_ExportBuf : ExportBufInst { 601 let Word1{19-16} = 0; // BURST_COUNT 602 let Word1{20} = 0; // VALID_PIXEL_MODE 603 let Word1{21} = eop; 604 let Word1{29-22} = inst; 605 let Word1{30} = 0; // MARK 606 let Word1{31} = 1; // BARRIER 607} 608defm : SteamOutputExportPattern<EG_ExportBuf, 0x40, 0x41, 0x42, 0x43>; 609 610def CF_TC_EG : CF_CLAUSE_EG<1, (ins i32imm:$ADDR, i32imm:$COUNT), 611 "TEX $COUNT @$ADDR"> { 612 let POP_COUNT = 0; 613} 614def CF_VC_EG : CF_CLAUSE_EG<2, (ins i32imm:$ADDR, i32imm:$COUNT), 615 "VTX $COUNT @$ADDR"> { 616 let POP_COUNT = 0; 617} 618def WHILE_LOOP_EG : CF_CLAUSE_EG<6, (ins i32imm:$ADDR), 619 "LOOP_START_DX10 @$ADDR"> { 620 let POP_COUNT = 0; 621 let COUNT = 0; 622} 623def END_LOOP_EG : CF_CLAUSE_EG<5, (ins i32imm:$ADDR), "END_LOOP @$ADDR"> { 624 let POP_COUNT = 0; 625 let COUNT = 0; 626} 627def LOOP_BREAK_EG : CF_CLAUSE_EG<9, (ins i32imm:$ADDR), 628 "LOOP_BREAK @$ADDR"> { 629 let POP_COUNT = 0; 630 let COUNT = 0; 631} 632def CF_CONTINUE_EG : CF_CLAUSE_EG<8, (ins i32imm:$ADDR), 633 "CONTINUE @$ADDR"> { 634 let POP_COUNT = 0; 635 let COUNT = 0; 636} 637def CF_JUMP_EG : CF_CLAUSE_EG<10, (ins i32imm:$ADDR, i32imm:$POP_COUNT), 638 "JUMP @$ADDR POP:$POP_COUNT"> { 639 let COUNT = 0; 640} 641def CF_PUSH_EG : CF_CLAUSE_EG<11, (ins i32imm:$ADDR, i32imm:$POP_COUNT), 642 "PUSH @$ADDR POP:$POP_COUNT"> { 643 let COUNT = 0; 644} 645def CF_ELSE_EG : CF_CLAUSE_EG<13, (ins i32imm:$ADDR, i32imm:$POP_COUNT), 646 "ELSE @$ADDR POP:$POP_COUNT"> { 647 let COUNT = 0; 648} 649def CF_CALL_FS_EG : CF_CLAUSE_EG<19, (ins), "CALL_FS"> { 650 let ADDR = 0; 651 let COUNT = 0; 652 let POP_COUNT = 0; 653} 654def POP_EG : CF_CLAUSE_EG<14, (ins i32imm:$ADDR, i32imm:$POP_COUNT), 655 "POP @$ADDR POP:$POP_COUNT"> { 656 let COUNT = 0; 657} 658def CF_END_EG : CF_CLAUSE_EG<0, (ins), "CF_END"> { 659 let COUNT = 0; 660 let POP_COUNT = 0; 661 let ADDR = 0; 662 let END_OF_PROGRAM = 1; 663} 664 665} // End Predicates = [isEGorCayman] 666