1 //===-- AMDGPUDisassembler.hpp - Disassembler for AMDGPU ISA ---*- C++ -*--===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 ///
12 /// This file contains declaration for AMDGPU ISA disassembler
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
17 #define LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
18 
19 #include "llvm/ADT/ArrayRef.h"
20 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
21 #include "llvm/MC/MCDisassembler/MCRelocationInfo.h"
22 #include "llvm/MC/MCDisassembler/MCSymbolizer.h"
23 #include <cstdint>
24 #include <algorithm>
25 #include <memory>
26 
27 namespace llvm {
28 
29 class MCContext;
30 class MCInst;
31 class MCOperand;
32 class MCSubtargetInfo;
33 class Twine;
34 
35 //===----------------------------------------------------------------------===//
36 // AMDGPUDisassembler
37 //===----------------------------------------------------------------------===//
38 
39 class AMDGPUDisassembler : public MCDisassembler {
40 private:
41   mutable ArrayRef<uint8_t> Bytes;
42 
43 public:
44   AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
45     MCDisassembler(STI, Ctx) {}
46 
47   ~AMDGPUDisassembler() override = default;
48 
49   DecodeStatus getInstruction(MCInst &MI, uint64_t &Size,
50                               ArrayRef<uint8_t> Bytes, uint64_t Address,
51                               raw_ostream &WS, raw_ostream &CS) const override;
52 
53   const char* getRegClassName(unsigned RegClassID) const;
54 
55   MCOperand createRegOperand(unsigned int RegId) const;
56   MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const;
57   MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const;
58 
59   MCOperand errOperand(unsigned V, const Twine& ErrMsg) const;
60 
61   DecodeStatus tryDecodeInst(const uint8_t* Table,
62                               MCInst &MI,
63                               uint64_t Inst,
64                               uint64_t Address) const;
65 
66   MCOperand decodeOperand_VGPR_32(unsigned Val) const;
67   MCOperand decodeOperand_VS_32(unsigned Val) const;
68   MCOperand decodeOperand_VS_64(unsigned Val) const;
69   MCOperand decodeOperand_VSrc16(unsigned Val) const;
70   MCOperand decodeOperand_VSrcV216(unsigned Val) const;
71 
72   MCOperand decodeOperand_VReg_64(unsigned Val) const;
73   MCOperand decodeOperand_VReg_96(unsigned Val) const;
74   MCOperand decodeOperand_VReg_128(unsigned Val) const;
75 
76   MCOperand decodeOperand_SReg_32(unsigned Val) const;
77   MCOperand decodeOperand_SReg_32_XM0_XEXEC(unsigned Val) const;
78   MCOperand decodeOperand_SReg_64(unsigned Val) const;
79   MCOperand decodeOperand_SReg_64_XEXEC(unsigned Val) const;
80   MCOperand decodeOperand_SReg_128(unsigned Val) const;
81   MCOperand decodeOperand_SReg_256(unsigned Val) const;
82   MCOperand decodeOperand_SReg_512(unsigned Val) const;
83 
84   enum OpWidthTy {
85     OPW32,
86     OPW64,
87     OPW128,
88     OPW16,
89     OPWV216,
90     OPW_LAST_,
91     OPW_FIRST_ = OPW32
92   };
93 
94   unsigned getVgprClassId(const OpWidthTy Width) const;
95   unsigned getSgprClassId(const OpWidthTy Width) const;
96   unsigned getTtmpClassId(const OpWidthTy Width) const;
97 
98   static MCOperand decodeIntImmed(unsigned Imm);
99   static MCOperand decodeFPImmed(OpWidthTy Width, unsigned Imm);
100   MCOperand decodeLiteralConstant() const;
101 
102   MCOperand decodeSrcOp(const OpWidthTy Width, unsigned Val) const;
103   MCOperand decodeSpecialReg32(unsigned Val) const;
104   MCOperand decodeSpecialReg64(unsigned Val) const;
105 };
106 
107 //===----------------------------------------------------------------------===//
108 // AMDGPUSymbolizer
109 //===----------------------------------------------------------------------===//
110 
111 class AMDGPUSymbolizer : public MCSymbolizer {
112 private:
113   void *DisInfo;
114 
115 public:
116   AMDGPUSymbolizer(MCContext &Ctx, std::unique_ptr<MCRelocationInfo> &&RelInfo,
117                    void *disInfo)
118                    : MCSymbolizer(Ctx, std::move(RelInfo)), DisInfo(disInfo) {}
119 
120   bool tryAddingSymbolicOperand(MCInst &Inst, raw_ostream &cStream,
121                                 int64_t Value, uint64_t Address,
122                                 bool IsBranch, uint64_t Offset,
123                                 uint64_t InstSize) override;
124 
125   void tryAddingPcLoadReferenceComment(raw_ostream &cStream,
126                                        int64_t Value,
127                                        uint64_t Address) override;
128 };
129 
130 } // end namespace llvm
131 
132 #endif // LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
133