1 //===-- AMDGPUDisassembler.hpp - Disassembler for AMDGPU ISA ---*- C++ -*--===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 ///
12 /// This file contains declaration for AMDGPU ISA disassembler
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
17 #define LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
18 
19 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
20 
21 namespace llvm {
22 
23   class MCContext;
24   class MCInst;
25   class MCSubtargetInfo;
26 
27   class AMDGPUDisassembler : public MCDisassembler {
28   public:
29     AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
30       MCDisassembler(STI, Ctx) {}
31 
32     ~AMDGPUDisassembler() {}
33 
34     DecodeStatus getInstruction(MCInst &MI, uint64_t &Size,
35                                 ArrayRef<uint8_t> Bytes, uint64_t Address,
36                                 raw_ostream &WS, raw_ostream &CS) const override;
37 
38     /// Decode inline float value in VSrc field
39     DecodeStatus DecodeLitFloat(unsigned Imm, uint32_t& F) const;
40     /// Decode inline integer value in VSrc field
41     DecodeStatus DecodeLitInteger(unsigned Imm, int64_t& I) const;
42     /// Decode VGPR register
43     DecodeStatus DecodeVgprRegister(unsigned Val, unsigned& RegID) const;
44     /// Decode SGPR register
45     DecodeStatus DecodeSgprRegister(unsigned Val, unsigned& RegID) const;
46     /// Decode register in VSrc field
47     DecodeStatus DecodeSrcRegister(unsigned Val, unsigned& RegID) const;
48 
49     DecodeStatus DecodeVS_32RegisterClass(MCInst &Inst, unsigned Imm,
50                                           uint64_t Addr) const;
51 
52     DecodeStatus DecodeVGPR_32RegisterClass(MCInst &Inst, unsigned Imm,
53                                             uint64_t Addr) const;
54   };
55 } // namespace llvm
56 
57 #endif //LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
58