1 //===- AMDGPUDisassembler.hpp - Disassembler for AMDGPU ISA -----*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 /// \file 10 /// 11 /// This file contains declaration for AMDGPU ISA disassembler 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H 16 #define LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H 17 18 #include "llvm/ADT/ArrayRef.h" 19 #include "llvm/MC/MCContext.h" 20 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 21 #include "llvm/MC/MCDisassembler/MCRelocationInfo.h" 22 #include "llvm/MC/MCDisassembler/MCSymbolizer.h" 23 #include "llvm/MC/MCInstrInfo.h" 24 #include "llvm/Support/DataExtractor.h" 25 26 #include <algorithm> 27 #include <cstdint> 28 #include <memory> 29 30 namespace llvm { 31 32 class MCInst; 33 class MCOperand; 34 class MCSubtargetInfo; 35 class Twine; 36 37 //===----------------------------------------------------------------------===// 38 // AMDGPUDisassembler 39 //===----------------------------------------------------------------------===// 40 41 class AMDGPUDisassembler : public MCDisassembler { 42 private: 43 std::unique_ptr<MCInstrInfo const> const MCII; 44 const MCRegisterInfo &MRI; 45 const unsigned TargetMaxInstBytes; 46 mutable ArrayRef<uint8_t> Bytes; 47 mutable uint32_t Literal; 48 mutable bool HasLiteral; 49 50 public: 51 AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, 52 MCInstrInfo const *MCII); 53 ~AMDGPUDisassembler() override = default; 54 55 DecodeStatus getInstruction(MCInst &MI, uint64_t &Size, 56 ArrayRef<uint8_t> Bytes, uint64_t Address, 57 raw_ostream &CS) const override; 58 59 const char* getRegClassName(unsigned RegClassID) const; 60 61 MCOperand createRegOperand(unsigned int RegId) const; 62 MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const; 63 MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const; 64 65 MCOperand errOperand(unsigned V, const Twine& ErrMsg) const; 66 67 DecodeStatus tryDecodeInst(const uint8_t* Table, MCInst &MI, uint64_t Inst, 68 uint64_t Address) const; 69 70 Optional<DecodeStatus> onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, 71 ArrayRef<uint8_t> Bytes, 72 uint64_t Address, 73 raw_ostream &CStream) const override; 74 75 DecodeStatus decodeKernelDescriptor(StringRef KdName, ArrayRef<uint8_t> Bytes, 76 uint64_t KdAddress) const; 77 78 DecodeStatus 79 decodeKernelDescriptorDirective(DataExtractor::Cursor &Cursor, 80 ArrayRef<uint8_t> Bytes, 81 raw_string_ostream &KdStream) const; 82 83 /// Decode as directives that handle COMPUTE_PGM_RSRC1. 84 /// \param FourByteBuffer - Bytes holding contents of COMPUTE_PGM_RSRC1. 85 /// \param KdStream - Stream to write the disassembled directives to. 86 // NOLINTNEXTLINE(readability-identifier-naming) 87 DecodeStatus decodeCOMPUTE_PGM_RSRC1(uint32_t FourByteBuffer, 88 raw_string_ostream &KdStream) const; 89 90 /// Decode as directives that handle COMPUTE_PGM_RSRC2. 91 /// \param FourByteBuffer - Bytes holding contents of COMPUTE_PGM_RSRC2. 92 /// \param KdStream - Stream to write the disassembled directives to. 93 // NOLINTNEXTLINE(readability-identifier-naming) 94 DecodeStatus decodeCOMPUTE_PGM_RSRC2(uint32_t FourByteBuffer, 95 raw_string_ostream &KdStream) const; 96 97 DecodeStatus convertSDWAInst(MCInst &MI) const; 98 DecodeStatus convertDPP8Inst(MCInst &MI) const; 99 DecodeStatus convertMIMGInst(MCInst &MI) const; 100 101 MCOperand decodeOperand_VGPR_32(unsigned Val) const; 102 MCOperand decodeOperand_VRegOrLds_32(unsigned Val) const; 103 104 MCOperand decodeOperand_VS_32(unsigned Val) const; 105 MCOperand decodeOperand_VS_64(unsigned Val) const; 106 MCOperand decodeOperand_VS_128(unsigned Val) const; 107 MCOperand decodeOperand_VSrc16(unsigned Val) const; 108 MCOperand decodeOperand_VSrcV216(unsigned Val) const; 109 110 MCOperand decodeOperand_VReg_64(unsigned Val) const; 111 MCOperand decodeOperand_VReg_96(unsigned Val) const; 112 MCOperand decodeOperand_VReg_128(unsigned Val) const; 113 MCOperand decodeOperand_VReg_256(unsigned Val) const; 114 MCOperand decodeOperand_VReg_512(unsigned Val) const; 115 116 MCOperand decodeOperand_SReg_32(unsigned Val) const; 117 MCOperand decodeOperand_SReg_32_XM0_XEXEC(unsigned Val) const; 118 MCOperand decodeOperand_SReg_32_XEXEC_HI(unsigned Val) const; 119 MCOperand decodeOperand_SRegOrLds_32(unsigned Val) const; 120 MCOperand decodeOperand_SReg_64(unsigned Val) const; 121 MCOperand decodeOperand_SReg_64_XEXEC(unsigned Val) const; 122 MCOperand decodeOperand_SReg_128(unsigned Val) const; 123 MCOperand decodeOperand_SReg_256(unsigned Val) const; 124 MCOperand decodeOperand_SReg_512(unsigned Val) const; 125 126 MCOperand decodeOperand_AGPR_32(unsigned Val) const; 127 MCOperand decodeOperand_AReg_128(unsigned Val) const; 128 MCOperand decodeOperand_AReg_512(unsigned Val) const; 129 MCOperand decodeOperand_AReg_1024(unsigned Val) const; 130 MCOperand decodeOperand_AV_32(unsigned Val) const; 131 MCOperand decodeOperand_AV_64(unsigned Val) const; 132 133 enum OpWidthTy { 134 OPW32, 135 OPW64, 136 OPW128, 137 OPW256, 138 OPW512, 139 OPW1024, 140 OPW16, 141 OPWV216, 142 OPW_LAST_, 143 OPW_FIRST_ = OPW32 144 }; 145 146 unsigned getVgprClassId(const OpWidthTy Width) const; 147 unsigned getAgprClassId(const OpWidthTy Width) const; 148 unsigned getSgprClassId(const OpWidthTy Width) const; 149 unsigned getTtmpClassId(const OpWidthTy Width) const; 150 151 static MCOperand decodeIntImmed(unsigned Imm); 152 static MCOperand decodeFPImmed(OpWidthTy Width, unsigned Imm); 153 MCOperand decodeLiteralConstant() const; 154 155 MCOperand decodeSrcOp(const OpWidthTy Width, unsigned Val) const; 156 MCOperand decodeDstOp(const OpWidthTy Width, unsigned Val) const; 157 MCOperand decodeSpecialReg32(unsigned Val) const; 158 MCOperand decodeSpecialReg64(unsigned Val) const; 159 160 MCOperand decodeSDWASrc(const OpWidthTy Width, unsigned Val) const; 161 MCOperand decodeSDWASrc16(unsigned Val) const; 162 MCOperand decodeSDWASrc32(unsigned Val) const; 163 MCOperand decodeSDWAVopcDst(unsigned Val) const; 164 165 MCOperand decodeBoolReg(unsigned Val) const; 166 167 int getTTmpIdx(unsigned Val) const; 168 169 bool isVI() const; 170 bool isGFX9() const; 171 bool isGFX10() const; 172 }; 173 174 //===----------------------------------------------------------------------===// 175 // AMDGPUSymbolizer 176 //===----------------------------------------------------------------------===// 177 178 class AMDGPUSymbolizer : public MCSymbolizer { 179 private: 180 void *DisInfo; 181 182 public: 183 AMDGPUSymbolizer(MCContext &Ctx, std::unique_ptr<MCRelocationInfo> &&RelInfo, 184 void *disInfo) 185 : MCSymbolizer(Ctx, std::move(RelInfo)), DisInfo(disInfo) {} 186 187 bool tryAddingSymbolicOperand(MCInst &Inst, raw_ostream &cStream, 188 int64_t Value, uint64_t Address, 189 bool IsBranch, uint64_t Offset, 190 uint64_t InstSize) override; 191 192 void tryAddingPcLoadReferenceComment(raw_ostream &cStream, 193 int64_t Value, 194 uint64_t Address) override; 195 }; 196 197 } // end namespace llvm 198 199 #endif // LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H 200