1 //===-- AMDGPUDisassembler.hpp - Disassembler for AMDGPU ISA ---*- C++ -*--===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 ///
12 /// This file contains declaration for AMDGPU ISA disassembler
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
17 #define LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
18 
19 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
20 
21 namespace llvm {
22 
23   class MCContext;
24   class MCInst;
25   class MCOperand;
26   class MCSubtargetInfo;
27   class Twine;
28 
29   class AMDGPUDisassembler : public MCDisassembler {
30   private:
31     mutable ArrayRef<uint8_t> Bytes;
32 
33   public:
34     AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
35       MCDisassembler(STI, Ctx) {}
36 
37     ~AMDGPUDisassembler() {}
38 
39     DecodeStatus getInstruction(MCInst &MI, uint64_t &Size,
40                                 ArrayRef<uint8_t> Bytes, uint64_t Address,
41                                 raw_ostream &WS, raw_ostream &CS) const override;
42 
43     const char* getRegClassName(unsigned RegClassID) const;
44 
45     MCOperand createRegOperand(unsigned int RegId) const;
46     MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const;
47     MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const;
48 
49     MCOperand errOperand(unsigned V, const llvm::Twine& ErrMsg) const;
50 
51     DecodeStatus tryDecodeInst(const uint8_t* Table,
52                                MCInst &MI,
53                                uint64_t Inst,
54                                uint64_t Address) const;
55 
56     MCOperand decodeOperand_VGPR_32(unsigned Val) const;
57     MCOperand decodeOperand_VS_32(unsigned Val) const;
58     MCOperand decodeOperand_VS_64(unsigned Val) const;
59 
60     MCOperand decodeOperand_VReg_64(unsigned Val) const;
61     MCOperand decodeOperand_VReg_96(unsigned Val) const;
62     MCOperand decodeOperand_VReg_128(unsigned Val) const;
63 
64     MCOperand decodeOperand_SGPR_32(unsigned Val) const;
65     MCOperand decodeOperand_SReg_32(unsigned Val) const;
66     MCOperand decodeOperand_SReg_64(unsigned Val) const;
67     MCOperand decodeOperand_SReg_128(unsigned Val) const;
68     MCOperand decodeOperand_SReg_256(unsigned Val) const;
69     MCOperand decodeOperand_SReg_512(unsigned Val) const;
70 
71     enum { OP32 = true, OP64 = false };
72 
73     static MCOperand decodeIntImmed(unsigned Imm);
74     static MCOperand decodeFPImmed(bool Is32, unsigned Imm);
75     MCOperand decodeLiteralConstant() const;
76 
77     MCOperand decodeSrcOp(bool Is32, unsigned Val) const;
78     MCOperand decodeSpecialReg32(unsigned Val) const;
79     MCOperand decodeSpecialReg64(unsigned Val) const;
80   };
81 } // namespace llvm
82 
83 #endif //LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
84