1 //===-- AMDGPUDisassembler.hpp - Disassembler for AMDGPU ISA ---*- C++ -*--===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 ///
12 /// This file contains declaration for AMDGPU ISA disassembler
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
17 #define LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
18 
19 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
20 
21 namespace llvm {
22 
23   class MCContext;
24   class MCInst;
25   class MCSubtargetInfo;
26 
27   class AMDGPUDisassembler : public MCDisassembler {
28   private:
29     /// true if 32-bit literal constant is placed after instruction
30     mutable bool HasLiteral;
31     mutable ArrayRef<uint8_t> Bytes;
32 
33   public:
34     AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
35       MCDisassembler(STI, Ctx), HasLiteral(false) {}
36 
37     ~AMDGPUDisassembler() {}
38 
39     DecodeStatus getInstruction(MCInst &MI, uint64_t &Size,
40                                 ArrayRef<uint8_t> Bytes, uint64_t Address,
41                                 raw_ostream &WS, raw_ostream &CS) const override;
42 
43     /// Decode inline float value in SRC field
44     DecodeStatus DecodeImmedFloat(unsigned Imm, uint32_t &F) const;
45     /// Decode inline double value in SRC field
46     DecodeStatus DecodeImmedDouble(unsigned Imm, uint64_t &D) const;
47     /// Decode inline integer value in SRC field
48     DecodeStatus DecodeImmedInteger(unsigned Imm, int64_t &I) const;
49     /// Decode VGPR register
50     DecodeStatus DecodeVgprRegister(unsigned Val, unsigned &RegID,
51                                     unsigned Size = 32) const;
52     /// Decode SGPR register
53     DecodeStatus DecodeSgprRegister(unsigned Val, unsigned &RegID,
54                                     unsigned Size = 32) const;
55     /// Decode 32-bit register in SRC field
56     DecodeStatus DecodeSrc32Register(unsigned Val, unsigned &RegID) const;
57     /// Decode 64-bit register in SRC field
58     DecodeStatus DecodeSrc64Register(unsigned Val, unsigned &RegID) const;
59 
60     /// Decode literal constant after instruction
61     DecodeStatus DecodeLiteralConstant(MCInst &Inst, uint64_t &Literal) const;
62 
63     DecodeStatus DecodeVGPR_32RegisterClass(MCInst &Inst, unsigned Imm,
64                                             uint64_t Addr) const;
65 
66     DecodeStatus DecodeVSRegisterClass(MCInst &Inst, unsigned Imm,
67                                        uint64_t Addr, bool Is32) const;
68 
69     DecodeStatus DecodeVS_32RegisterClass(MCInst &Inst, unsigned Imm,
70                                           uint64_t Addr) const;
71 
72     DecodeStatus DecodeVS_64RegisterClass(MCInst &Inst, unsigned Imm,
73                                           uint64_t Addr) const;
74 
75     DecodeStatus DecodeVReg_64RegisterClass(MCInst &Inst, unsigned Imm,
76                                             uint64_t Addr) const;
77   };
78 } // namespace llvm
79 
80 #endif // LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
81