1 //===-- AMDGPUDisassembler.hpp - Disassembler for AMDGPU ISA ---*- C++ -*--===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 ///
12 /// This file contains declaration for AMDGPU ISA disassembler
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
17 #define LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
18 
19 #include "llvm/ADT/ArrayRef.h"
20 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
21 #include "llvm/MC/MCDisassembler/MCSymbolizer.h"
22 
23 namespace llvm {
24 
25 class MCContext;
26 class MCInst;
27 class MCOperand;
28 class MCSubtargetInfo;
29 class Twine;
30 
31 //===----------------------------------------------------------------------===//
32 // AMDGPUDisassembler
33 //===----------------------------------------------------------------------===//
34 
35 class AMDGPUDisassembler : public MCDisassembler {
36 private:
37   mutable ArrayRef<uint8_t> Bytes;
38 
39 public:
40   AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
41     MCDisassembler(STI, Ctx) {}
42 
43   ~AMDGPUDisassembler() {}
44 
45   DecodeStatus getInstruction(MCInst &MI, uint64_t &Size,
46                               ArrayRef<uint8_t> Bytes, uint64_t Address,
47                               raw_ostream &WS, raw_ostream &CS) const override;
48 
49   const char* getRegClassName(unsigned RegClassID) const;
50 
51   MCOperand createRegOperand(unsigned int RegId) const;
52   MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const;
53   MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const;
54 
55   MCOperand errOperand(unsigned V, const llvm::Twine& ErrMsg) const;
56 
57   DecodeStatus tryDecodeInst(const uint8_t* Table,
58                               MCInst &MI,
59                               uint64_t Inst,
60                               uint64_t Address) const;
61 
62   MCOperand decodeOperand_VGPR_32(unsigned Val) const;
63   MCOperand decodeOperand_VS_32(unsigned Val) const;
64   MCOperand decodeOperand_VS_64(unsigned Val) const;
65 
66   MCOperand decodeOperand_VReg_64(unsigned Val) const;
67   MCOperand decodeOperand_VReg_96(unsigned Val) const;
68   MCOperand decodeOperand_VReg_128(unsigned Val) const;
69 
70   MCOperand decodeOperand_SReg_32(unsigned Val) const;
71   MCOperand decodeOperand_SReg_32_XM0(unsigned Val) const;
72   MCOperand decodeOperand_SReg_64(unsigned Val) const;
73   MCOperand decodeOperand_SReg_128(unsigned Val) const;
74   MCOperand decodeOperand_SReg_256(unsigned Val) const;
75   MCOperand decodeOperand_SReg_512(unsigned Val) const;
76 
77   enum OpWidthTy {
78     OPW32,
79     OPW64,
80     OPW128,
81     OPW_LAST_,
82     OPW_FIRST_ = OPW32
83   };
84   unsigned getVgprClassId(const OpWidthTy Width) const;
85   unsigned getSgprClassId(const OpWidthTy Width) const;
86   unsigned getTtmpClassId(const OpWidthTy Width) const;
87 
88   static MCOperand decodeIntImmed(unsigned Imm);
89   static MCOperand decodeFPImmed(bool Is32, unsigned Imm);
90   MCOperand decodeLiteralConstant() const;
91 
92   MCOperand decodeSrcOp(const OpWidthTy Width, unsigned Val) const;
93   MCOperand decodeSpecialReg32(unsigned Val) const;
94   MCOperand decodeSpecialReg64(unsigned Val) const;
95 };
96 
97 //===----------------------------------------------------------------------===//
98 // AMDGPUSymbolizer
99 //===----------------------------------------------------------------------===//
100 
101 class AMDGPUSymbolizer : public MCSymbolizer {
102 private:
103   void *DisInfo;
104 
105 public:
106   AMDGPUSymbolizer(MCContext &Ctx, std::unique_ptr<MCRelocationInfo> &&RelInfo,
107                    void *disInfo)
108                    : MCSymbolizer(Ctx, std::move(RelInfo)), DisInfo(disInfo) {}
109 
110   bool tryAddingSymbolicOperand(MCInst &Inst, raw_ostream &cStream,
111                                 int64_t Value, uint64_t Address,
112                                 bool IsBranch, uint64_t Offset,
113                                 uint64_t InstSize) override;
114 
115   void tryAddingPcLoadReferenceComment(raw_ostream &cStream,
116                                        int64_t Value,
117                                        uint64_t Address) override {
118     assert(false && "Implement if needed");
119   }
120 };
121 
122 } // namespace llvm
123 
124 #endif //LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
125