1 //===- AMDGPUDisassembler.hpp - Disassembler for AMDGPU ISA -----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 ///
11 /// This file contains declaration for AMDGPU ISA disassembler
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
16 #define LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
17 
18 #include "llvm/ADT/ArrayRef.h"
19 #include "llvm/MC/MCContext.h"
20 #include "llvm/MC/MCInstrInfo.h"
21 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
22 #include "llvm/MC/MCDisassembler/MCRelocationInfo.h"
23 #include "llvm/MC/MCDisassembler/MCSymbolizer.h"
24 
25 #include <algorithm>
26 #include <cstdint>
27 #include <memory>
28 
29 namespace llvm {
30 
31 class MCInst;
32 class MCOperand;
33 class MCSubtargetInfo;
34 class Twine;
35 
36 //===----------------------------------------------------------------------===//
37 // AMDGPUDisassembler
38 //===----------------------------------------------------------------------===//
39 
40 class AMDGPUDisassembler : public MCDisassembler {
41 private:
42   std::unique_ptr<MCInstrInfo const> const MCII;
43   const MCRegisterInfo &MRI;
44   mutable ArrayRef<uint8_t> Bytes;
45   mutable uint32_t Literal;
46   mutable bool HasLiteral;
47 
48 public:
49   AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
50                      MCInstrInfo const *MCII) :
51     MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()) {}
52 
53   ~AMDGPUDisassembler() override = default;
54 
55   DecodeStatus getInstruction(MCInst &MI, uint64_t &Size,
56                               ArrayRef<uint8_t> Bytes, uint64_t Address,
57                               raw_ostream &WS, raw_ostream &CS) const override;
58 
59   const char* getRegClassName(unsigned RegClassID) const;
60 
61   MCOperand createRegOperand(unsigned int RegId) const;
62   MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const;
63   MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const;
64 
65   MCOperand errOperand(unsigned V, const Twine& ErrMsg) const;
66 
67   DecodeStatus tryDecodeInst(const uint8_t* Table, MCInst &MI, uint64_t Inst,
68                              uint64_t Address) const;
69 
70   DecodeStatus convertSDWAInst(MCInst &MI) const;
71   DecodeStatus convertMIMGInst(MCInst &MI) const;
72 
73   MCOperand decodeOperand_VGPR_32(unsigned Val) const;
74   MCOperand decodeOperand_VS_32(unsigned Val) const;
75   MCOperand decodeOperand_VS_64(unsigned Val) const;
76   MCOperand decodeOperand_VS_128(unsigned Val) const;
77   MCOperand decodeOperand_VSrc16(unsigned Val) const;
78   MCOperand decodeOperand_VSrcV216(unsigned Val) const;
79 
80   MCOperand decodeOperand_VReg_64(unsigned Val) const;
81   MCOperand decodeOperand_VReg_96(unsigned Val) const;
82   MCOperand decodeOperand_VReg_128(unsigned Val) const;
83 
84   MCOperand decodeOperand_SReg_32(unsigned Val) const;
85   MCOperand decodeOperand_SReg_32_XM0_XEXEC(unsigned Val) const;
86   MCOperand decodeOperand_SReg_32_XEXEC_HI(unsigned Val) const;
87   MCOperand decodeOperand_SReg_64(unsigned Val) const;
88   MCOperand decodeOperand_SReg_64_XEXEC(unsigned Val) const;
89   MCOperand decodeOperand_SReg_128(unsigned Val) const;
90   MCOperand decodeOperand_SReg_256(unsigned Val) const;
91   MCOperand decodeOperand_SReg_512(unsigned Val) const;
92 
93   enum OpWidthTy {
94     OPW32,
95     OPW64,
96     OPW128,
97     OPW256,
98     OPW512,
99     OPW16,
100     OPWV216,
101     OPW_LAST_,
102     OPW_FIRST_ = OPW32
103   };
104 
105   unsigned getVgprClassId(const OpWidthTy Width) const;
106   unsigned getSgprClassId(const OpWidthTy Width) const;
107   unsigned getTtmpClassId(const OpWidthTy Width) const;
108 
109   static MCOperand decodeIntImmed(unsigned Imm);
110   static MCOperand decodeFPImmed(OpWidthTy Width, unsigned Imm);
111   MCOperand decodeLiteralConstant() const;
112 
113   MCOperand decodeSrcOp(const OpWidthTy Width, unsigned Val) const;
114   MCOperand decodeDstOp(const OpWidthTy Width, unsigned Val) const;
115   MCOperand decodeSpecialReg32(unsigned Val) const;
116   MCOperand decodeSpecialReg64(unsigned Val) const;
117 
118   MCOperand decodeSDWASrc(const OpWidthTy Width, unsigned Val) const;
119   MCOperand decodeSDWASrc16(unsigned Val) const;
120   MCOperand decodeSDWASrc32(unsigned Val) const;
121   MCOperand decodeSDWAVopcDst(unsigned Val) const;
122 
123   int getTTmpIdx(unsigned Val) const;
124 
125   bool isVI() const;
126   bool isGFX9() const;
127   };
128 
129 //===----------------------------------------------------------------------===//
130 // AMDGPUSymbolizer
131 //===----------------------------------------------------------------------===//
132 
133 class AMDGPUSymbolizer : public MCSymbolizer {
134 private:
135   void *DisInfo;
136 
137 public:
138   AMDGPUSymbolizer(MCContext &Ctx, std::unique_ptr<MCRelocationInfo> &&RelInfo,
139                    void *disInfo)
140                    : MCSymbolizer(Ctx, std::move(RelInfo)), DisInfo(disInfo) {}
141 
142   bool tryAddingSymbolicOperand(MCInst &Inst, raw_ostream &cStream,
143                                 int64_t Value, uint64_t Address,
144                                 bool IsBranch, uint64_t Offset,
145                                 uint64_t InstSize) override;
146 
147   void tryAddingPcLoadReferenceComment(raw_ostream &cStream,
148                                        int64_t Value,
149                                        uint64_t Address) override;
150 };
151 
152 } // end namespace llvm
153 
154 #endif // LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
155