1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 //===----------------------------------------------------------------------===// 10 // 11 /// \file 12 /// 13 /// This file contains definition for AMDGPU ISA disassembler 14 // 15 //===----------------------------------------------------------------------===// 16 17 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)? 18 19 #include "Disassembler/AMDGPUDisassembler.h" 20 #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 21 #include "TargetInfo/AMDGPUTargetInfo.h" 22 #include "Utils/AMDGPUBaseInfo.h" 23 #include "llvm-c/DisassemblerTypes.h" 24 #include "llvm/BinaryFormat/ELF.h" 25 #include "llvm/MC/MCAsmInfo.h" 26 #include "llvm/MC/MCContext.h" 27 #include "llvm/MC/MCDecoderOps.h" 28 #include "llvm/MC/MCExpr.h" 29 #include "llvm/MC/MCInstrDesc.h" 30 #include "llvm/MC/MCRegisterInfo.h" 31 #include "llvm/MC/MCSubtargetInfo.h" 32 #include "llvm/MC/TargetRegistry.h" 33 #include "llvm/Support/AMDHSAKernelDescriptor.h" 34 35 using namespace llvm; 36 37 #define DEBUG_TYPE "amdgpu-disassembler" 38 39 #define SGPR_MAX \ 40 (isGFX10Plus() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \ 41 : AMDGPU::EncValues::SGPR_MAX_SI) 42 43 using DecodeStatus = llvm::MCDisassembler::DecodeStatus; 44 45 AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI, 46 MCContext &Ctx, 47 MCInstrInfo const *MCII) : 48 MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()), 49 TargetMaxInstBytes(Ctx.getAsmInfo()->getMaxInstLength(&STI)) { 50 51 // ToDo: AMDGPUDisassembler supports only VI ISA. 52 if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding] && !isGFX10Plus()) 53 report_fatal_error("Disassembly not yet supported for subtarget"); 54 } 55 56 inline static MCDisassembler::DecodeStatus 57 addOperand(MCInst &Inst, const MCOperand& Opnd) { 58 Inst.addOperand(Opnd); 59 return Opnd.isValid() ? 60 MCDisassembler::Success : 61 MCDisassembler::Fail; 62 } 63 64 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, 65 uint16_t NameIdx) { 66 int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx); 67 if (OpIdx != -1) { 68 auto I = MI.begin(); 69 std::advance(I, OpIdx); 70 MI.insert(I, Op); 71 } 72 return OpIdx; 73 } 74 75 static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm, 76 uint64_t Addr, 77 const MCDisassembler *Decoder) { 78 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 79 80 // Our branches take a simm16, but we need two extra bits to account for the 81 // factor of 4. 82 APInt SignedOffset(18, Imm * 4, true); 83 int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue(); 84 85 if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2)) 86 return MCDisassembler::Success; 87 return addOperand(Inst, MCOperand::createImm(Imm)); 88 } 89 90 static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, uint64_t Addr, 91 const MCDisassembler *Decoder) { 92 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 93 int64_t Offset; 94 if (DAsm->isVI()) { // VI supports 20-bit unsigned offsets. 95 Offset = Imm & 0xFFFFF; 96 } else { // GFX9+ supports 21-bit signed offsets. 97 Offset = SignExtend64<21>(Imm); 98 } 99 return addOperand(Inst, MCOperand::createImm(Offset)); 100 } 101 102 static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, uint64_t Addr, 103 const MCDisassembler *Decoder) { 104 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 105 return addOperand(Inst, DAsm->decodeBoolReg(Val)); 106 } 107 108 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \ 109 static DecodeStatus StaticDecoderName(MCInst &Inst, unsigned Imm, \ 110 uint64_t /*Addr*/, \ 111 const MCDisassembler *Decoder) { \ 112 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 113 return addOperand(Inst, DAsm->DecoderName(Imm)); \ 114 } 115 116 #define DECODE_OPERAND_REG(RegClass) \ 117 DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass) 118 119 DECODE_OPERAND_REG(VGPR_32) 120 DECODE_OPERAND_REG(VRegOrLds_32) 121 DECODE_OPERAND_REG(VS_32) 122 DECODE_OPERAND_REG(VS_64) 123 DECODE_OPERAND_REG(VS_128) 124 125 DECODE_OPERAND_REG(VReg_64) 126 DECODE_OPERAND_REG(VReg_96) 127 DECODE_OPERAND_REG(VReg_128) 128 DECODE_OPERAND_REG(VReg_256) 129 DECODE_OPERAND_REG(VReg_512) 130 DECODE_OPERAND_REG(VReg_1024) 131 132 DECODE_OPERAND_REG(SReg_32) 133 DECODE_OPERAND_REG(SReg_32_XM0_XEXEC) 134 DECODE_OPERAND_REG(SReg_32_XEXEC_HI) 135 DECODE_OPERAND_REG(SRegOrLds_32) 136 DECODE_OPERAND_REG(SReg_64) 137 DECODE_OPERAND_REG(SReg_64_XEXEC) 138 DECODE_OPERAND_REG(SReg_128) 139 DECODE_OPERAND_REG(SReg_256) 140 DECODE_OPERAND_REG(SReg_512) 141 142 DECODE_OPERAND_REG(AGPR_32) 143 DECODE_OPERAND_REG(AReg_64) 144 DECODE_OPERAND_REG(AReg_128) 145 DECODE_OPERAND_REG(AReg_256) 146 DECODE_OPERAND_REG(AReg_512) 147 DECODE_OPERAND_REG(AReg_1024) 148 DECODE_OPERAND_REG(AV_32) 149 DECODE_OPERAND_REG(AV_64) 150 DECODE_OPERAND_REG(AV_128) 151 DECODE_OPERAND_REG(AV_512) 152 153 static DecodeStatus decodeOperand_VSrc16(MCInst &Inst, unsigned Imm, 154 uint64_t Addr, 155 const MCDisassembler *Decoder) { 156 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 157 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); 158 } 159 160 static DecodeStatus decodeOperand_VSrcV216(MCInst &Inst, unsigned Imm, 161 uint64_t Addr, 162 const MCDisassembler *Decoder) { 163 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 164 return addOperand(Inst, DAsm->decodeOperand_VSrcV216(Imm)); 165 } 166 167 static DecodeStatus decodeOperand_VSrcV232(MCInst &Inst, unsigned Imm, 168 uint64_t Addr, 169 const MCDisassembler *Decoder) { 170 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 171 return addOperand(Inst, DAsm->decodeOperand_VSrcV232(Imm)); 172 } 173 174 static DecodeStatus decodeOperand_VS_16(MCInst &Inst, unsigned Imm, 175 uint64_t Addr, 176 const MCDisassembler *Decoder) { 177 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 178 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); 179 } 180 181 static DecodeStatus decodeOperand_VS_32(MCInst &Inst, unsigned Imm, 182 uint64_t Addr, 183 const MCDisassembler *Decoder) { 184 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 185 return addOperand(Inst, DAsm->decodeOperand_VS_32(Imm)); 186 } 187 188 static DecodeStatus decodeOperand_AReg_64(MCInst &Inst, unsigned Imm, 189 uint64_t Addr, 190 const MCDisassembler *Decoder) { 191 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 192 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm | 512)); 193 } 194 195 static DecodeStatus decodeOperand_AReg_128(MCInst &Inst, unsigned Imm, 196 uint64_t Addr, 197 const MCDisassembler *Decoder) { 198 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 199 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm | 512)); 200 } 201 202 static DecodeStatus decodeOperand_AReg_256(MCInst &Inst, unsigned Imm, 203 uint64_t Addr, 204 const MCDisassembler *Decoder) { 205 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 206 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW256, Imm | 512)); 207 } 208 209 static DecodeStatus decodeOperand_AReg_512(MCInst &Inst, unsigned Imm, 210 uint64_t Addr, 211 const MCDisassembler *Decoder) { 212 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 213 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm | 512)); 214 } 215 216 static DecodeStatus decodeOperand_AReg_1024(MCInst &Inst, unsigned Imm, 217 uint64_t Addr, 218 const MCDisassembler *Decoder) { 219 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 220 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm | 512)); 221 } 222 223 static DecodeStatus decodeOperand_VReg_64(MCInst &Inst, unsigned Imm, 224 uint64_t Addr, 225 const MCDisassembler *Decoder) { 226 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 227 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm)); 228 } 229 230 static DecodeStatus decodeOperand_VReg_128(MCInst &Inst, unsigned Imm, 231 uint64_t Addr, 232 const MCDisassembler *Decoder) { 233 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 234 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm)); 235 } 236 237 static DecodeStatus decodeOperand_VReg_256(MCInst &Inst, unsigned Imm, 238 uint64_t Addr, 239 const MCDisassembler *Decoder) { 240 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 241 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW256, Imm)); 242 } 243 244 static DecodeStatus decodeOperand_VReg_512(MCInst &Inst, unsigned Imm, 245 uint64_t Addr, 246 const MCDisassembler *Decoder) { 247 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 248 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm)); 249 } 250 251 static DecodeStatus decodeOperand_VReg_1024(MCInst &Inst, unsigned Imm, 252 uint64_t Addr, 253 const MCDisassembler *Decoder) { 254 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 255 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm)); 256 } 257 258 static DecodeStatus decodeOperand_f32kimm(MCInst &Inst, unsigned Imm, 259 uint64_t Addr, 260 const MCDisassembler *Decoder) { 261 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 262 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm)); 263 } 264 265 static DecodeStatus decodeOperand_f16kimm(MCInst &Inst, unsigned Imm, 266 uint64_t Addr, 267 const MCDisassembler *Decoder) { 268 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 269 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm)); 270 } 271 272 static DecodeStatus 273 decodeOperand_VS_16_Deferred(MCInst &Inst, unsigned Imm, uint64_t Addr, 274 const MCDisassembler *Decoder) { 275 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 276 return addOperand( 277 Inst, DAsm->decodeSrcOp(llvm::AMDGPUDisassembler::OPW16, Imm, true)); 278 } 279 280 static DecodeStatus 281 decodeOperand_VS_32_Deferred(MCInst &Inst, unsigned Imm, uint64_t Addr, 282 const MCDisassembler *Decoder) { 283 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 284 return addOperand( 285 Inst, DAsm->decodeSrcOp(llvm::AMDGPUDisassembler::OPW32, Imm, true)); 286 } 287 288 static bool IsAGPROperand(const MCInst &Inst, int OpIdx, 289 const MCRegisterInfo *MRI) { 290 if (OpIdx < 0) 291 return false; 292 293 const MCOperand &Op = Inst.getOperand(OpIdx); 294 if (!Op.isReg()) 295 return false; 296 297 unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0); 298 auto Reg = Sub ? Sub : Op.getReg(); 299 return Reg >= AMDGPU::AGPR0 && Reg <= AMDGPU::AGPR255; 300 } 301 302 static DecodeStatus decodeOperand_AVLdSt_Any(MCInst &Inst, unsigned Imm, 303 AMDGPUDisassembler::OpWidthTy Opw, 304 const MCDisassembler *Decoder) { 305 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 306 if (!DAsm->isGFX90A()) { 307 Imm &= 511; 308 } else { 309 // If atomic has both vdata and vdst their register classes are tied. 310 // The bit is decoded along with the vdst, first operand. We need to 311 // change register class to AGPR if vdst was AGPR. 312 // If a DS instruction has both data0 and data1 their register classes 313 // are also tied. 314 unsigned Opc = Inst.getOpcode(); 315 uint64_t TSFlags = DAsm->getMCII()->get(Opc).TSFlags; 316 uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0 317 : AMDGPU::OpName::vdata; 318 const MCRegisterInfo *MRI = DAsm->getContext().getRegisterInfo(); 319 int DataIdx = AMDGPU::getNamedOperandIdx(Opc, DataNameIdx); 320 if ((int)Inst.getNumOperands() == DataIdx) { 321 int DstIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst); 322 if (IsAGPROperand(Inst, DstIdx, MRI)) 323 Imm |= 512; 324 } 325 326 if (TSFlags & SIInstrFlags::DS) { 327 int Data2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data1); 328 if ((int)Inst.getNumOperands() == Data2Idx && 329 IsAGPROperand(Inst, DataIdx, MRI)) 330 Imm |= 512; 331 } 332 } 333 return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256)); 334 } 335 336 static DecodeStatus 337 DecodeAVLdSt_32RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 338 const MCDisassembler *Decoder) { 339 return decodeOperand_AVLdSt_Any(Inst, Imm, 340 AMDGPUDisassembler::OPW32, Decoder); 341 } 342 343 static DecodeStatus 344 DecodeAVLdSt_64RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 345 const MCDisassembler *Decoder) { 346 return decodeOperand_AVLdSt_Any(Inst, Imm, 347 AMDGPUDisassembler::OPW64, Decoder); 348 } 349 350 static DecodeStatus 351 DecodeAVLdSt_96RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 352 const MCDisassembler *Decoder) { 353 return decodeOperand_AVLdSt_Any(Inst, Imm, 354 AMDGPUDisassembler::OPW96, Decoder); 355 } 356 357 static DecodeStatus 358 DecodeAVLdSt_128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 359 const MCDisassembler *Decoder) { 360 return decodeOperand_AVLdSt_Any(Inst, Imm, 361 AMDGPUDisassembler::OPW128, Decoder); 362 } 363 364 static DecodeStatus decodeOperand_SReg_32(MCInst &Inst, unsigned Imm, 365 uint64_t Addr, 366 const MCDisassembler *Decoder) { 367 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 368 return addOperand(Inst, DAsm->decodeOperand_SReg_32(Imm)); 369 } 370 371 #define DECODE_SDWA(DecName) \ 372 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName) 373 374 DECODE_SDWA(Src32) 375 DECODE_SDWA(Src16) 376 DECODE_SDWA(VopcDst) 377 378 #include "AMDGPUGenDisassemblerTables.inc" 379 380 //===----------------------------------------------------------------------===// 381 // 382 //===----------------------------------------------------------------------===// 383 384 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) { 385 assert(Bytes.size() >= sizeof(T)); 386 const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data()); 387 Bytes = Bytes.slice(sizeof(T)); 388 return Res; 389 } 390 391 // The disassembler is greedy, so we need to check FI operand value to 392 // not parse a dpp if the correct literal is not set. For dpp16 the 393 // autogenerated decoder checks the dpp literal 394 static bool isValidDPP8(const MCInst &MI) { 395 using namespace llvm::AMDGPU::DPP; 396 int FiIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::fi); 397 assert(FiIdx != -1); 398 if ((unsigned)FiIdx >= MI.getNumOperands()) 399 return false; 400 unsigned Fi = MI.getOperand(FiIdx).getImm(); 401 return Fi == DPP8_FI_0 || Fi == DPP8_FI_1; 402 } 403 404 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 405 ArrayRef<uint8_t> Bytes_, 406 uint64_t Address, 407 raw_ostream &CS) const { 408 CommentStream = &CS; 409 bool IsSDWA = false; 410 411 unsigned MaxInstBytesNum = std::min((size_t)TargetMaxInstBytes, Bytes_.size()); 412 Bytes = Bytes_.slice(0, MaxInstBytesNum); 413 414 DecodeStatus Res = MCDisassembler::Fail; 415 do { 416 // ToDo: better to switch encoding length using some bit predicate 417 // but it is unknown yet, so try all we can 418 419 // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2 420 // encodings 421 if (Bytes.size() >= 8) { 422 const uint64_t QW = eatBytes<uint64_t>(Bytes); 423 424 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) { 425 Res = tryDecodeInst(DecoderTableGFX10_B64, MI, QW, Address); 426 if (Res) { 427 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dpp8) 428 == -1) 429 break; 430 if (convertDPP8Inst(MI) == MCDisassembler::Success) 431 break; 432 MI = MCInst(); // clear 433 } 434 } 435 436 Res = tryDecodeInst(DecoderTableDPP864, MI, QW, Address); 437 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 438 break; 439 440 MI = MCInst(); // clear 441 442 Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address); 443 if (Res) break; 444 445 Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address); 446 if (Res) { IsSDWA = true; break; } 447 448 Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address); 449 if (Res) { IsSDWA = true; break; } 450 451 Res = tryDecodeInst(DecoderTableSDWA1064, MI, QW, Address); 452 if (Res) { IsSDWA = true; break; } 453 454 if (STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem]) { 455 Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address); 456 if (Res) 457 break; 458 } 459 460 // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and 461 // v_mad_mixhi_f16 for FMA variants. Try to decode using this special 462 // table first so we print the correct name. 463 if (STI.getFeatureBits()[AMDGPU::FeatureFmaMixInsts]) { 464 Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address); 465 if (Res) 466 break; 467 } 468 } 469 470 // Reinitialize Bytes as DPP64 could have eaten too much 471 Bytes = Bytes_.slice(0, MaxInstBytesNum); 472 473 // Try decode 32-bit instruction 474 if (Bytes.size() < 4) break; 475 const uint32_t DW = eatBytes<uint32_t>(Bytes); 476 Res = tryDecodeInst(DecoderTableGFX832, MI, DW, Address); 477 if (Res) break; 478 479 Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address); 480 if (Res) break; 481 482 Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address); 483 if (Res) break; 484 485 if (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]) { 486 Res = tryDecodeInst(DecoderTableGFX90A32, MI, DW, Address); 487 if (Res) 488 break; 489 } 490 491 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) { 492 Res = tryDecodeInst(DecoderTableGFX10_B32, MI, DW, Address); 493 if (Res) break; 494 } 495 496 Res = tryDecodeInst(DecoderTableGFX1032, MI, DW, Address); 497 if (Res) break; 498 499 Res = tryDecodeInst(DecoderTableGFX1132, MI, DW, Address); 500 if (Res) break; 501 502 if (Bytes.size() < 4) break; 503 const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW; 504 505 if (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]) { 506 Res = tryDecodeInst(DecoderTableGFX90A64, MI, QW, Address); 507 if (Res) 508 break; 509 } 510 511 Res = tryDecodeInst(DecoderTableGFX864, MI, QW, Address); 512 if (Res) break; 513 514 Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address); 515 if (Res) break; 516 517 Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address); 518 if (Res) break; 519 520 Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address); 521 if (Res) break; 522 523 Res = tryDecodeInst(DecoderTableGFX1164, MI, QW, Address); 524 } while (false); 525 526 if (Res && (MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi || 527 MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx6_gfx7 || 528 MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx10 || 529 MI.getOpcode() == AMDGPU::V_MAC_LEGACY_F32_e64_gfx6_gfx7 || 530 MI.getOpcode() == AMDGPU::V_MAC_LEGACY_F32_e64_gfx10 || 531 MI.getOpcode() == AMDGPU::V_MAC_F16_e64_vi || 532 MI.getOpcode() == AMDGPU::V_FMAC_F64_e64_gfx90a || 533 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_vi || 534 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_gfx10 || 535 MI.getOpcode() == AMDGPU::V_FMAC_LEGACY_F32_e64_gfx10 || 536 MI.getOpcode() == AMDGPU::V_FMAC_F16_e64_gfx10)) { 537 // Insert dummy unused src2_modifiers. 538 insertNamedMCOperand(MI, MCOperand::createImm(0), 539 AMDGPU::OpName::src2_modifiers); 540 } 541 542 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 543 (SIInstrFlags::MUBUF | SIInstrFlags::FLAT | SIInstrFlags::SMRD))) { 544 int CPolPos = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 545 AMDGPU::OpName::cpol); 546 if (CPolPos != -1) { 547 unsigned CPol = 548 (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::IsAtomicRet) ? 549 AMDGPU::CPol::GLC : 0; 550 if (MI.getNumOperands() <= (unsigned)CPolPos) { 551 insertNamedMCOperand(MI, MCOperand::createImm(CPol), 552 AMDGPU::OpName::cpol); 553 } else if (CPol) { 554 MI.getOperand(CPolPos).setImm(MI.getOperand(CPolPos).getImm() | CPol); 555 } 556 } 557 } 558 559 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 560 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF)) && 561 (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts])) { 562 // GFX90A lost TFE, its place is occupied by ACC. 563 int TFEOpIdx = 564 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::tfe); 565 if (TFEOpIdx != -1) { 566 auto TFEIter = MI.begin(); 567 std::advance(TFEIter, TFEOpIdx); 568 MI.insert(TFEIter, MCOperand::createImm(0)); 569 } 570 } 571 572 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 573 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF))) { 574 int SWZOpIdx = 575 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::swz); 576 if (SWZOpIdx != -1) { 577 auto SWZIter = MI.begin(); 578 std::advance(SWZIter, SWZOpIdx); 579 MI.insert(SWZIter, MCOperand::createImm(0)); 580 } 581 } 582 583 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) { 584 int VAddr0Idx = 585 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 586 int RsrcIdx = 587 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc); 588 unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1; 589 if (VAddr0Idx >= 0 && NSAArgs > 0) { 590 unsigned NSAWords = (NSAArgs + 3) / 4; 591 if (Bytes.size() < 4 * NSAWords) { 592 Res = MCDisassembler::Fail; 593 } else { 594 for (unsigned i = 0; i < NSAArgs; ++i) { 595 MI.insert(MI.begin() + VAddr0Idx + 1 + i, 596 decodeOperand_VGPR_32(Bytes[i])); 597 } 598 Bytes = Bytes.slice(4 * NSAWords); 599 } 600 } 601 602 if (Res) 603 Res = convertMIMGInst(MI); 604 } 605 606 if (Res && IsSDWA) 607 Res = convertSDWAInst(MI); 608 609 int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 610 AMDGPU::OpName::vdst_in); 611 if (VDstIn_Idx != -1) { 612 int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx, 613 MCOI::OperandConstraint::TIED_TO); 614 if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx || 615 !MI.getOperand(VDstIn_Idx).isReg() || 616 MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) { 617 if (MI.getNumOperands() > (unsigned)VDstIn_Idx) 618 MI.erase(&MI.getOperand(VDstIn_Idx)); 619 insertNamedMCOperand(MI, 620 MCOperand::createReg(MI.getOperand(Tied).getReg()), 621 AMDGPU::OpName::vdst_in); 622 } 623 } 624 625 int ImmLitIdx = 626 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::imm); 627 if (Res && ImmLitIdx != -1) 628 Res = convertFMAanyK(MI, ImmLitIdx); 629 630 // if the opcode was not recognized we'll assume a Size of 4 bytes 631 // (unless there are fewer bytes left) 632 Size = Res ? (MaxInstBytesNum - Bytes.size()) 633 : std::min((size_t)4, Bytes_.size()); 634 return Res; 635 } 636 637 DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const { 638 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 639 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 640 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst) != -1) 641 // VOPC - insert clamp 642 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp); 643 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 644 int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst); 645 if (SDst != -1) { 646 // VOPC - insert VCC register as sdst 647 insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC), 648 AMDGPU::OpName::sdst); 649 } else { 650 // VOP1/2 - insert omod if present in instruction 651 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod); 652 } 653 } 654 return MCDisassembler::Success; 655 } 656 657 // We must check FI == literal to reject not genuine dpp8 insts, and we must 658 // first add optional MI operands to check FI 659 DecodeStatus AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const { 660 unsigned Opc = MI.getOpcode(); 661 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 662 663 // Insert dummy unused src modifiers. 664 if (MI.getNumOperands() < DescNumOps && 665 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1) 666 insertNamedMCOperand(MI, MCOperand::createImm(0), 667 AMDGPU::OpName::src0_modifiers); 668 669 if (MI.getNumOperands() < DescNumOps && 670 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers) != -1) 671 insertNamedMCOperand(MI, MCOperand::createImm(0), 672 AMDGPU::OpName::src1_modifiers); 673 674 return isValidDPP8(MI) ? MCDisassembler::Success : MCDisassembler::SoftFail; 675 } 676 677 // Note that before gfx10, the MIMG encoding provided no information about 678 // VADDR size. Consequently, decoded instructions always show address as if it 679 // has 1 dword, which could be not really so. 680 DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const { 681 682 int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 683 AMDGPU::OpName::vdst); 684 685 int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 686 AMDGPU::OpName::vdata); 687 int VAddr0Idx = 688 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 689 int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 690 AMDGPU::OpName::dmask); 691 692 int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 693 AMDGPU::OpName::tfe); 694 int D16Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 695 AMDGPU::OpName::d16); 696 697 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode()); 698 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = 699 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); 700 701 assert(VDataIdx != -1); 702 if (BaseOpcode->BVH) { 703 // Add A16 operand for intersect_ray instructions 704 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16) > -1) { 705 addOperand(MI, MCOperand::createImm(1)); 706 } 707 return MCDisassembler::Success; 708 } 709 710 bool IsAtomic = (VDstIdx != -1); 711 bool IsGather4 = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::Gather4; 712 bool IsNSA = false; 713 unsigned AddrSize = Info->VAddrDwords; 714 715 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 716 unsigned DimIdx = 717 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim); 718 int A16Idx = 719 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16); 720 const AMDGPU::MIMGDimInfo *Dim = 721 AMDGPU::getMIMGDimInfoByEncoding(MI.getOperand(DimIdx).getImm()); 722 const bool IsA16 = (A16Idx != -1 && MI.getOperand(A16Idx).getImm()); 723 724 AddrSize = 725 AMDGPU::getAddrSizeMIMGOp(BaseOpcode, Dim, IsA16, AMDGPU::hasG16(STI)); 726 727 IsNSA = Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA; 728 if (!IsNSA) { 729 if (AddrSize > 8) 730 AddrSize = 16; 731 } else { 732 if (AddrSize > Info->VAddrDwords) { 733 // The NSA encoding does not contain enough operands for the combination 734 // of base opcode / dimension. Should this be an error? 735 return MCDisassembler::Success; 736 } 737 } 738 } 739 740 unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf; 741 unsigned DstSize = IsGather4 ? 4 : std::max(countPopulation(DMask), 1u); 742 743 bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm(); 744 if (D16 && AMDGPU::hasPackedD16(STI)) { 745 DstSize = (DstSize + 1) / 2; 746 } 747 748 if (TFEIdx != -1 && MI.getOperand(TFEIdx).getImm()) 749 DstSize += 1; 750 751 if (DstSize == Info->VDataDwords && AddrSize == Info->VAddrDwords) 752 return MCDisassembler::Success; 753 754 int NewOpcode = 755 AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize); 756 if (NewOpcode == -1) 757 return MCDisassembler::Success; 758 759 // Widen the register to the correct number of enabled channels. 760 unsigned NewVdata = AMDGPU::NoRegister; 761 if (DstSize != Info->VDataDwords) { 762 auto DataRCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass; 763 764 // Get first subregister of VData 765 unsigned Vdata0 = MI.getOperand(VDataIdx).getReg(); 766 unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0); 767 Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0; 768 769 NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0, 770 &MRI.getRegClass(DataRCID)); 771 if (NewVdata == AMDGPU::NoRegister) { 772 // It's possible to encode this such that the low register + enabled 773 // components exceeds the register count. 774 return MCDisassembler::Success; 775 } 776 } 777 778 unsigned NewVAddr0 = AMDGPU::NoRegister; 779 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10] && !IsNSA && 780 AddrSize != Info->VAddrDwords) { 781 unsigned VAddr0 = MI.getOperand(VAddr0Idx).getReg(); 782 unsigned VAddrSub0 = MRI.getSubReg(VAddr0, AMDGPU::sub0); 783 VAddr0 = (VAddrSub0 != 0) ? VAddrSub0 : VAddr0; 784 785 auto AddrRCID = MCII->get(NewOpcode).OpInfo[VAddr0Idx].RegClass; 786 NewVAddr0 = MRI.getMatchingSuperReg(VAddr0, AMDGPU::sub0, 787 &MRI.getRegClass(AddrRCID)); 788 if (NewVAddr0 == AMDGPU::NoRegister) 789 return MCDisassembler::Success; 790 } 791 792 MI.setOpcode(NewOpcode); 793 794 if (NewVdata != AMDGPU::NoRegister) { 795 MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata); 796 797 if (IsAtomic) { 798 // Atomic operations have an additional operand (a copy of data) 799 MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata); 800 } 801 } 802 803 if (NewVAddr0 != AMDGPU::NoRegister) { 804 MI.getOperand(VAddr0Idx) = MCOperand::createReg(NewVAddr0); 805 } else if (IsNSA) { 806 assert(AddrSize <= Info->VAddrDwords); 807 MI.erase(MI.begin() + VAddr0Idx + AddrSize, 808 MI.begin() + VAddr0Idx + Info->VAddrDwords); 809 } 810 811 return MCDisassembler::Success; 812 } 813 814 DecodeStatus AMDGPUDisassembler::convertFMAanyK(MCInst &MI, 815 int ImmLitIdx) const { 816 assert(HasLiteral && "Should have decoded a literal"); 817 const MCInstrDesc &Desc = MCII->get(MI.getOpcode()); 818 unsigned DescNumOps = Desc.getNumOperands(); 819 assert(DescNumOps == MI.getNumOperands()); 820 for (unsigned I = 0; I < DescNumOps; ++I) { 821 auto &Op = MI.getOperand(I); 822 auto OpType = Desc.OpInfo[I].OperandType; 823 bool IsDeferredOp = (OpType == AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED || 824 OpType == AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED); 825 if (Op.isImm() && Op.getImm() == AMDGPU::EncValues::LITERAL_CONST && 826 IsDeferredOp) 827 Op.setImm(Literal); 828 } 829 return MCDisassembler::Success; 830 } 831 832 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { 833 return getContext().getRegisterInfo()-> 834 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); 835 } 836 837 inline 838 MCOperand AMDGPUDisassembler::errOperand(unsigned V, 839 const Twine& ErrMsg) const { 840 *CommentStream << "Error: " + ErrMsg; 841 842 // ToDo: add support for error operands to MCInst.h 843 // return MCOperand::createError(V); 844 return MCOperand(); 845 } 846 847 inline 848 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const { 849 return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI)); 850 } 851 852 inline 853 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, 854 unsigned Val) const { 855 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; 856 if (Val >= RegCl.getNumRegs()) 857 return errOperand(Val, Twine(getRegClassName(RegClassID)) + 858 ": unknown register " + Twine(Val)); 859 return createRegOperand(RegCl.getRegister(Val)); 860 } 861 862 inline 863 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID, 864 unsigned Val) const { 865 // ToDo: SI/CI have 104 SGPRs, VI - 102 866 // Valery: here we accepting as much as we can, let assembler sort it out 867 int shift = 0; 868 switch (SRegClassID) { 869 case AMDGPU::SGPR_32RegClassID: 870 case AMDGPU::TTMP_32RegClassID: 871 break; 872 case AMDGPU::SGPR_64RegClassID: 873 case AMDGPU::TTMP_64RegClassID: 874 shift = 1; 875 break; 876 case AMDGPU::SGPR_128RegClassID: 877 case AMDGPU::TTMP_128RegClassID: 878 // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in 879 // this bundle? 880 case AMDGPU::SGPR_256RegClassID: 881 case AMDGPU::TTMP_256RegClassID: 882 // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in 883 // this bundle? 884 case AMDGPU::SGPR_512RegClassID: 885 case AMDGPU::TTMP_512RegClassID: 886 shift = 2; 887 break; 888 // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in 889 // this bundle? 890 default: 891 llvm_unreachable("unhandled register class"); 892 } 893 894 if (Val % (1 << shift)) { 895 *CommentStream << "Warning: " << getRegClassName(SRegClassID) 896 << ": scalar reg isn't aligned " << Val; 897 } 898 899 return createRegOperand(SRegClassID, Val >> shift); 900 } 901 902 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const { 903 return decodeSrcOp(OPW32, Val); 904 } 905 906 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const { 907 return decodeSrcOp(OPW64, Val); 908 } 909 910 MCOperand AMDGPUDisassembler::decodeOperand_VS_128(unsigned Val) const { 911 return decodeSrcOp(OPW128, Val); 912 } 913 914 MCOperand AMDGPUDisassembler::decodeOperand_VSrc16(unsigned Val) const { 915 return decodeSrcOp(OPW16, Val); 916 } 917 918 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV216(unsigned Val) const { 919 return decodeSrcOp(OPWV216, Val); 920 } 921 922 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV232(unsigned Val) const { 923 return decodeSrcOp(OPWV232, Val); 924 } 925 926 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const { 927 // Some instructions have operand restrictions beyond what the encoding 928 // allows. Some ordinarily VSrc_32 operands are VGPR_32, so clear the extra 929 // high bit. 930 Val &= 255; 931 932 return createRegOperand(AMDGPU::VGPR_32RegClassID, Val); 933 } 934 935 MCOperand AMDGPUDisassembler::decodeOperand_VRegOrLds_32(unsigned Val) const { 936 return decodeSrcOp(OPW32, Val); 937 } 938 939 MCOperand AMDGPUDisassembler::decodeOperand_AGPR_32(unsigned Val) const { 940 return createRegOperand(AMDGPU::AGPR_32RegClassID, Val & 255); 941 } 942 943 MCOperand AMDGPUDisassembler::decodeOperand_AReg_64(unsigned Val) const { 944 return createRegOperand(AMDGPU::AReg_64RegClassID, Val & 255); 945 } 946 947 MCOperand AMDGPUDisassembler::decodeOperand_AReg_128(unsigned Val) const { 948 return createRegOperand(AMDGPU::AReg_128RegClassID, Val & 255); 949 } 950 951 MCOperand AMDGPUDisassembler::decodeOperand_AReg_256(unsigned Val) const { 952 return createRegOperand(AMDGPU::AReg_256RegClassID, Val & 255); 953 } 954 955 MCOperand AMDGPUDisassembler::decodeOperand_AReg_512(unsigned Val) const { 956 return createRegOperand(AMDGPU::AReg_512RegClassID, Val & 255); 957 } 958 959 MCOperand AMDGPUDisassembler::decodeOperand_AReg_1024(unsigned Val) const { 960 return createRegOperand(AMDGPU::AReg_1024RegClassID, Val & 255); 961 } 962 963 MCOperand AMDGPUDisassembler::decodeOperand_AV_32(unsigned Val) const { 964 return decodeSrcOp(OPW32, Val); 965 } 966 967 MCOperand AMDGPUDisassembler::decodeOperand_AV_64(unsigned Val) const { 968 return decodeSrcOp(OPW64, Val); 969 } 970 971 MCOperand AMDGPUDisassembler::decodeOperand_AV_128(unsigned Val) const { 972 return decodeSrcOp(OPW128, Val); 973 } 974 975 MCOperand AMDGPUDisassembler::decodeOperand_AV_512(unsigned Val) const { 976 return decodeSrcOp(OPW512, Val); 977 } 978 979 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const { 980 return createRegOperand(AMDGPU::VReg_64RegClassID, Val); 981 } 982 983 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const { 984 return createRegOperand(AMDGPU::VReg_96RegClassID, Val); 985 } 986 987 MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const { 988 return createRegOperand(AMDGPU::VReg_128RegClassID, Val); 989 } 990 991 MCOperand AMDGPUDisassembler::decodeOperand_VReg_256(unsigned Val) const { 992 return createRegOperand(AMDGPU::VReg_256RegClassID, Val); 993 } 994 995 MCOperand AMDGPUDisassembler::decodeOperand_VReg_512(unsigned Val) const { 996 return createRegOperand(AMDGPU::VReg_512RegClassID, Val); 997 } 998 999 MCOperand AMDGPUDisassembler::decodeOperand_VReg_1024(unsigned Val) const { 1000 return createRegOperand(AMDGPU::VReg_1024RegClassID, Val); 1001 } 1002 1003 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const { 1004 // table-gen generated disassembler doesn't care about operand types 1005 // leaving only registry class so SSrc_32 operand turns into SReg_32 1006 // and therefore we accept immediates and literals here as well 1007 return decodeSrcOp(OPW32, Val); 1008 } 1009 1010 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0_XEXEC( 1011 unsigned Val) const { 1012 // SReg_32_XM0 is SReg_32 without M0 or EXEC_LO/EXEC_HI 1013 return decodeOperand_SReg_32(Val); 1014 } 1015 1016 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XEXEC_HI( 1017 unsigned Val) const { 1018 // SReg_32_XM0 is SReg_32 without EXEC_HI 1019 return decodeOperand_SReg_32(Val); 1020 } 1021 1022 MCOperand AMDGPUDisassembler::decodeOperand_SRegOrLds_32(unsigned Val) const { 1023 // table-gen generated disassembler doesn't care about operand types 1024 // leaving only registry class so SSrc_32 operand turns into SReg_32 1025 // and therefore we accept immediates and literals here as well 1026 return decodeSrcOp(OPW32, Val); 1027 } 1028 1029 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const { 1030 return decodeSrcOp(OPW64, Val); 1031 } 1032 1033 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64_XEXEC(unsigned Val) const { 1034 return decodeSrcOp(OPW64, Val); 1035 } 1036 1037 MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const { 1038 return decodeSrcOp(OPW128, Val); 1039 } 1040 1041 MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const { 1042 return decodeDstOp(OPW256, Val); 1043 } 1044 1045 MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const { 1046 return decodeDstOp(OPW512, Val); 1047 } 1048 1049 // Decode Literals for insts which always have a literal in the encoding 1050 MCOperand 1051 AMDGPUDisassembler::decodeMandatoryLiteralConstant(unsigned Val) const { 1052 if (HasLiteral) { 1053 if (Literal != Val) 1054 return errOperand(Val, "More than one unique literal is illegal"); 1055 } 1056 HasLiteral = true; 1057 Literal = Val; 1058 return MCOperand::createImm(Literal); 1059 } 1060 1061 MCOperand AMDGPUDisassembler::decodeLiteralConstant() const { 1062 // For now all literal constants are supposed to be unsigned integer 1063 // ToDo: deal with signed/unsigned 64-bit integer constants 1064 // ToDo: deal with float/double constants 1065 if (!HasLiteral) { 1066 if (Bytes.size() < 4) { 1067 return errOperand(0, "cannot read literal, inst bytes left " + 1068 Twine(Bytes.size())); 1069 } 1070 HasLiteral = true; 1071 Literal = eatBytes<uint32_t>(Bytes); 1072 } 1073 return MCOperand::createImm(Literal); 1074 } 1075 1076 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) { 1077 using namespace AMDGPU::EncValues; 1078 1079 assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX); 1080 return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ? 1081 (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) : 1082 (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm))); 1083 // Cast prevents negative overflow. 1084 } 1085 1086 static int64_t getInlineImmVal32(unsigned Imm) { 1087 switch (Imm) { 1088 case 240: 1089 return FloatToBits(0.5f); 1090 case 241: 1091 return FloatToBits(-0.5f); 1092 case 242: 1093 return FloatToBits(1.0f); 1094 case 243: 1095 return FloatToBits(-1.0f); 1096 case 244: 1097 return FloatToBits(2.0f); 1098 case 245: 1099 return FloatToBits(-2.0f); 1100 case 246: 1101 return FloatToBits(4.0f); 1102 case 247: 1103 return FloatToBits(-4.0f); 1104 case 248: // 1 / (2 * PI) 1105 return 0x3e22f983; 1106 default: 1107 llvm_unreachable("invalid fp inline imm"); 1108 } 1109 } 1110 1111 static int64_t getInlineImmVal64(unsigned Imm) { 1112 switch (Imm) { 1113 case 240: 1114 return DoubleToBits(0.5); 1115 case 241: 1116 return DoubleToBits(-0.5); 1117 case 242: 1118 return DoubleToBits(1.0); 1119 case 243: 1120 return DoubleToBits(-1.0); 1121 case 244: 1122 return DoubleToBits(2.0); 1123 case 245: 1124 return DoubleToBits(-2.0); 1125 case 246: 1126 return DoubleToBits(4.0); 1127 case 247: 1128 return DoubleToBits(-4.0); 1129 case 248: // 1 / (2 * PI) 1130 return 0x3fc45f306dc9c882; 1131 default: 1132 llvm_unreachable("invalid fp inline imm"); 1133 } 1134 } 1135 1136 static int64_t getInlineImmVal16(unsigned Imm) { 1137 switch (Imm) { 1138 case 240: 1139 return 0x3800; 1140 case 241: 1141 return 0xB800; 1142 case 242: 1143 return 0x3C00; 1144 case 243: 1145 return 0xBC00; 1146 case 244: 1147 return 0x4000; 1148 case 245: 1149 return 0xC000; 1150 case 246: 1151 return 0x4400; 1152 case 247: 1153 return 0xC400; 1154 case 248: // 1 / (2 * PI) 1155 return 0x3118; 1156 default: 1157 llvm_unreachable("invalid fp inline imm"); 1158 } 1159 } 1160 1161 MCOperand AMDGPUDisassembler::decodeFPImmed(OpWidthTy Width, unsigned Imm) { 1162 assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN 1163 && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX); 1164 1165 // ToDo: case 248: 1/(2*PI) - is allowed only on VI 1166 switch (Width) { 1167 case OPW32: 1168 case OPW128: // splat constants 1169 case OPW512: 1170 case OPW1024: 1171 case OPWV232: 1172 return MCOperand::createImm(getInlineImmVal32(Imm)); 1173 case OPW64: 1174 case OPW256: 1175 return MCOperand::createImm(getInlineImmVal64(Imm)); 1176 case OPW16: 1177 case OPWV216: 1178 return MCOperand::createImm(getInlineImmVal16(Imm)); 1179 default: 1180 llvm_unreachable("implement me"); 1181 } 1182 } 1183 1184 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const { 1185 using namespace AMDGPU; 1186 1187 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1188 switch (Width) { 1189 default: // fall 1190 case OPW32: 1191 case OPW16: 1192 case OPWV216: 1193 return VGPR_32RegClassID; 1194 case OPW64: 1195 case OPWV232: return VReg_64RegClassID; 1196 case OPW96: return VReg_96RegClassID; 1197 case OPW128: return VReg_128RegClassID; 1198 case OPW160: return VReg_160RegClassID; 1199 case OPW256: return VReg_256RegClassID; 1200 case OPW512: return VReg_512RegClassID; 1201 case OPW1024: return VReg_1024RegClassID; 1202 } 1203 } 1204 1205 unsigned AMDGPUDisassembler::getAgprClassId(const OpWidthTy Width) const { 1206 using namespace AMDGPU; 1207 1208 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1209 switch (Width) { 1210 default: // fall 1211 case OPW32: 1212 case OPW16: 1213 case OPWV216: 1214 return AGPR_32RegClassID; 1215 case OPW64: 1216 case OPWV232: return AReg_64RegClassID; 1217 case OPW96: return AReg_96RegClassID; 1218 case OPW128: return AReg_128RegClassID; 1219 case OPW160: return AReg_160RegClassID; 1220 case OPW256: return AReg_256RegClassID; 1221 case OPW512: return AReg_512RegClassID; 1222 case OPW1024: return AReg_1024RegClassID; 1223 } 1224 } 1225 1226 1227 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const { 1228 using namespace AMDGPU; 1229 1230 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1231 switch (Width) { 1232 default: // fall 1233 case OPW32: 1234 case OPW16: 1235 case OPWV216: 1236 return SGPR_32RegClassID; 1237 case OPW64: 1238 case OPWV232: return SGPR_64RegClassID; 1239 case OPW96: return SGPR_96RegClassID; 1240 case OPW128: return SGPR_128RegClassID; 1241 case OPW160: return SGPR_160RegClassID; 1242 case OPW256: return SGPR_256RegClassID; 1243 case OPW512: return SGPR_512RegClassID; 1244 } 1245 } 1246 1247 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const { 1248 using namespace AMDGPU; 1249 1250 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1251 switch (Width) { 1252 default: // fall 1253 case OPW32: 1254 case OPW16: 1255 case OPWV216: 1256 return TTMP_32RegClassID; 1257 case OPW64: 1258 case OPWV232: return TTMP_64RegClassID; 1259 case OPW128: return TTMP_128RegClassID; 1260 case OPW256: return TTMP_256RegClassID; 1261 case OPW512: return TTMP_512RegClassID; 1262 } 1263 } 1264 1265 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const { 1266 using namespace AMDGPU::EncValues; 1267 1268 unsigned TTmpMin = isGFX9Plus() ? TTMP_GFX9PLUS_MIN : TTMP_VI_MIN; 1269 unsigned TTmpMax = isGFX9Plus() ? TTMP_GFX9PLUS_MAX : TTMP_VI_MAX; 1270 1271 return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1; 1272 } 1273 1274 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val, 1275 bool MandatoryLiteral) const { 1276 using namespace AMDGPU::EncValues; 1277 1278 assert(Val < 1024); // enum10 1279 1280 bool IsAGPR = Val & 512; 1281 Val &= 511; 1282 1283 if (VGPR_MIN <= Val && Val <= VGPR_MAX) { 1284 return createRegOperand(IsAGPR ? getAgprClassId(Width) 1285 : getVgprClassId(Width), Val - VGPR_MIN); 1286 } 1287 if (Val <= SGPR_MAX) { 1288 // "SGPR_MIN <= Val" is always true and causes compilation warning. 1289 static_assert(SGPR_MIN == 0, ""); 1290 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1291 } 1292 1293 int TTmpIdx = getTTmpIdx(Val); 1294 if (TTmpIdx >= 0) { 1295 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1296 } 1297 1298 if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX) 1299 return decodeIntImmed(Val); 1300 1301 if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX) 1302 return decodeFPImmed(Width, Val); 1303 1304 if (Val == LITERAL_CONST) { 1305 if (MandatoryLiteral) 1306 // Keep a sentinel value for deferred setting 1307 return MCOperand::createImm(LITERAL_CONST); 1308 else 1309 return decodeLiteralConstant(); 1310 } 1311 1312 switch (Width) { 1313 case OPW32: 1314 case OPW16: 1315 case OPWV216: 1316 return decodeSpecialReg32(Val); 1317 case OPW64: 1318 case OPWV232: 1319 return decodeSpecialReg64(Val); 1320 default: 1321 llvm_unreachable("unexpected immediate type"); 1322 } 1323 } 1324 1325 MCOperand AMDGPUDisassembler::decodeDstOp(const OpWidthTy Width, unsigned Val) const { 1326 using namespace AMDGPU::EncValues; 1327 1328 assert(Val < 128); 1329 assert(Width == OPW256 || Width == OPW512); 1330 1331 if (Val <= SGPR_MAX) { 1332 // "SGPR_MIN <= Val" is always true and causes compilation warning. 1333 static_assert(SGPR_MIN == 0, ""); 1334 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1335 } 1336 1337 int TTmpIdx = getTTmpIdx(Val); 1338 if (TTmpIdx >= 0) { 1339 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1340 } 1341 1342 llvm_unreachable("unknown dst register"); 1343 } 1344 1345 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { 1346 using namespace AMDGPU; 1347 1348 switch (Val) { 1349 case 102: return createRegOperand(FLAT_SCR_LO); 1350 case 103: return createRegOperand(FLAT_SCR_HI); 1351 case 104: return createRegOperand(XNACK_MASK_LO); 1352 case 105: return createRegOperand(XNACK_MASK_HI); 1353 case 106: return createRegOperand(VCC_LO); 1354 case 107: return createRegOperand(VCC_HI); 1355 case 108: return createRegOperand(TBA_LO); 1356 case 109: return createRegOperand(TBA_HI); 1357 case 110: return createRegOperand(TMA_LO); 1358 case 111: return createRegOperand(TMA_HI); 1359 case 124: 1360 return isGFX11Plus() ? createRegOperand(SGPR_NULL) : createRegOperand(M0); 1361 case 125: 1362 return isGFX11Plus() ? createRegOperand(M0) : createRegOperand(SGPR_NULL); 1363 case 126: return createRegOperand(EXEC_LO); 1364 case 127: return createRegOperand(EXEC_HI); 1365 case 235: return createRegOperand(SRC_SHARED_BASE); 1366 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1367 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1368 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1369 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1370 case 251: return createRegOperand(SRC_VCCZ); 1371 case 252: return createRegOperand(SRC_EXECZ); 1372 case 253: return createRegOperand(SRC_SCC); 1373 case 254: return createRegOperand(LDS_DIRECT); 1374 default: break; 1375 } 1376 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1377 } 1378 1379 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { 1380 using namespace AMDGPU; 1381 1382 switch (Val) { 1383 case 102: return createRegOperand(FLAT_SCR); 1384 case 104: return createRegOperand(XNACK_MASK); 1385 case 106: return createRegOperand(VCC); 1386 case 108: return createRegOperand(TBA); 1387 case 110: return createRegOperand(TMA); 1388 case 124: 1389 if (isGFX11Plus()) 1390 return createRegOperand(SGPR_NULL); 1391 break; 1392 case 125: 1393 if (!isGFX11Plus()) 1394 return createRegOperand(SGPR_NULL); 1395 break; 1396 case 126: return createRegOperand(EXEC); 1397 case 235: return createRegOperand(SRC_SHARED_BASE); 1398 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1399 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1400 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1401 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1402 case 251: return createRegOperand(SRC_VCCZ); 1403 case 252: return createRegOperand(SRC_EXECZ); 1404 case 253: return createRegOperand(SRC_SCC); 1405 default: break; 1406 } 1407 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1408 } 1409 1410 MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width, 1411 const unsigned Val) const { 1412 using namespace AMDGPU::SDWA; 1413 using namespace AMDGPU::EncValues; 1414 1415 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 1416 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 1417 // XXX: cast to int is needed to avoid stupid warning: 1418 // compare with unsigned is always true 1419 if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) && 1420 Val <= SDWA9EncValues::SRC_VGPR_MAX) { 1421 return createRegOperand(getVgprClassId(Width), 1422 Val - SDWA9EncValues::SRC_VGPR_MIN); 1423 } 1424 if (SDWA9EncValues::SRC_SGPR_MIN <= Val && 1425 Val <= (isGFX10Plus() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10 1426 : SDWA9EncValues::SRC_SGPR_MAX_SI)) { 1427 return createSRegOperand(getSgprClassId(Width), 1428 Val - SDWA9EncValues::SRC_SGPR_MIN); 1429 } 1430 if (SDWA9EncValues::SRC_TTMP_MIN <= Val && 1431 Val <= SDWA9EncValues::SRC_TTMP_MAX) { 1432 return createSRegOperand(getTtmpClassId(Width), 1433 Val - SDWA9EncValues::SRC_TTMP_MIN); 1434 } 1435 1436 const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN; 1437 1438 if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX) 1439 return decodeIntImmed(SVal); 1440 1441 if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX) 1442 return decodeFPImmed(Width, SVal); 1443 1444 return decodeSpecialReg32(SVal); 1445 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 1446 return createRegOperand(getVgprClassId(Width), Val); 1447 } 1448 llvm_unreachable("unsupported target"); 1449 } 1450 1451 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const { 1452 return decodeSDWASrc(OPW16, Val); 1453 } 1454 1455 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const { 1456 return decodeSDWASrc(OPW32, Val); 1457 } 1458 1459 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const { 1460 using namespace AMDGPU::SDWA; 1461 1462 assert((STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 1463 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) && 1464 "SDWAVopcDst should be present only on GFX9+"); 1465 1466 bool IsWave64 = STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64]; 1467 1468 if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) { 1469 Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK; 1470 1471 int TTmpIdx = getTTmpIdx(Val); 1472 if (TTmpIdx >= 0) { 1473 auto TTmpClsId = getTtmpClassId(IsWave64 ? OPW64 : OPW32); 1474 return createSRegOperand(TTmpClsId, TTmpIdx); 1475 } else if (Val > SGPR_MAX) { 1476 return IsWave64 ? decodeSpecialReg64(Val) 1477 : decodeSpecialReg32(Val); 1478 } else { 1479 return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val); 1480 } 1481 } else { 1482 return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO); 1483 } 1484 } 1485 1486 MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const { 1487 return STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ? 1488 decodeOperand_SReg_64(Val) : decodeOperand_SReg_32(Val); 1489 } 1490 1491 bool AMDGPUDisassembler::isVI() const { 1492 return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]; 1493 } 1494 1495 bool AMDGPUDisassembler::isGFX9() const { return AMDGPU::isGFX9(STI); } 1496 1497 bool AMDGPUDisassembler::isGFX90A() const { 1498 return STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]; 1499 } 1500 1501 bool AMDGPUDisassembler::isGFX9Plus() const { return AMDGPU::isGFX9Plus(STI); } 1502 1503 bool AMDGPUDisassembler::isGFX10() const { return AMDGPU::isGFX10(STI); } 1504 1505 bool AMDGPUDisassembler::isGFX10Plus() const { 1506 return AMDGPU::isGFX10Plus(STI); 1507 } 1508 1509 bool AMDGPUDisassembler::isGFX11() const { 1510 return STI.getFeatureBits()[AMDGPU::FeatureGFX11]; 1511 } 1512 1513 bool AMDGPUDisassembler::isGFX11Plus() const { 1514 return AMDGPU::isGFX11Plus(STI); 1515 } 1516 1517 1518 bool AMDGPUDisassembler::hasArchitectedFlatScratch() const { 1519 return STI.getFeatureBits()[AMDGPU::FeatureArchitectedFlatScratch]; 1520 } 1521 1522 //===----------------------------------------------------------------------===// 1523 // AMDGPU specific symbol handling 1524 //===----------------------------------------------------------------------===// 1525 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1526 do { \ 1527 KdStream << Indent << DIRECTIVE " " \ 1528 << ((FourByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 1529 } while (0) 1530 1531 // NOLINTNEXTLINE(readability-identifier-naming) 1532 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1( 1533 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1534 using namespace amdhsa; 1535 StringRef Indent = "\t"; 1536 1537 // We cannot accurately backward compute #VGPRs used from 1538 // GRANULATED_WORKITEM_VGPR_COUNT. But we are concerned with getting the same 1539 // value of GRANULATED_WORKITEM_VGPR_COUNT in the reassembled binary. So we 1540 // simply calculate the inverse of what the assembler does. 1541 1542 uint32_t GranulatedWorkitemVGPRCount = 1543 (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT) >> 1544 COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT_SHIFT; 1545 1546 uint32_t NextFreeVGPR = (GranulatedWorkitemVGPRCount + 1) * 1547 AMDGPU::IsaInfo::getVGPREncodingGranule(&STI); 1548 1549 KdStream << Indent << ".amdhsa_next_free_vgpr " << NextFreeVGPR << '\n'; 1550 1551 // We cannot backward compute values used to calculate 1552 // GRANULATED_WAVEFRONT_SGPR_COUNT. Hence the original values for following 1553 // directives can't be computed: 1554 // .amdhsa_reserve_vcc 1555 // .amdhsa_reserve_flat_scratch 1556 // .amdhsa_reserve_xnack_mask 1557 // They take their respective default values if not specified in the assembly. 1558 // 1559 // GRANULATED_WAVEFRONT_SGPR_COUNT 1560 // = f(NEXT_FREE_SGPR + VCC + FLAT_SCRATCH + XNACK_MASK) 1561 // 1562 // We compute the inverse as though all directives apart from NEXT_FREE_SGPR 1563 // are set to 0. So while disassembling we consider that: 1564 // 1565 // GRANULATED_WAVEFRONT_SGPR_COUNT 1566 // = f(NEXT_FREE_SGPR + 0 + 0 + 0) 1567 // 1568 // The disassembler cannot recover the original values of those 3 directives. 1569 1570 uint32_t GranulatedWavefrontSGPRCount = 1571 (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT) >> 1572 COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT_SHIFT; 1573 1574 if (isGFX10Plus() && GranulatedWavefrontSGPRCount) 1575 return MCDisassembler::Fail; 1576 1577 uint32_t NextFreeSGPR = (GranulatedWavefrontSGPRCount + 1) * 1578 AMDGPU::IsaInfo::getSGPREncodingGranule(&STI); 1579 1580 KdStream << Indent << ".amdhsa_reserve_vcc " << 0 << '\n'; 1581 if (!hasArchitectedFlatScratch()) 1582 KdStream << Indent << ".amdhsa_reserve_flat_scratch " << 0 << '\n'; 1583 KdStream << Indent << ".amdhsa_reserve_xnack_mask " << 0 << '\n'; 1584 KdStream << Indent << ".amdhsa_next_free_sgpr " << NextFreeSGPR << "\n"; 1585 1586 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIORITY) 1587 return MCDisassembler::Fail; 1588 1589 PRINT_DIRECTIVE(".amdhsa_float_round_mode_32", 1590 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); 1591 PRINT_DIRECTIVE(".amdhsa_float_round_mode_16_64", 1592 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); 1593 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_32", 1594 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); 1595 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_16_64", 1596 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); 1597 1598 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIV) 1599 return MCDisassembler::Fail; 1600 1601 PRINT_DIRECTIVE(".amdhsa_dx10_clamp", COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP); 1602 1603 if (FourByteBuffer & COMPUTE_PGM_RSRC1_DEBUG_MODE) 1604 return MCDisassembler::Fail; 1605 1606 PRINT_DIRECTIVE(".amdhsa_ieee_mode", COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE); 1607 1608 if (FourByteBuffer & COMPUTE_PGM_RSRC1_BULKY) 1609 return MCDisassembler::Fail; 1610 1611 if (FourByteBuffer & COMPUTE_PGM_RSRC1_CDBG_USER) 1612 return MCDisassembler::Fail; 1613 1614 PRINT_DIRECTIVE(".amdhsa_fp16_overflow", COMPUTE_PGM_RSRC1_FP16_OVFL); 1615 1616 if (FourByteBuffer & COMPUTE_PGM_RSRC1_RESERVED0) 1617 return MCDisassembler::Fail; 1618 1619 if (isGFX10Plus()) { 1620 PRINT_DIRECTIVE(".amdhsa_workgroup_processor_mode", 1621 COMPUTE_PGM_RSRC1_WGP_MODE); 1622 PRINT_DIRECTIVE(".amdhsa_memory_ordered", COMPUTE_PGM_RSRC1_MEM_ORDERED); 1623 PRINT_DIRECTIVE(".amdhsa_forward_progress", COMPUTE_PGM_RSRC1_FWD_PROGRESS); 1624 } 1625 return MCDisassembler::Success; 1626 } 1627 1628 // NOLINTNEXTLINE(readability-identifier-naming) 1629 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2( 1630 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1631 using namespace amdhsa; 1632 StringRef Indent = "\t"; 1633 if (hasArchitectedFlatScratch()) 1634 PRINT_DIRECTIVE(".amdhsa_enable_private_segment", 1635 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1636 else 1637 PRINT_DIRECTIVE(".amdhsa_system_sgpr_private_segment_wavefront_offset", 1638 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1639 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_x", 1640 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); 1641 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_y", 1642 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); 1643 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_z", 1644 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); 1645 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_info", 1646 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); 1647 PRINT_DIRECTIVE(".amdhsa_system_vgpr_workitem_id", 1648 COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); 1649 1650 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_ADDRESS_WATCH) 1651 return MCDisassembler::Fail; 1652 1653 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_MEMORY) 1654 return MCDisassembler::Fail; 1655 1656 if (FourByteBuffer & COMPUTE_PGM_RSRC2_GRANULATED_LDS_SIZE) 1657 return MCDisassembler::Fail; 1658 1659 PRINT_DIRECTIVE( 1660 ".amdhsa_exception_fp_ieee_invalid_op", 1661 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); 1662 PRINT_DIRECTIVE(".amdhsa_exception_fp_denorm_src", 1663 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); 1664 PRINT_DIRECTIVE( 1665 ".amdhsa_exception_fp_ieee_div_zero", 1666 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); 1667 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_overflow", 1668 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); 1669 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_underflow", 1670 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); 1671 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_inexact", 1672 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); 1673 PRINT_DIRECTIVE(".amdhsa_exception_int_div_zero", 1674 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); 1675 1676 if (FourByteBuffer & COMPUTE_PGM_RSRC2_RESERVED0) 1677 return MCDisassembler::Fail; 1678 1679 return MCDisassembler::Success; 1680 } 1681 1682 #undef PRINT_DIRECTIVE 1683 1684 MCDisassembler::DecodeStatus 1685 AMDGPUDisassembler::decodeKernelDescriptorDirective( 1686 DataExtractor::Cursor &Cursor, ArrayRef<uint8_t> Bytes, 1687 raw_string_ostream &KdStream) const { 1688 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1689 do { \ 1690 KdStream << Indent << DIRECTIVE " " \ 1691 << ((TwoByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 1692 } while (0) 1693 1694 uint16_t TwoByteBuffer = 0; 1695 uint32_t FourByteBuffer = 0; 1696 1697 StringRef ReservedBytes; 1698 StringRef Indent = "\t"; 1699 1700 assert(Bytes.size() == 64); 1701 DataExtractor DE(Bytes, /*IsLittleEndian=*/true, /*AddressSize=*/8); 1702 1703 switch (Cursor.tell()) { 1704 case amdhsa::GROUP_SEGMENT_FIXED_SIZE_OFFSET: 1705 FourByteBuffer = DE.getU32(Cursor); 1706 KdStream << Indent << ".amdhsa_group_segment_fixed_size " << FourByteBuffer 1707 << '\n'; 1708 return MCDisassembler::Success; 1709 1710 case amdhsa::PRIVATE_SEGMENT_FIXED_SIZE_OFFSET: 1711 FourByteBuffer = DE.getU32(Cursor); 1712 KdStream << Indent << ".amdhsa_private_segment_fixed_size " 1713 << FourByteBuffer << '\n'; 1714 return MCDisassembler::Success; 1715 1716 case amdhsa::KERNARG_SIZE_OFFSET: 1717 FourByteBuffer = DE.getU32(Cursor); 1718 KdStream << Indent << ".amdhsa_kernarg_size " 1719 << FourByteBuffer << '\n'; 1720 return MCDisassembler::Success; 1721 1722 case amdhsa::RESERVED0_OFFSET: 1723 // 4 reserved bytes, must be 0. 1724 ReservedBytes = DE.getBytes(Cursor, 4); 1725 for (int I = 0; I < 4; ++I) { 1726 if (ReservedBytes[I] != 0) { 1727 return MCDisassembler::Fail; 1728 } 1729 } 1730 return MCDisassembler::Success; 1731 1732 case amdhsa::KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET: 1733 // KERNEL_CODE_ENTRY_BYTE_OFFSET 1734 // So far no directive controls this for Code Object V3, so simply skip for 1735 // disassembly. 1736 DE.skip(Cursor, 8); 1737 return MCDisassembler::Success; 1738 1739 case amdhsa::RESERVED1_OFFSET: 1740 // 20 reserved bytes, must be 0. 1741 ReservedBytes = DE.getBytes(Cursor, 20); 1742 for (int I = 0; I < 20; ++I) { 1743 if (ReservedBytes[I] != 0) { 1744 return MCDisassembler::Fail; 1745 } 1746 } 1747 return MCDisassembler::Success; 1748 1749 case amdhsa::COMPUTE_PGM_RSRC3_OFFSET: 1750 // COMPUTE_PGM_RSRC3 1751 // - Only set for GFX10, GFX6-9 have this to be 0. 1752 // - Currently no directives directly control this. 1753 FourByteBuffer = DE.getU32(Cursor); 1754 if (!isGFX10Plus() && FourByteBuffer) { 1755 return MCDisassembler::Fail; 1756 } 1757 return MCDisassembler::Success; 1758 1759 case amdhsa::COMPUTE_PGM_RSRC1_OFFSET: 1760 FourByteBuffer = DE.getU32(Cursor); 1761 if (decodeCOMPUTE_PGM_RSRC1(FourByteBuffer, KdStream) == 1762 MCDisassembler::Fail) { 1763 return MCDisassembler::Fail; 1764 } 1765 return MCDisassembler::Success; 1766 1767 case amdhsa::COMPUTE_PGM_RSRC2_OFFSET: 1768 FourByteBuffer = DE.getU32(Cursor); 1769 if (decodeCOMPUTE_PGM_RSRC2(FourByteBuffer, KdStream) == 1770 MCDisassembler::Fail) { 1771 return MCDisassembler::Fail; 1772 } 1773 return MCDisassembler::Success; 1774 1775 case amdhsa::KERNEL_CODE_PROPERTIES_OFFSET: 1776 using namespace amdhsa; 1777 TwoByteBuffer = DE.getU16(Cursor); 1778 1779 if (!hasArchitectedFlatScratch()) 1780 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_buffer", 1781 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); 1782 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_ptr", 1783 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); 1784 PRINT_DIRECTIVE(".amdhsa_user_sgpr_queue_ptr", 1785 KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); 1786 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_segment_ptr", 1787 KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); 1788 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_id", 1789 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); 1790 if (!hasArchitectedFlatScratch()) 1791 PRINT_DIRECTIVE(".amdhsa_user_sgpr_flat_scratch_init", 1792 KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); 1793 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_size", 1794 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); 1795 1796 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED0) 1797 return MCDisassembler::Fail; 1798 1799 // Reserved for GFX9 1800 if (isGFX9() && 1801 (TwoByteBuffer & KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32)) { 1802 return MCDisassembler::Fail; 1803 } else if (isGFX10Plus()) { 1804 PRINT_DIRECTIVE(".amdhsa_wavefront_size32", 1805 KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 1806 } 1807 1808 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED1) 1809 return MCDisassembler::Fail; 1810 1811 return MCDisassembler::Success; 1812 1813 case amdhsa::RESERVED2_OFFSET: 1814 // 6 bytes from here are reserved, must be 0. 1815 ReservedBytes = DE.getBytes(Cursor, 6); 1816 for (int I = 0; I < 6; ++I) { 1817 if (ReservedBytes[I] != 0) 1818 return MCDisassembler::Fail; 1819 } 1820 return MCDisassembler::Success; 1821 1822 default: 1823 llvm_unreachable("Unhandled index. Case statements cover everything."); 1824 return MCDisassembler::Fail; 1825 } 1826 #undef PRINT_DIRECTIVE 1827 } 1828 1829 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeKernelDescriptor( 1830 StringRef KdName, ArrayRef<uint8_t> Bytes, uint64_t KdAddress) const { 1831 // CP microcode requires the kernel descriptor to be 64 aligned. 1832 if (Bytes.size() != 64 || KdAddress % 64 != 0) 1833 return MCDisassembler::Fail; 1834 1835 std::string Kd; 1836 raw_string_ostream KdStream(Kd); 1837 KdStream << ".amdhsa_kernel " << KdName << '\n'; 1838 1839 DataExtractor::Cursor C(0); 1840 while (C && C.tell() < Bytes.size()) { 1841 MCDisassembler::DecodeStatus Status = 1842 decodeKernelDescriptorDirective(C, Bytes, KdStream); 1843 1844 cantFail(C.takeError()); 1845 1846 if (Status == MCDisassembler::Fail) 1847 return MCDisassembler::Fail; 1848 } 1849 KdStream << ".end_amdhsa_kernel\n"; 1850 outs() << KdStream.str(); 1851 return MCDisassembler::Success; 1852 } 1853 1854 Optional<MCDisassembler::DecodeStatus> 1855 AMDGPUDisassembler::onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, 1856 ArrayRef<uint8_t> Bytes, uint64_t Address, 1857 raw_ostream &CStream) const { 1858 // Right now only kernel descriptor needs to be handled. 1859 // We ignore all other symbols for target specific handling. 1860 // TODO: 1861 // Fix the spurious symbol issue for AMDGPU kernels. Exists for both Code 1862 // Object V2 and V3 when symbols are marked protected. 1863 1864 // amd_kernel_code_t for Code Object V2. 1865 if (Symbol.Type == ELF::STT_AMDGPU_HSA_KERNEL) { 1866 Size = 256; 1867 return MCDisassembler::Fail; 1868 } 1869 1870 // Code Object V3 kernel descriptors. 1871 StringRef Name = Symbol.Name; 1872 if (Symbol.Type == ELF::STT_OBJECT && Name.endswith(StringRef(".kd"))) { 1873 Size = 64; // Size = 64 regardless of success or failure. 1874 return decodeKernelDescriptor(Name.drop_back(3), Bytes, Address); 1875 } 1876 return None; 1877 } 1878 1879 //===----------------------------------------------------------------------===// 1880 // AMDGPUSymbolizer 1881 //===----------------------------------------------------------------------===// 1882 1883 // Try to find symbol name for specified label 1884 bool AMDGPUSymbolizer::tryAddingSymbolicOperand(MCInst &Inst, 1885 raw_ostream &/*cStream*/, int64_t Value, 1886 uint64_t /*Address*/, bool IsBranch, 1887 uint64_t /*Offset*/, uint64_t /*InstSize*/) { 1888 1889 if (!IsBranch) { 1890 return false; 1891 } 1892 1893 auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo); 1894 if (!Symbols) 1895 return false; 1896 1897 auto Result = llvm::find_if(*Symbols, [Value](const SymbolInfoTy &Val) { 1898 return Val.Addr == static_cast<uint64_t>(Value) && 1899 Val.Type == ELF::STT_NOTYPE; 1900 }); 1901 if (Result != Symbols->end()) { 1902 auto *Sym = Ctx.getOrCreateSymbol(Result->Name); 1903 const auto *Add = MCSymbolRefExpr::create(Sym, Ctx); 1904 Inst.addOperand(MCOperand::createExpr(Add)); 1905 return true; 1906 } 1907 // Add to list of referenced addresses, so caller can synthesize a label. 1908 ReferencedAddresses.push_back(static_cast<uint64_t>(Value)); 1909 return false; 1910 } 1911 1912 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream, 1913 int64_t Value, 1914 uint64_t Address) { 1915 llvm_unreachable("unimplemented"); 1916 } 1917 1918 //===----------------------------------------------------------------------===// 1919 // Initialization 1920 //===----------------------------------------------------------------------===// 1921 1922 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/, 1923 LLVMOpInfoCallback /*GetOpInfo*/, 1924 LLVMSymbolLookupCallback /*SymbolLookUp*/, 1925 void *DisInfo, 1926 MCContext *Ctx, 1927 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 1928 return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo); 1929 } 1930 1931 static MCDisassembler *createAMDGPUDisassembler(const Target &T, 1932 const MCSubtargetInfo &STI, 1933 MCContext &Ctx) { 1934 return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo()); 1935 } 1936 1937 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler() { 1938 TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(), 1939 createAMDGPUDisassembler); 1940 TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(), 1941 createAMDGPUSymbolizer); 1942 } 1943