1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //===----------------------------------------------------------------------===//
10 //
11 /// \file
12 ///
13 /// This file contains definition for AMDGPU ISA disassembler
14 //
15 //===----------------------------------------------------------------------===//
16 
17 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)?
18 
19 #include "Disassembler/AMDGPUDisassembler.h"
20 #include "AMDGPU.h"
21 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
22 #include "SIDefines.h"
23 #include "TargetInfo/AMDGPUTargetInfo.h"
24 #include "Utils/AMDGPUBaseInfo.h"
25 #include "llvm-c/Disassembler.h"
26 #include "llvm/ADT/APInt.h"
27 #include "llvm/ADT/ArrayRef.h"
28 #include "llvm/ADT/Twine.h"
29 #include "llvm/BinaryFormat/ELF.h"
30 #include "llvm/MC/MCAsmInfo.h"
31 #include "llvm/MC/MCContext.h"
32 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
33 #include "llvm/MC/MCExpr.h"
34 #include "llvm/MC/MCFixedLenDisassembler.h"
35 #include "llvm/MC/MCInst.h"
36 #include "llvm/MC/MCSubtargetInfo.h"
37 #include "llvm/Support/Endian.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/MathExtras.h"
40 #include "llvm/Support/TargetRegistry.h"
41 #include "llvm/Support/raw_ostream.h"
42 #include <algorithm>
43 #include <cassert>
44 #include <cstddef>
45 #include <cstdint>
46 #include <iterator>
47 #include <tuple>
48 #include <vector>
49 
50 using namespace llvm;
51 
52 #define DEBUG_TYPE "amdgpu-disassembler"
53 
54 #define SGPR_MAX (isGFX10() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \
55                             : AMDGPU::EncValues::SGPR_MAX_SI)
56 
57 using DecodeStatus = llvm::MCDisassembler::DecodeStatus;
58 
59 AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI,
60                                        MCContext &Ctx,
61                                        MCInstrInfo const *MCII) :
62   MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()),
63   TargetMaxInstBytes(Ctx.getAsmInfo()->getMaxInstLength(&STI)) {
64 
65   // ToDo: AMDGPUDisassembler supports only VI ISA.
66   if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding] && !isGFX10())
67     report_fatal_error("Disassembly not yet supported for subtarget");
68 }
69 
70 inline static MCDisassembler::DecodeStatus
71 addOperand(MCInst &Inst, const MCOperand& Opnd) {
72   Inst.addOperand(Opnd);
73   return Opnd.isValid() ?
74     MCDisassembler::Success :
75     MCDisassembler::Fail;
76 }
77 
78 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op,
79                                 uint16_t NameIdx) {
80   int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx);
81   if (OpIdx != -1) {
82     auto I = MI.begin();
83     std::advance(I, OpIdx);
84     MI.insert(I, Op);
85   }
86   return OpIdx;
87 }
88 
89 static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm,
90                                        uint64_t Addr, const void *Decoder) {
91   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
92 
93   // Our branches take a simm16, but we need two extra bits to account for the
94   // factor of 4.
95   APInt SignedOffset(18, Imm * 4, true);
96   int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue();
97 
98   if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2))
99     return MCDisassembler::Success;
100   return addOperand(Inst, MCOperand::createImm(Imm));
101 }
102 
103 static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm,
104                                      uint64_t Addr, const void *Decoder) {
105   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
106   int64_t Offset;
107   if (DAsm->isVI()) {         // VI supports 20-bit unsigned offsets.
108     Offset = Imm & 0xFFFFF;
109   } else {                    // GFX9+ supports 21-bit signed offsets.
110     Offset = SignExtend64<21>(Imm);
111   }
112   return addOperand(Inst, MCOperand::createImm(Offset));
113 }
114 
115 static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val,
116                                   uint64_t Addr, const void *Decoder) {
117   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
118   return addOperand(Inst, DAsm->decodeBoolReg(Val));
119 }
120 
121 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \
122 static DecodeStatus StaticDecoderName(MCInst &Inst, \
123                                        unsigned Imm, \
124                                        uint64_t /*Addr*/, \
125                                        const void *Decoder) { \
126   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); \
127   return addOperand(Inst, DAsm->DecoderName(Imm)); \
128 }
129 
130 #define DECODE_OPERAND_REG(RegClass) \
131 DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass)
132 
133 DECODE_OPERAND_REG(VGPR_32)
134 DECODE_OPERAND_REG(VRegOrLds_32)
135 DECODE_OPERAND_REG(VS_32)
136 DECODE_OPERAND_REG(VS_64)
137 DECODE_OPERAND_REG(VS_128)
138 
139 DECODE_OPERAND_REG(VReg_64)
140 DECODE_OPERAND_REG(VReg_96)
141 DECODE_OPERAND_REG(VReg_128)
142 
143 DECODE_OPERAND_REG(SReg_32)
144 DECODE_OPERAND_REG(SReg_32_XM0_XEXEC)
145 DECODE_OPERAND_REG(SReg_32_XEXEC_HI)
146 DECODE_OPERAND_REG(SRegOrLds_32)
147 DECODE_OPERAND_REG(SReg_64)
148 DECODE_OPERAND_REG(SReg_64_XEXEC)
149 DECODE_OPERAND_REG(SReg_128)
150 DECODE_OPERAND_REG(SReg_256)
151 DECODE_OPERAND_REG(SReg_512)
152 
153 DECODE_OPERAND_REG(AGPR_32)
154 DECODE_OPERAND_REG(AReg_128)
155 DECODE_OPERAND_REG(AReg_512)
156 DECODE_OPERAND_REG(AReg_1024)
157 DECODE_OPERAND_REG(AV_32)
158 DECODE_OPERAND_REG(AV_64)
159 
160 static DecodeStatus decodeOperand_VSrc16(MCInst &Inst,
161                                          unsigned Imm,
162                                          uint64_t Addr,
163                                          const void *Decoder) {
164   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
165   return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm));
166 }
167 
168 static DecodeStatus decodeOperand_VSrcV216(MCInst &Inst,
169                                          unsigned Imm,
170                                          uint64_t Addr,
171                                          const void *Decoder) {
172   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
173   return addOperand(Inst, DAsm->decodeOperand_VSrcV216(Imm));
174 }
175 
176 static DecodeStatus decodeOperand_VS_16(MCInst &Inst,
177                                         unsigned Imm,
178                                         uint64_t Addr,
179                                         const void *Decoder) {
180   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
181   return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm));
182 }
183 
184 static DecodeStatus decodeOperand_VS_32(MCInst &Inst,
185                                         unsigned Imm,
186                                         uint64_t Addr,
187                                         const void *Decoder) {
188   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
189   return addOperand(Inst, DAsm->decodeOperand_VS_32(Imm));
190 }
191 
192 static DecodeStatus decodeOperand_AReg_128(MCInst &Inst,
193                                            unsigned Imm,
194                                            uint64_t Addr,
195                                            const void *Decoder) {
196   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
197   return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm | 512));
198 }
199 
200 static DecodeStatus decodeOperand_AReg_512(MCInst &Inst,
201                                            unsigned Imm,
202                                            uint64_t Addr,
203                                            const void *Decoder) {
204   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
205   return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm | 512));
206 }
207 
208 static DecodeStatus decodeOperand_AReg_1024(MCInst &Inst,
209                                             unsigned Imm,
210                                             uint64_t Addr,
211                                             const void *Decoder) {
212   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
213   return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm | 512));
214 }
215 
216 static DecodeStatus decodeOperand_SReg_32(MCInst &Inst,
217                                           unsigned Imm,
218                                           uint64_t Addr,
219                                           const void *Decoder) {
220   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
221   return addOperand(Inst, DAsm->decodeOperand_SReg_32(Imm));
222 }
223 
224 static DecodeStatus decodeOperand_VGPR_32(MCInst &Inst,
225                                          unsigned Imm,
226                                          uint64_t Addr,
227                                          const void *Decoder) {
228   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
229   return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW32, Imm));
230 }
231 
232 #define DECODE_SDWA(DecName) \
233 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName)
234 
235 DECODE_SDWA(Src32)
236 DECODE_SDWA(Src16)
237 DECODE_SDWA(VopcDst)
238 
239 #include "AMDGPUGenDisassemblerTables.inc"
240 
241 //===----------------------------------------------------------------------===//
242 //
243 //===----------------------------------------------------------------------===//
244 
245 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) {
246   assert(Bytes.size() >= sizeof(T));
247   const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data());
248   Bytes = Bytes.slice(sizeof(T));
249   return Res;
250 }
251 
252 DecodeStatus AMDGPUDisassembler::tryDecodeInst(const uint8_t* Table,
253                                                MCInst &MI,
254                                                uint64_t Inst,
255                                                uint64_t Address) const {
256   assert(MI.getOpcode() == 0);
257   assert(MI.getNumOperands() == 0);
258   MCInst TmpInst;
259   HasLiteral = false;
260   const auto SavedBytes = Bytes;
261   if (decodeInstruction(Table, TmpInst, Inst, Address, this, STI)) {
262     MI = TmpInst;
263     return MCDisassembler::Success;
264   }
265   Bytes = SavedBytes;
266   return MCDisassembler::Fail;
267 }
268 
269 static bool isValidDPP8(const MCInst &MI) {
270   using namespace llvm::AMDGPU::DPP;
271   int FiIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::fi);
272   assert(FiIdx != -1);
273   if ((unsigned)FiIdx >= MI.getNumOperands())
274     return false;
275   unsigned Fi = MI.getOperand(FiIdx).getImm();
276   return Fi == DPP8_FI_0 || Fi == DPP8_FI_1;
277 }
278 
279 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
280                                                 ArrayRef<uint8_t> Bytes_,
281                                                 uint64_t Address,
282                                                 raw_ostream &CS) const {
283   CommentStream = &CS;
284   bool IsSDWA = false;
285 
286   unsigned MaxInstBytesNum = std::min((size_t)TargetMaxInstBytes, Bytes_.size());
287   Bytes = Bytes_.slice(0, MaxInstBytesNum);
288 
289   DecodeStatus Res = MCDisassembler::Fail;
290   do {
291     // ToDo: better to switch encoding length using some bit predicate
292     // but it is unknown yet, so try all we can
293 
294     // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2
295     // encodings
296     if (Bytes.size() >= 8) {
297       const uint64_t QW = eatBytes<uint64_t>(Bytes);
298 
299       Res = tryDecodeInst(DecoderTableDPP864, MI, QW, Address);
300       if (Res && convertDPP8Inst(MI) == MCDisassembler::Success)
301         break;
302 
303       MI = MCInst(); // clear
304 
305       Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address);
306       if (Res) break;
307 
308       Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address);
309       if (Res) { IsSDWA = true;  break; }
310 
311       Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address);
312       if (Res) { IsSDWA = true;  break; }
313 
314       Res = tryDecodeInst(DecoderTableSDWA1064, MI, QW, Address);
315       if (Res) { IsSDWA = true;  break; }
316 
317       if (STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem]) {
318         Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address);
319         if (Res)
320           break;
321       }
322 
323       // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and
324       // v_mad_mixhi_f16 for FMA variants. Try to decode using this special
325       // table first so we print the correct name.
326       if (STI.getFeatureBits()[AMDGPU::FeatureFmaMixInsts]) {
327         Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address);
328         if (Res)
329           break;
330       }
331     }
332 
333     // Reinitialize Bytes as DPP64 could have eaten too much
334     Bytes = Bytes_.slice(0, MaxInstBytesNum);
335 
336     // Try decode 32-bit instruction
337     if (Bytes.size() < 4) break;
338     const uint32_t DW = eatBytes<uint32_t>(Bytes);
339     Res = tryDecodeInst(DecoderTableGFX832, MI, DW, Address);
340     if (Res) break;
341 
342     Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address);
343     if (Res) break;
344 
345     Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address);
346     if (Res) break;
347 
348     Res = tryDecodeInst(DecoderTableGFX1032, MI, DW, Address);
349     if (Res) break;
350 
351     if (Bytes.size() < 4) break;
352     const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW;
353     Res = tryDecodeInst(DecoderTableGFX864, MI, QW, Address);
354     if (Res) break;
355 
356     Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address);
357     if (Res) break;
358 
359     Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address);
360     if (Res) break;
361 
362     Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address);
363   } while (false);
364 
365   if (Res && (MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi ||
366               MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx6_gfx7 ||
367               MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx10 ||
368               MI.getOpcode() == AMDGPU::V_MAC_F16_e64_vi ||
369               MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_vi ||
370               MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_gfx10 ||
371               MI.getOpcode() == AMDGPU::V_FMAC_F16_e64_gfx10)) {
372     // Insert dummy unused src2_modifiers.
373     insertNamedMCOperand(MI, MCOperand::createImm(0),
374                          AMDGPU::OpName::src2_modifiers);
375   }
376 
377   if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) {
378     int VAddr0Idx =
379         AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0);
380     int RsrcIdx =
381         AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc);
382     unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1;
383     if (VAddr0Idx >= 0 && NSAArgs > 0) {
384       unsigned NSAWords = (NSAArgs + 3) / 4;
385       if (Bytes.size() < 4 * NSAWords) {
386         Res = MCDisassembler::Fail;
387       } else {
388         for (unsigned i = 0; i < NSAArgs; ++i) {
389           MI.insert(MI.begin() + VAddr0Idx + 1 + i,
390                     decodeOperand_VGPR_32(Bytes[i]));
391         }
392         Bytes = Bytes.slice(4 * NSAWords);
393       }
394     }
395 
396     if (Res)
397       Res = convertMIMGInst(MI);
398   }
399 
400   if (Res && IsSDWA)
401     Res = convertSDWAInst(MI);
402 
403   int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
404                                               AMDGPU::OpName::vdst_in);
405   if (VDstIn_Idx != -1) {
406     int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx,
407                            MCOI::OperandConstraint::TIED_TO);
408     if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx ||
409          !MI.getOperand(VDstIn_Idx).isReg() ||
410          MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) {
411       if (MI.getNumOperands() > (unsigned)VDstIn_Idx)
412         MI.erase(&MI.getOperand(VDstIn_Idx));
413       insertNamedMCOperand(MI,
414         MCOperand::createReg(MI.getOperand(Tied).getReg()),
415         AMDGPU::OpName::vdst_in);
416     }
417   }
418 
419   // if the opcode was not recognized we'll assume a Size of 4 bytes
420   // (unless there are fewer bytes left)
421   Size = Res ? (MaxInstBytesNum - Bytes.size())
422              : std::min((size_t)4, Bytes_.size());
423   return Res;
424 }
425 
426 DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const {
427   if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] ||
428       STI.getFeatureBits()[AMDGPU::FeatureGFX10]) {
429     if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst) != -1)
430       // VOPC - insert clamp
431       insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp);
432   } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) {
433     int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst);
434     if (SDst != -1) {
435       // VOPC - insert VCC register as sdst
436       insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC),
437                            AMDGPU::OpName::sdst);
438     } else {
439       // VOP1/2 - insert omod if present in instruction
440       insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod);
441     }
442   }
443   return MCDisassembler::Success;
444 }
445 
446 DecodeStatus AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const {
447   unsigned Opc = MI.getOpcode();
448   unsigned DescNumOps = MCII->get(Opc).getNumOperands();
449 
450   // Insert dummy unused src modifiers.
451   if (MI.getNumOperands() < DescNumOps &&
452       AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1)
453     insertNamedMCOperand(MI, MCOperand::createImm(0),
454                          AMDGPU::OpName::src0_modifiers);
455 
456   if (MI.getNumOperands() < DescNumOps &&
457       AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers) != -1)
458     insertNamedMCOperand(MI, MCOperand::createImm(0),
459                          AMDGPU::OpName::src1_modifiers);
460 
461   return isValidDPP8(MI) ? MCDisassembler::Success : MCDisassembler::SoftFail;
462 }
463 
464 // Note that before gfx10, the MIMG encoding provided no information about
465 // VADDR size. Consequently, decoded instructions always show address as if it
466 // has 1 dword, which could be not really so.
467 DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const {
468 
469   int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
470                                            AMDGPU::OpName::vdst);
471 
472   int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
473                                             AMDGPU::OpName::vdata);
474   int VAddr0Idx =
475       AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0);
476   int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
477                                             AMDGPU::OpName::dmask);
478 
479   int TFEIdx   = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
480                                             AMDGPU::OpName::tfe);
481   int D16Idx   = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
482                                             AMDGPU::OpName::d16);
483 
484   assert(VDataIdx != -1);
485   assert(DMaskIdx != -1);
486   assert(TFEIdx != -1);
487 
488   const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode());
489   bool IsAtomic = (VDstIdx != -1);
490   bool IsGather4 = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::Gather4;
491 
492   bool IsNSA = false;
493   unsigned AddrSize = Info->VAddrDwords;
494 
495   if (STI.getFeatureBits()[AMDGPU::FeatureGFX10]) {
496     unsigned DimIdx =
497         AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim);
498     const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode =
499         AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode);
500     const AMDGPU::MIMGDimInfo *Dim =
501         AMDGPU::getMIMGDimInfoByEncoding(MI.getOperand(DimIdx).getImm());
502 
503     AddrSize = BaseOpcode->NumExtraArgs +
504                (BaseOpcode->Gradients ? Dim->NumGradients : 0) +
505                (BaseOpcode->Coordinates ? Dim->NumCoords : 0) +
506                (BaseOpcode->LodOrClampOrMip ? 1 : 0);
507     IsNSA = Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA;
508     if (!IsNSA) {
509       if (AddrSize > 8)
510         AddrSize = 16;
511       else if (AddrSize > 4)
512         AddrSize = 8;
513     } else {
514       if (AddrSize > Info->VAddrDwords) {
515         // The NSA encoding does not contain enough operands for the combination
516         // of base opcode / dimension. Should this be an error?
517         return MCDisassembler::Success;
518       }
519     }
520   }
521 
522   unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf;
523   unsigned DstSize = IsGather4 ? 4 : std::max(countPopulation(DMask), 1u);
524 
525   bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm();
526   if (D16 && AMDGPU::hasPackedD16(STI)) {
527     DstSize = (DstSize + 1) / 2;
528   }
529 
530   // FIXME: Add tfe support
531   if (MI.getOperand(TFEIdx).getImm())
532     return MCDisassembler::Success;
533 
534   if (DstSize == Info->VDataDwords && AddrSize == Info->VAddrDwords)
535     return MCDisassembler::Success;
536 
537   int NewOpcode =
538       AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize);
539   if (NewOpcode == -1)
540     return MCDisassembler::Success;
541 
542   // Widen the register to the correct number of enabled channels.
543   unsigned NewVdata = AMDGPU::NoRegister;
544   if (DstSize != Info->VDataDwords) {
545     auto DataRCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass;
546 
547     // Get first subregister of VData
548     unsigned Vdata0 = MI.getOperand(VDataIdx).getReg();
549     unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0);
550     Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0;
551 
552     NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0,
553                                        &MRI.getRegClass(DataRCID));
554     if (NewVdata == AMDGPU::NoRegister) {
555       // It's possible to encode this such that the low register + enabled
556       // components exceeds the register count.
557       return MCDisassembler::Success;
558     }
559   }
560 
561   unsigned NewVAddr0 = AMDGPU::NoRegister;
562   if (STI.getFeatureBits()[AMDGPU::FeatureGFX10] && !IsNSA &&
563       AddrSize != Info->VAddrDwords) {
564     unsigned VAddr0 = MI.getOperand(VAddr0Idx).getReg();
565     unsigned VAddrSub0 = MRI.getSubReg(VAddr0, AMDGPU::sub0);
566     VAddr0 = (VAddrSub0 != 0) ? VAddrSub0 : VAddr0;
567 
568     auto AddrRCID = MCII->get(NewOpcode).OpInfo[VAddr0Idx].RegClass;
569     NewVAddr0 = MRI.getMatchingSuperReg(VAddr0, AMDGPU::sub0,
570                                         &MRI.getRegClass(AddrRCID));
571     if (NewVAddr0 == AMDGPU::NoRegister)
572       return MCDisassembler::Success;
573   }
574 
575   MI.setOpcode(NewOpcode);
576 
577   if (NewVdata != AMDGPU::NoRegister) {
578     MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata);
579 
580     if (IsAtomic) {
581       // Atomic operations have an additional operand (a copy of data)
582       MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata);
583     }
584   }
585 
586   if (NewVAddr0 != AMDGPU::NoRegister) {
587     MI.getOperand(VAddr0Idx) = MCOperand::createReg(NewVAddr0);
588   } else if (IsNSA) {
589     assert(AddrSize <= Info->VAddrDwords);
590     MI.erase(MI.begin() + VAddr0Idx + AddrSize,
591              MI.begin() + VAddr0Idx + Info->VAddrDwords);
592   }
593 
594   return MCDisassembler::Success;
595 }
596 
597 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const {
598   return getContext().getRegisterInfo()->
599     getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]);
600 }
601 
602 inline
603 MCOperand AMDGPUDisassembler::errOperand(unsigned V,
604                                          const Twine& ErrMsg) const {
605   *CommentStream << "Error: " + ErrMsg;
606 
607   // ToDo: add support for error operands to MCInst.h
608   // return MCOperand::createError(V);
609   return MCOperand();
610 }
611 
612 inline
613 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const {
614   return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI));
615 }
616 
617 inline
618 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID,
619                                                unsigned Val) const {
620   const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID];
621   if (Val >= RegCl.getNumRegs())
622     return errOperand(Val, Twine(getRegClassName(RegClassID)) +
623                            ": unknown register " + Twine(Val));
624   return createRegOperand(RegCl.getRegister(Val));
625 }
626 
627 inline
628 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID,
629                                                 unsigned Val) const {
630   // ToDo: SI/CI have 104 SGPRs, VI - 102
631   // Valery: here we accepting as much as we can, let assembler sort it out
632   int shift = 0;
633   switch (SRegClassID) {
634   case AMDGPU::SGPR_32RegClassID:
635   case AMDGPU::TTMP_32RegClassID:
636     break;
637   case AMDGPU::SGPR_64RegClassID:
638   case AMDGPU::TTMP_64RegClassID:
639     shift = 1;
640     break;
641   case AMDGPU::SGPR_128RegClassID:
642   case AMDGPU::TTMP_128RegClassID:
643   // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in
644   // this bundle?
645   case AMDGPU::SGPR_256RegClassID:
646   case AMDGPU::TTMP_256RegClassID:
647     // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in
648   // this bundle?
649   case AMDGPU::SGPR_512RegClassID:
650   case AMDGPU::TTMP_512RegClassID:
651     shift = 2;
652     break;
653   // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in
654   // this bundle?
655   default:
656     llvm_unreachable("unhandled register class");
657   }
658 
659   if (Val % (1 << shift)) {
660     *CommentStream << "Warning: " << getRegClassName(SRegClassID)
661                    << ": scalar reg isn't aligned " << Val;
662   }
663 
664   return createRegOperand(SRegClassID, Val >> shift);
665 }
666 
667 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const {
668   return decodeSrcOp(OPW32, Val);
669 }
670 
671 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const {
672   return decodeSrcOp(OPW64, Val);
673 }
674 
675 MCOperand AMDGPUDisassembler::decodeOperand_VS_128(unsigned Val) const {
676   return decodeSrcOp(OPW128, Val);
677 }
678 
679 MCOperand AMDGPUDisassembler::decodeOperand_VSrc16(unsigned Val) const {
680   return decodeSrcOp(OPW16, Val);
681 }
682 
683 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV216(unsigned Val) const {
684   return decodeSrcOp(OPWV216, Val);
685 }
686 
687 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const {
688   // Some instructions have operand restrictions beyond what the encoding
689   // allows. Some ordinarily VSrc_32 operands are VGPR_32, so clear the extra
690   // high bit.
691   Val &= 255;
692 
693   return createRegOperand(AMDGPU::VGPR_32RegClassID, Val);
694 }
695 
696 MCOperand AMDGPUDisassembler::decodeOperand_VRegOrLds_32(unsigned Val) const {
697   return decodeSrcOp(OPW32, Val);
698 }
699 
700 MCOperand AMDGPUDisassembler::decodeOperand_AGPR_32(unsigned Val) const {
701   return createRegOperand(AMDGPU::AGPR_32RegClassID, Val & 255);
702 }
703 
704 MCOperand AMDGPUDisassembler::decodeOperand_AReg_128(unsigned Val) const {
705   return createRegOperand(AMDGPU::AReg_128RegClassID, Val & 255);
706 }
707 
708 MCOperand AMDGPUDisassembler::decodeOperand_AReg_512(unsigned Val) const {
709   return createRegOperand(AMDGPU::AReg_512RegClassID, Val & 255);
710 }
711 
712 MCOperand AMDGPUDisassembler::decodeOperand_AReg_1024(unsigned Val) const {
713   return createRegOperand(AMDGPU::AReg_1024RegClassID, Val & 255);
714 }
715 
716 MCOperand AMDGPUDisassembler::decodeOperand_AV_32(unsigned Val) const {
717   return decodeSrcOp(OPW32, Val);
718 }
719 
720 MCOperand AMDGPUDisassembler::decodeOperand_AV_64(unsigned Val) const {
721   return decodeSrcOp(OPW64, Val);
722 }
723 
724 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const {
725   return createRegOperand(AMDGPU::VReg_64RegClassID, Val);
726 }
727 
728 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const {
729   return createRegOperand(AMDGPU::VReg_96RegClassID, Val);
730 }
731 
732 MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const {
733   return createRegOperand(AMDGPU::VReg_128RegClassID, Val);
734 }
735 
736 MCOperand AMDGPUDisassembler::decodeOperand_VReg_256(unsigned Val) const {
737   return createRegOperand(AMDGPU::VReg_256RegClassID, Val);
738 }
739 
740 MCOperand AMDGPUDisassembler::decodeOperand_VReg_512(unsigned Val) const {
741   return createRegOperand(AMDGPU::VReg_512RegClassID, Val);
742 }
743 
744 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const {
745   // table-gen generated disassembler doesn't care about operand types
746   // leaving only registry class so SSrc_32 operand turns into SReg_32
747   // and therefore we accept immediates and literals here as well
748   return decodeSrcOp(OPW32, Val);
749 }
750 
751 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0_XEXEC(
752   unsigned Val) const {
753   // SReg_32_XM0 is SReg_32 without M0 or EXEC_LO/EXEC_HI
754   return decodeOperand_SReg_32(Val);
755 }
756 
757 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XEXEC_HI(
758   unsigned Val) const {
759   // SReg_32_XM0 is SReg_32 without EXEC_HI
760   return decodeOperand_SReg_32(Val);
761 }
762 
763 MCOperand AMDGPUDisassembler::decodeOperand_SRegOrLds_32(unsigned Val) const {
764   // table-gen generated disassembler doesn't care about operand types
765   // leaving only registry class so SSrc_32 operand turns into SReg_32
766   // and therefore we accept immediates and literals here as well
767   return decodeSrcOp(OPW32, Val);
768 }
769 
770 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const {
771   return decodeSrcOp(OPW64, Val);
772 }
773 
774 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64_XEXEC(unsigned Val) const {
775   return decodeSrcOp(OPW64, Val);
776 }
777 
778 MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const {
779   return decodeSrcOp(OPW128, Val);
780 }
781 
782 MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const {
783   return decodeDstOp(OPW256, Val);
784 }
785 
786 MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const {
787   return decodeDstOp(OPW512, Val);
788 }
789 
790 MCOperand AMDGPUDisassembler::decodeLiteralConstant() const {
791   // For now all literal constants are supposed to be unsigned integer
792   // ToDo: deal with signed/unsigned 64-bit integer constants
793   // ToDo: deal with float/double constants
794   if (!HasLiteral) {
795     if (Bytes.size() < 4) {
796       return errOperand(0, "cannot read literal, inst bytes left " +
797                         Twine(Bytes.size()));
798     }
799     HasLiteral = true;
800     Literal = eatBytes<uint32_t>(Bytes);
801   }
802   return MCOperand::createImm(Literal);
803 }
804 
805 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) {
806   using namespace AMDGPU::EncValues;
807 
808   assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX);
809   return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ?
810     (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) :
811     (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm)));
812       // Cast prevents negative overflow.
813 }
814 
815 static int64_t getInlineImmVal32(unsigned Imm) {
816   switch (Imm) {
817   case 240:
818     return FloatToBits(0.5f);
819   case 241:
820     return FloatToBits(-0.5f);
821   case 242:
822     return FloatToBits(1.0f);
823   case 243:
824     return FloatToBits(-1.0f);
825   case 244:
826     return FloatToBits(2.0f);
827   case 245:
828     return FloatToBits(-2.0f);
829   case 246:
830     return FloatToBits(4.0f);
831   case 247:
832     return FloatToBits(-4.0f);
833   case 248: // 1 / (2 * PI)
834     return 0x3e22f983;
835   default:
836     llvm_unreachable("invalid fp inline imm");
837   }
838 }
839 
840 static int64_t getInlineImmVal64(unsigned Imm) {
841   switch (Imm) {
842   case 240:
843     return DoubleToBits(0.5);
844   case 241:
845     return DoubleToBits(-0.5);
846   case 242:
847     return DoubleToBits(1.0);
848   case 243:
849     return DoubleToBits(-1.0);
850   case 244:
851     return DoubleToBits(2.0);
852   case 245:
853     return DoubleToBits(-2.0);
854   case 246:
855     return DoubleToBits(4.0);
856   case 247:
857     return DoubleToBits(-4.0);
858   case 248: // 1 / (2 * PI)
859     return 0x3fc45f306dc9c882;
860   default:
861     llvm_unreachable("invalid fp inline imm");
862   }
863 }
864 
865 static int64_t getInlineImmVal16(unsigned Imm) {
866   switch (Imm) {
867   case 240:
868     return 0x3800;
869   case 241:
870     return 0xB800;
871   case 242:
872     return 0x3C00;
873   case 243:
874     return 0xBC00;
875   case 244:
876     return 0x4000;
877   case 245:
878     return 0xC000;
879   case 246:
880     return 0x4400;
881   case 247:
882     return 0xC400;
883   case 248: // 1 / (2 * PI)
884     return 0x3118;
885   default:
886     llvm_unreachable("invalid fp inline imm");
887   }
888 }
889 
890 MCOperand AMDGPUDisassembler::decodeFPImmed(OpWidthTy Width, unsigned Imm) {
891   assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN
892       && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX);
893 
894   // ToDo: case 248: 1/(2*PI) - is allowed only on VI
895   switch (Width) {
896   case OPW32:
897   case OPW128: // splat constants
898   case OPW512:
899   case OPW1024:
900     return MCOperand::createImm(getInlineImmVal32(Imm));
901   case OPW64:
902     return MCOperand::createImm(getInlineImmVal64(Imm));
903   case OPW16:
904   case OPWV216:
905     return MCOperand::createImm(getInlineImmVal16(Imm));
906   default:
907     llvm_unreachable("implement me");
908   }
909 }
910 
911 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const {
912   using namespace AMDGPU;
913 
914   assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
915   switch (Width) {
916   default: // fall
917   case OPW32:
918   case OPW16:
919   case OPWV216:
920     return VGPR_32RegClassID;
921   case OPW64: return VReg_64RegClassID;
922   case OPW128: return VReg_128RegClassID;
923   }
924 }
925 
926 unsigned AMDGPUDisassembler::getAgprClassId(const OpWidthTy Width) const {
927   using namespace AMDGPU;
928 
929   assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
930   switch (Width) {
931   default: // fall
932   case OPW32:
933   case OPW16:
934   case OPWV216:
935     return AGPR_32RegClassID;
936   case OPW64: return AReg_64RegClassID;
937   case OPW128: return AReg_128RegClassID;
938   case OPW256: return AReg_256RegClassID;
939   case OPW512: return AReg_512RegClassID;
940   case OPW1024: return AReg_1024RegClassID;
941   }
942 }
943 
944 
945 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const {
946   using namespace AMDGPU;
947 
948   assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
949   switch (Width) {
950   default: // fall
951   case OPW32:
952   case OPW16:
953   case OPWV216:
954     return SGPR_32RegClassID;
955   case OPW64: return SGPR_64RegClassID;
956   case OPW128: return SGPR_128RegClassID;
957   case OPW256: return SGPR_256RegClassID;
958   case OPW512: return SGPR_512RegClassID;
959   }
960 }
961 
962 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const {
963   using namespace AMDGPU;
964 
965   assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
966   switch (Width) {
967   default: // fall
968   case OPW32:
969   case OPW16:
970   case OPWV216:
971     return TTMP_32RegClassID;
972   case OPW64: return TTMP_64RegClassID;
973   case OPW128: return TTMP_128RegClassID;
974   case OPW256: return TTMP_256RegClassID;
975   case OPW512: return TTMP_512RegClassID;
976   }
977 }
978 
979 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const {
980   using namespace AMDGPU::EncValues;
981 
982   unsigned TTmpMin =
983       (isGFX9() || isGFX10()) ? TTMP_GFX9_GFX10_MIN : TTMP_VI_MIN;
984   unsigned TTmpMax =
985       (isGFX9() || isGFX10()) ? TTMP_GFX9_GFX10_MAX : TTMP_VI_MAX;
986 
987   return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1;
988 }
989 
990 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val) const {
991   using namespace AMDGPU::EncValues;
992 
993   assert(Val < 1024); // enum10
994 
995   bool IsAGPR = Val & 512;
996   Val &= 511;
997 
998   if (VGPR_MIN <= Val && Val <= VGPR_MAX) {
999     return createRegOperand(IsAGPR ? getAgprClassId(Width)
1000                                    : getVgprClassId(Width), Val - VGPR_MIN);
1001   }
1002   if (Val <= SGPR_MAX) {
1003     assert(SGPR_MIN == 0); // "SGPR_MIN <= Val" is always true and causes compilation warning.
1004     return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN);
1005   }
1006 
1007   int TTmpIdx = getTTmpIdx(Val);
1008   if (TTmpIdx >= 0) {
1009     return createSRegOperand(getTtmpClassId(Width), TTmpIdx);
1010   }
1011 
1012   if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX)
1013     return decodeIntImmed(Val);
1014 
1015   if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX)
1016     return decodeFPImmed(Width, Val);
1017 
1018   if (Val == LITERAL_CONST)
1019     return decodeLiteralConstant();
1020 
1021   switch (Width) {
1022   case OPW32:
1023   case OPW16:
1024   case OPWV216:
1025     return decodeSpecialReg32(Val);
1026   case OPW64:
1027     return decodeSpecialReg64(Val);
1028   default:
1029     llvm_unreachable("unexpected immediate type");
1030   }
1031 }
1032 
1033 MCOperand AMDGPUDisassembler::decodeDstOp(const OpWidthTy Width, unsigned Val) const {
1034   using namespace AMDGPU::EncValues;
1035 
1036   assert(Val < 128);
1037   assert(Width == OPW256 || Width == OPW512);
1038 
1039   if (Val <= SGPR_MAX) {
1040     assert(SGPR_MIN == 0); // "SGPR_MIN <= Val" is always true and causes compilation warning.
1041     return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN);
1042   }
1043 
1044   int TTmpIdx = getTTmpIdx(Val);
1045   if (TTmpIdx >= 0) {
1046     return createSRegOperand(getTtmpClassId(Width), TTmpIdx);
1047   }
1048 
1049   llvm_unreachable("unknown dst register");
1050 }
1051 
1052 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const {
1053   using namespace AMDGPU;
1054 
1055   switch (Val) {
1056   case 102: return createRegOperand(FLAT_SCR_LO);
1057   case 103: return createRegOperand(FLAT_SCR_HI);
1058   case 104: return createRegOperand(XNACK_MASK_LO);
1059   case 105: return createRegOperand(XNACK_MASK_HI);
1060   case 106: return createRegOperand(VCC_LO);
1061   case 107: return createRegOperand(VCC_HI);
1062   case 108: return createRegOperand(TBA_LO);
1063   case 109: return createRegOperand(TBA_HI);
1064   case 110: return createRegOperand(TMA_LO);
1065   case 111: return createRegOperand(TMA_HI);
1066   case 124: return createRegOperand(M0);
1067   case 125: return createRegOperand(SGPR_NULL);
1068   case 126: return createRegOperand(EXEC_LO);
1069   case 127: return createRegOperand(EXEC_HI);
1070   case 235: return createRegOperand(SRC_SHARED_BASE);
1071   case 236: return createRegOperand(SRC_SHARED_LIMIT);
1072   case 237: return createRegOperand(SRC_PRIVATE_BASE);
1073   case 238: return createRegOperand(SRC_PRIVATE_LIMIT);
1074   case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID);
1075   case 251: return createRegOperand(SRC_VCCZ);
1076   case 252: return createRegOperand(SRC_EXECZ);
1077   case 253: return createRegOperand(SRC_SCC);
1078   case 254: return createRegOperand(LDS_DIRECT);
1079   default: break;
1080   }
1081   return errOperand(Val, "unknown operand encoding " + Twine(Val));
1082 }
1083 
1084 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const {
1085   using namespace AMDGPU;
1086 
1087   switch (Val) {
1088   case 102: return createRegOperand(FLAT_SCR);
1089   case 104: return createRegOperand(XNACK_MASK);
1090   case 106: return createRegOperand(VCC);
1091   case 108: return createRegOperand(TBA);
1092   case 110: return createRegOperand(TMA);
1093   case 125: return createRegOperand(SGPR_NULL);
1094   case 126: return createRegOperand(EXEC);
1095   case 235: return createRegOperand(SRC_SHARED_BASE);
1096   case 236: return createRegOperand(SRC_SHARED_LIMIT);
1097   case 237: return createRegOperand(SRC_PRIVATE_BASE);
1098   case 238: return createRegOperand(SRC_PRIVATE_LIMIT);
1099   case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID);
1100   case 251: return createRegOperand(SRC_VCCZ);
1101   case 252: return createRegOperand(SRC_EXECZ);
1102   case 253: return createRegOperand(SRC_SCC);
1103   default: break;
1104   }
1105   return errOperand(Val, "unknown operand encoding " + Twine(Val));
1106 }
1107 
1108 MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width,
1109                                             const unsigned Val) const {
1110   using namespace AMDGPU::SDWA;
1111   using namespace AMDGPU::EncValues;
1112 
1113   if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] ||
1114       STI.getFeatureBits()[AMDGPU::FeatureGFX10]) {
1115     // XXX: cast to int is needed to avoid stupid warning:
1116     // compare with unsigned is always true
1117     if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) &&
1118         Val <= SDWA9EncValues::SRC_VGPR_MAX) {
1119       return createRegOperand(getVgprClassId(Width),
1120                               Val - SDWA9EncValues::SRC_VGPR_MIN);
1121     }
1122     if (SDWA9EncValues::SRC_SGPR_MIN <= Val &&
1123         Val <= (isGFX10() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10
1124                           : SDWA9EncValues::SRC_SGPR_MAX_SI)) {
1125       return createSRegOperand(getSgprClassId(Width),
1126                                Val - SDWA9EncValues::SRC_SGPR_MIN);
1127     }
1128     if (SDWA9EncValues::SRC_TTMP_MIN <= Val &&
1129         Val <= SDWA9EncValues::SRC_TTMP_MAX) {
1130       return createSRegOperand(getTtmpClassId(Width),
1131                                Val - SDWA9EncValues::SRC_TTMP_MIN);
1132     }
1133 
1134     const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN;
1135 
1136     if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX)
1137       return decodeIntImmed(SVal);
1138 
1139     if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX)
1140       return decodeFPImmed(Width, SVal);
1141 
1142     return decodeSpecialReg32(SVal);
1143   } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) {
1144     return createRegOperand(getVgprClassId(Width), Val);
1145   }
1146   llvm_unreachable("unsupported target");
1147 }
1148 
1149 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const {
1150   return decodeSDWASrc(OPW16, Val);
1151 }
1152 
1153 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const {
1154   return decodeSDWASrc(OPW32, Val);
1155 }
1156 
1157 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const {
1158   using namespace AMDGPU::SDWA;
1159 
1160   assert((STI.getFeatureBits()[AMDGPU::FeatureGFX9] ||
1161           STI.getFeatureBits()[AMDGPU::FeatureGFX10]) &&
1162          "SDWAVopcDst should be present only on GFX9+");
1163 
1164   bool IsWave64 = STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64];
1165 
1166   if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) {
1167     Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK;
1168 
1169     int TTmpIdx = getTTmpIdx(Val);
1170     if (TTmpIdx >= 0) {
1171       auto TTmpClsId = getTtmpClassId(IsWave64 ? OPW64 : OPW32);
1172       return createSRegOperand(TTmpClsId, TTmpIdx);
1173     } else if (Val > SGPR_MAX) {
1174       return IsWave64 ? decodeSpecialReg64(Val)
1175                       : decodeSpecialReg32(Val);
1176     } else {
1177       return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val);
1178     }
1179   } else {
1180     return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO);
1181   }
1182 }
1183 
1184 MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const {
1185   return STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ?
1186     decodeOperand_SReg_64(Val) : decodeOperand_SReg_32(Val);
1187 }
1188 
1189 bool AMDGPUDisassembler::isVI() const {
1190   return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands];
1191 }
1192 
1193 bool AMDGPUDisassembler::isGFX9() const {
1194   return STI.getFeatureBits()[AMDGPU::FeatureGFX9];
1195 }
1196 
1197 bool AMDGPUDisassembler::isGFX10() const {
1198   return STI.getFeatureBits()[AMDGPU::FeatureGFX10];
1199 }
1200 
1201 //===----------------------------------------------------------------------===//
1202 // AMDGPUSymbolizer
1203 //===----------------------------------------------------------------------===//
1204 
1205 // Try to find symbol name for specified label
1206 bool AMDGPUSymbolizer::tryAddingSymbolicOperand(MCInst &Inst,
1207                                 raw_ostream &/*cStream*/, int64_t Value,
1208                                 uint64_t /*Address*/, bool IsBranch,
1209                                 uint64_t /*Offset*/, uint64_t /*InstSize*/) {
1210 
1211   if (!IsBranch) {
1212     return false;
1213   }
1214 
1215   auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo);
1216   if (!Symbols)
1217     return false;
1218 
1219   auto Result = std::find_if(Symbols->begin(), Symbols->end(),
1220                              [Value](const SymbolInfoTy& Val) {
1221                                 return Val.Addr == static_cast<uint64_t>(Value)
1222                                     && Val.Type == ELF::STT_NOTYPE;
1223                              });
1224   if (Result != Symbols->end()) {
1225     auto *Sym = Ctx.getOrCreateSymbol(Result->Name);
1226     const auto *Add = MCSymbolRefExpr::create(Sym, Ctx);
1227     Inst.addOperand(MCOperand::createExpr(Add));
1228     return true;
1229   }
1230   return false;
1231 }
1232 
1233 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream,
1234                                                        int64_t Value,
1235                                                        uint64_t Address) {
1236   llvm_unreachable("unimplemented");
1237 }
1238 
1239 //===----------------------------------------------------------------------===//
1240 // Initialization
1241 //===----------------------------------------------------------------------===//
1242 
1243 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/,
1244                               LLVMOpInfoCallback /*GetOpInfo*/,
1245                               LLVMSymbolLookupCallback /*SymbolLookUp*/,
1246                               void *DisInfo,
1247                               MCContext *Ctx,
1248                               std::unique_ptr<MCRelocationInfo> &&RelInfo) {
1249   return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo);
1250 }
1251 
1252 static MCDisassembler *createAMDGPUDisassembler(const Target &T,
1253                                                 const MCSubtargetInfo &STI,
1254                                                 MCContext &Ctx) {
1255   return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo());
1256 }
1257 
1258 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler() {
1259   TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(),
1260                                          createAMDGPUDisassembler);
1261   TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(),
1262                                        createAMDGPUSymbolizer);
1263 }
1264