1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 //===----------------------------------------------------------------------===// 10 // 11 /// \file 12 /// 13 /// This file contains definition for AMDGPU ISA disassembler 14 // 15 //===----------------------------------------------------------------------===// 16 17 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)? 18 19 #include "Disassembler/AMDGPUDisassembler.h" 20 #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 21 #include "TargetInfo/AMDGPUTargetInfo.h" 22 #include "Utils/AMDGPUBaseInfo.h" 23 #include "llvm-c/DisassemblerTypes.h" 24 #include "llvm/BinaryFormat/ELF.h" 25 #include "llvm/MC/MCAsmInfo.h" 26 #include "llvm/MC/MCContext.h" 27 #include "llvm/MC/MCExpr.h" 28 #include "llvm/MC/MCFixedLenDisassembler.h" 29 #include "llvm/MC/MCInstrDesc.h" 30 #include "llvm/MC/MCRegisterInfo.h" 31 #include "llvm/MC/MCSubtargetInfo.h" 32 #include "llvm/MC/TargetRegistry.h" 33 #include "llvm/Support/AMDHSAKernelDescriptor.h" 34 35 using namespace llvm; 36 37 #define DEBUG_TYPE "amdgpu-disassembler" 38 39 #define SGPR_MAX \ 40 (isGFX10Plus() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \ 41 : AMDGPU::EncValues::SGPR_MAX_SI) 42 43 using DecodeStatus = llvm::MCDisassembler::DecodeStatus; 44 45 AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI, 46 MCContext &Ctx, 47 MCInstrInfo const *MCII) : 48 MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()), 49 TargetMaxInstBytes(Ctx.getAsmInfo()->getMaxInstLength(&STI)) { 50 51 // ToDo: AMDGPUDisassembler supports only VI ISA. 52 if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding] && !isGFX10Plus()) 53 report_fatal_error("Disassembly not yet supported for subtarget"); 54 } 55 56 inline static MCDisassembler::DecodeStatus 57 addOperand(MCInst &Inst, const MCOperand& Opnd) { 58 Inst.addOperand(Opnd); 59 return Opnd.isValid() ? 60 MCDisassembler::Success : 61 MCDisassembler::Fail; 62 } 63 64 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, 65 uint16_t NameIdx) { 66 int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx); 67 if (OpIdx != -1) { 68 auto I = MI.begin(); 69 std::advance(I, OpIdx); 70 MI.insert(I, Op); 71 } 72 return OpIdx; 73 } 74 75 static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm, 76 uint64_t Addr, 77 const MCDisassembler *Decoder) { 78 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 79 80 // Our branches take a simm16, but we need two extra bits to account for the 81 // factor of 4. 82 APInt SignedOffset(18, Imm * 4, true); 83 int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue(); 84 85 if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2)) 86 return MCDisassembler::Success; 87 return addOperand(Inst, MCOperand::createImm(Imm)); 88 } 89 90 static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, uint64_t Addr, 91 const MCDisassembler *Decoder) { 92 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 93 int64_t Offset; 94 if (DAsm->isVI()) { // VI supports 20-bit unsigned offsets. 95 Offset = Imm & 0xFFFFF; 96 } else { // GFX9+ supports 21-bit signed offsets. 97 Offset = SignExtend64<21>(Imm); 98 } 99 return addOperand(Inst, MCOperand::createImm(Offset)); 100 } 101 102 static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, uint64_t Addr, 103 const MCDisassembler *Decoder) { 104 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 105 return addOperand(Inst, DAsm->decodeBoolReg(Val)); 106 } 107 108 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \ 109 static DecodeStatus StaticDecoderName(MCInst &Inst, unsigned Imm, \ 110 uint64_t /*Addr*/, \ 111 const MCDisassembler *Decoder) { \ 112 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 113 return addOperand(Inst, DAsm->DecoderName(Imm)); \ 114 } 115 116 #define DECODE_OPERAND_REG(RegClass) \ 117 DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass) 118 119 DECODE_OPERAND_REG(VGPR_32) 120 DECODE_OPERAND_REG(VRegOrLds_32) 121 DECODE_OPERAND_REG(VS_32) 122 DECODE_OPERAND_REG(VS_64) 123 DECODE_OPERAND_REG(VS_128) 124 125 DECODE_OPERAND_REG(VReg_64) 126 DECODE_OPERAND_REG(VReg_96) 127 DECODE_OPERAND_REG(VReg_128) 128 DECODE_OPERAND_REG(VReg_256) 129 DECODE_OPERAND_REG(VReg_512) 130 DECODE_OPERAND_REG(VReg_1024) 131 132 DECODE_OPERAND_REG(SReg_32) 133 DECODE_OPERAND_REG(SReg_32_XM0_XEXEC) 134 DECODE_OPERAND_REG(SReg_32_XEXEC_HI) 135 DECODE_OPERAND_REG(SRegOrLds_32) 136 DECODE_OPERAND_REG(SReg_64) 137 DECODE_OPERAND_REG(SReg_64_XEXEC) 138 DECODE_OPERAND_REG(SReg_128) 139 DECODE_OPERAND_REG(SReg_256) 140 DECODE_OPERAND_REG(SReg_512) 141 142 DECODE_OPERAND_REG(AGPR_32) 143 DECODE_OPERAND_REG(AReg_64) 144 DECODE_OPERAND_REG(AReg_128) 145 DECODE_OPERAND_REG(AReg_256) 146 DECODE_OPERAND_REG(AReg_512) 147 DECODE_OPERAND_REG(AReg_1024) 148 DECODE_OPERAND_REG(AV_32) 149 DECODE_OPERAND_REG(AV_64) 150 DECODE_OPERAND_REG(AV_128) 151 DECODE_OPERAND_REG(AV_512) 152 153 static DecodeStatus decodeOperand_VSrc16(MCInst &Inst, unsigned Imm, 154 uint64_t Addr, 155 const MCDisassembler *Decoder) { 156 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 157 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); 158 } 159 160 static DecodeStatus decodeOperand_VSrcV216(MCInst &Inst, unsigned Imm, 161 uint64_t Addr, 162 const MCDisassembler *Decoder) { 163 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 164 return addOperand(Inst, DAsm->decodeOperand_VSrcV216(Imm)); 165 } 166 167 static DecodeStatus decodeOperand_VSrcV232(MCInst &Inst, unsigned Imm, 168 uint64_t Addr, 169 const MCDisassembler *Decoder) { 170 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 171 return addOperand(Inst, DAsm->decodeOperand_VSrcV232(Imm)); 172 } 173 174 static DecodeStatus decodeOperand_VS_16(MCInst &Inst, unsigned Imm, 175 uint64_t Addr, 176 const MCDisassembler *Decoder) { 177 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 178 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); 179 } 180 181 static DecodeStatus decodeOperand_VS_32(MCInst &Inst, unsigned Imm, 182 uint64_t Addr, 183 const MCDisassembler *Decoder) { 184 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 185 return addOperand(Inst, DAsm->decodeOperand_VS_32(Imm)); 186 } 187 188 static DecodeStatus decodeOperand_AReg_64(MCInst &Inst, unsigned Imm, 189 uint64_t Addr, 190 const MCDisassembler *Decoder) { 191 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 192 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm | 512)); 193 } 194 195 static DecodeStatus decodeOperand_AReg_128(MCInst &Inst, unsigned Imm, 196 uint64_t Addr, 197 const MCDisassembler *Decoder) { 198 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 199 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm | 512)); 200 } 201 202 static DecodeStatus decodeOperand_AReg_256(MCInst &Inst, unsigned Imm, 203 uint64_t Addr, 204 const MCDisassembler *Decoder) { 205 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 206 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW256, Imm | 512)); 207 } 208 209 static DecodeStatus decodeOperand_AReg_512(MCInst &Inst, unsigned Imm, 210 uint64_t Addr, 211 const MCDisassembler *Decoder) { 212 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 213 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm | 512)); 214 } 215 216 static DecodeStatus decodeOperand_AReg_1024(MCInst &Inst, unsigned Imm, 217 uint64_t Addr, 218 const MCDisassembler *Decoder) { 219 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 220 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm | 512)); 221 } 222 223 static DecodeStatus decodeOperand_VReg_64(MCInst &Inst, unsigned Imm, 224 uint64_t Addr, 225 const MCDisassembler *Decoder) { 226 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 227 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm)); 228 } 229 230 static DecodeStatus decodeOperand_VReg_128(MCInst &Inst, unsigned Imm, 231 uint64_t Addr, 232 const MCDisassembler *Decoder) { 233 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 234 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm)); 235 } 236 237 static DecodeStatus decodeOperand_VReg_256(MCInst &Inst, unsigned Imm, 238 uint64_t Addr, 239 const MCDisassembler *Decoder) { 240 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 241 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW256, Imm)); 242 } 243 244 static DecodeStatus decodeOperand_VReg_512(MCInst &Inst, unsigned Imm, 245 uint64_t Addr, 246 const MCDisassembler *Decoder) { 247 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 248 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm)); 249 } 250 251 static DecodeStatus decodeOperand_VReg_1024(MCInst &Inst, unsigned Imm, 252 uint64_t Addr, 253 const MCDisassembler *Decoder) { 254 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 255 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm)); 256 } 257 258 static DecodeStatus decodeOperand_f32kimm(MCInst &Inst, unsigned Imm, 259 uint64_t Addr, 260 const MCDisassembler *Decoder) { 261 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 262 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm)); 263 } 264 265 static DecodeStatus decodeOperand_f16kimm(MCInst &Inst, unsigned Imm, 266 uint64_t Addr, 267 const MCDisassembler *Decoder) { 268 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 269 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm)); 270 } 271 272 static DecodeStatus 273 decodeOperand_VS_16_Deferred(MCInst &Inst, unsigned Imm, uint64_t Addr, 274 const MCDisassembler *Decoder) { 275 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 276 return addOperand( 277 Inst, DAsm->decodeSrcOp(llvm::AMDGPUDisassembler::OPW16, Imm, true)); 278 } 279 280 static DecodeStatus 281 decodeOperand_VS_32_Deferred(MCInst &Inst, unsigned Imm, uint64_t Addr, 282 const MCDisassembler *Decoder) { 283 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 284 return addOperand( 285 Inst, DAsm->decodeSrcOp(llvm::AMDGPUDisassembler::OPW32, Imm, true)); 286 } 287 288 static bool IsAGPROperand(const MCInst &Inst, int OpIdx, 289 const MCRegisterInfo *MRI) { 290 if (OpIdx < 0) 291 return false; 292 293 const MCOperand &Op = Inst.getOperand(OpIdx); 294 if (!Op.isReg()) 295 return false; 296 297 unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0); 298 auto Reg = Sub ? Sub : Op.getReg(); 299 return Reg >= AMDGPU::AGPR0 && Reg <= AMDGPU::AGPR255; 300 } 301 302 static DecodeStatus decodeOperand_AVLdSt_Any(MCInst &Inst, unsigned Imm, 303 AMDGPUDisassembler::OpWidthTy Opw, 304 const MCDisassembler *Decoder) { 305 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 306 if (!DAsm->isGFX90A()) { 307 Imm &= 511; 308 } else { 309 // If atomic has both vdata and vdst their register classes are tied. 310 // The bit is decoded along with the vdst, first operand. We need to 311 // change register class to AGPR if vdst was AGPR. 312 // If a DS instruction has both data0 and data1 their register classes 313 // are also tied. 314 unsigned Opc = Inst.getOpcode(); 315 uint64_t TSFlags = DAsm->getMCII()->get(Opc).TSFlags; 316 uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0 317 : AMDGPU::OpName::vdata; 318 const MCRegisterInfo *MRI = DAsm->getContext().getRegisterInfo(); 319 int DataIdx = AMDGPU::getNamedOperandIdx(Opc, DataNameIdx); 320 if ((int)Inst.getNumOperands() == DataIdx) { 321 int DstIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst); 322 if (IsAGPROperand(Inst, DstIdx, MRI)) 323 Imm |= 512; 324 } 325 326 if (TSFlags & SIInstrFlags::DS) { 327 int Data2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data1); 328 if ((int)Inst.getNumOperands() == Data2Idx && 329 IsAGPROperand(Inst, DataIdx, MRI)) 330 Imm |= 512; 331 } 332 } 333 return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256)); 334 } 335 336 static DecodeStatus 337 DecodeAVLdSt_32RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 338 const MCDisassembler *Decoder) { 339 return decodeOperand_AVLdSt_Any(Inst, Imm, 340 AMDGPUDisassembler::OPW32, Decoder); 341 } 342 343 static DecodeStatus 344 DecodeAVLdSt_64RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 345 const MCDisassembler *Decoder) { 346 return decodeOperand_AVLdSt_Any(Inst, Imm, 347 AMDGPUDisassembler::OPW64, Decoder); 348 } 349 350 static DecodeStatus 351 DecodeAVLdSt_96RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 352 const MCDisassembler *Decoder) { 353 return decodeOperand_AVLdSt_Any(Inst, Imm, 354 AMDGPUDisassembler::OPW96, Decoder); 355 } 356 357 static DecodeStatus 358 DecodeAVLdSt_128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 359 const MCDisassembler *Decoder) { 360 return decodeOperand_AVLdSt_Any(Inst, Imm, 361 AMDGPUDisassembler::OPW128, Decoder); 362 } 363 364 static DecodeStatus decodeOperand_SReg_32(MCInst &Inst, unsigned Imm, 365 uint64_t Addr, 366 const MCDisassembler *Decoder) { 367 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 368 return addOperand(Inst, DAsm->decodeOperand_SReg_32(Imm)); 369 } 370 371 #define DECODE_SDWA(DecName) \ 372 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName) 373 374 DECODE_SDWA(Src32) 375 DECODE_SDWA(Src16) 376 DECODE_SDWA(VopcDst) 377 378 #include "AMDGPUGenDisassemblerTables.inc" 379 380 //===----------------------------------------------------------------------===// 381 // 382 //===----------------------------------------------------------------------===// 383 384 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) { 385 assert(Bytes.size() >= sizeof(T)); 386 const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data()); 387 Bytes = Bytes.slice(sizeof(T)); 388 return Res; 389 } 390 391 DecodeStatus AMDGPUDisassembler::tryDecodeInst(const uint8_t* Table, 392 MCInst &MI, 393 uint64_t Inst, 394 uint64_t Address) const { 395 assert(MI.getOpcode() == 0); 396 assert(MI.getNumOperands() == 0); 397 MCInst TmpInst; 398 HasLiteral = false; 399 const auto SavedBytes = Bytes; 400 if (decodeInstruction(Table, TmpInst, Inst, Address, this, STI)) { 401 MI = TmpInst; 402 return MCDisassembler::Success; 403 } 404 Bytes = SavedBytes; 405 return MCDisassembler::Fail; 406 } 407 408 // The disassembler is greedy, so we need to check FI operand value to 409 // not parse a dpp if the correct literal is not set. For dpp16 the 410 // autogenerated decoder checks the dpp literal 411 static bool isValidDPP8(const MCInst &MI) { 412 using namespace llvm::AMDGPU::DPP; 413 int FiIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::fi); 414 assert(FiIdx != -1); 415 if ((unsigned)FiIdx >= MI.getNumOperands()) 416 return false; 417 unsigned Fi = MI.getOperand(FiIdx).getImm(); 418 return Fi == DPP8_FI_0 || Fi == DPP8_FI_1; 419 } 420 421 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 422 ArrayRef<uint8_t> Bytes_, 423 uint64_t Address, 424 raw_ostream &CS) const { 425 CommentStream = &CS; 426 bool IsSDWA = false; 427 428 unsigned MaxInstBytesNum = std::min((size_t)TargetMaxInstBytes, Bytes_.size()); 429 Bytes = Bytes_.slice(0, MaxInstBytesNum); 430 431 DecodeStatus Res = MCDisassembler::Fail; 432 do { 433 // ToDo: better to switch encoding length using some bit predicate 434 // but it is unknown yet, so try all we can 435 436 // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2 437 // encodings 438 if (Bytes.size() >= 8) { 439 const uint64_t QW = eatBytes<uint64_t>(Bytes); 440 441 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) { 442 Res = tryDecodeInst(DecoderTableGFX10_B64, MI, QW, Address); 443 if (Res) { 444 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dpp8) 445 == -1) 446 break; 447 if (convertDPP8Inst(MI) == MCDisassembler::Success) 448 break; 449 MI = MCInst(); // clear 450 } 451 } 452 453 Res = tryDecodeInst(DecoderTableDPP864, MI, QW, Address); 454 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 455 break; 456 457 MI = MCInst(); // clear 458 459 Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address); 460 if (Res) break; 461 462 Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address); 463 if (Res) { IsSDWA = true; break; } 464 465 Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address); 466 if (Res) { IsSDWA = true; break; } 467 468 Res = tryDecodeInst(DecoderTableSDWA1064, MI, QW, Address); 469 if (Res) { IsSDWA = true; break; } 470 471 if (STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem]) { 472 Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address); 473 if (Res) 474 break; 475 } 476 477 // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and 478 // v_mad_mixhi_f16 for FMA variants. Try to decode using this special 479 // table first so we print the correct name. 480 if (STI.getFeatureBits()[AMDGPU::FeatureFmaMixInsts]) { 481 Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address); 482 if (Res) 483 break; 484 } 485 } 486 487 // Reinitialize Bytes as DPP64 could have eaten too much 488 Bytes = Bytes_.slice(0, MaxInstBytesNum); 489 490 // Try decode 32-bit instruction 491 if (Bytes.size() < 4) break; 492 const uint32_t DW = eatBytes<uint32_t>(Bytes); 493 Res = tryDecodeInst(DecoderTableGFX832, MI, DW, Address); 494 if (Res) break; 495 496 Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address); 497 if (Res) break; 498 499 Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address); 500 if (Res) break; 501 502 if (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]) { 503 Res = tryDecodeInst(DecoderTableGFX90A32, MI, DW, Address); 504 if (Res) 505 break; 506 } 507 508 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) { 509 Res = tryDecodeInst(DecoderTableGFX10_B32, MI, DW, Address); 510 if (Res) break; 511 } 512 513 Res = tryDecodeInst(DecoderTableGFX1032, MI, DW, Address); 514 if (Res) break; 515 516 if (Bytes.size() < 4) break; 517 const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW; 518 519 if (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]) { 520 Res = tryDecodeInst(DecoderTableGFX90A64, MI, QW, Address); 521 if (Res) 522 break; 523 } 524 525 Res = tryDecodeInst(DecoderTableGFX864, MI, QW, Address); 526 if (Res) break; 527 528 Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address); 529 if (Res) break; 530 531 Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address); 532 if (Res) break; 533 534 Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address); 535 } while (false); 536 537 if (Res && (MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi || 538 MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx6_gfx7 || 539 MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx10 || 540 MI.getOpcode() == AMDGPU::V_MAC_LEGACY_F32_e64_gfx6_gfx7 || 541 MI.getOpcode() == AMDGPU::V_MAC_LEGACY_F32_e64_gfx10 || 542 MI.getOpcode() == AMDGPU::V_MAC_F16_e64_vi || 543 MI.getOpcode() == AMDGPU::V_FMAC_F64_e64_gfx90a || 544 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_vi || 545 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_gfx10 || 546 MI.getOpcode() == AMDGPU::V_FMAC_LEGACY_F32_e64_gfx10 || 547 MI.getOpcode() == AMDGPU::V_FMAC_F16_e64_gfx10)) { 548 // Insert dummy unused src2_modifiers. 549 insertNamedMCOperand(MI, MCOperand::createImm(0), 550 AMDGPU::OpName::src2_modifiers); 551 } 552 553 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 554 (SIInstrFlags::MUBUF | SIInstrFlags::FLAT | SIInstrFlags::SMRD))) { 555 int CPolPos = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 556 AMDGPU::OpName::cpol); 557 if (CPolPos != -1) { 558 unsigned CPol = 559 (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::IsAtomicRet) ? 560 AMDGPU::CPol::GLC : 0; 561 if (MI.getNumOperands() <= (unsigned)CPolPos) { 562 insertNamedMCOperand(MI, MCOperand::createImm(CPol), 563 AMDGPU::OpName::cpol); 564 } else if (CPol) { 565 MI.getOperand(CPolPos).setImm(MI.getOperand(CPolPos).getImm() | CPol); 566 } 567 } 568 } 569 570 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 571 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF)) && 572 (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts])) { 573 // GFX90A lost TFE, its place is occupied by ACC. 574 int TFEOpIdx = 575 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::tfe); 576 if (TFEOpIdx != -1) { 577 auto TFEIter = MI.begin(); 578 std::advance(TFEIter, TFEOpIdx); 579 MI.insert(TFEIter, MCOperand::createImm(0)); 580 } 581 } 582 583 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 584 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF))) { 585 int SWZOpIdx = 586 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::swz); 587 if (SWZOpIdx != -1) { 588 auto SWZIter = MI.begin(); 589 std::advance(SWZIter, SWZOpIdx); 590 MI.insert(SWZIter, MCOperand::createImm(0)); 591 } 592 } 593 594 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) { 595 int VAddr0Idx = 596 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 597 int RsrcIdx = 598 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc); 599 unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1; 600 if (VAddr0Idx >= 0 && NSAArgs > 0) { 601 unsigned NSAWords = (NSAArgs + 3) / 4; 602 if (Bytes.size() < 4 * NSAWords) { 603 Res = MCDisassembler::Fail; 604 } else { 605 for (unsigned i = 0; i < NSAArgs; ++i) { 606 MI.insert(MI.begin() + VAddr0Idx + 1 + i, 607 decodeOperand_VGPR_32(Bytes[i])); 608 } 609 Bytes = Bytes.slice(4 * NSAWords); 610 } 611 } 612 613 if (Res) 614 Res = convertMIMGInst(MI); 615 } 616 617 if (Res && IsSDWA) 618 Res = convertSDWAInst(MI); 619 620 int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 621 AMDGPU::OpName::vdst_in); 622 if (VDstIn_Idx != -1) { 623 int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx, 624 MCOI::OperandConstraint::TIED_TO); 625 if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx || 626 !MI.getOperand(VDstIn_Idx).isReg() || 627 MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) { 628 if (MI.getNumOperands() > (unsigned)VDstIn_Idx) 629 MI.erase(&MI.getOperand(VDstIn_Idx)); 630 insertNamedMCOperand(MI, 631 MCOperand::createReg(MI.getOperand(Tied).getReg()), 632 AMDGPU::OpName::vdst_in); 633 } 634 } 635 636 int ImmLitIdx = 637 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::imm); 638 if (Res && ImmLitIdx != -1) 639 Res = convertFMAanyK(MI, ImmLitIdx); 640 641 // if the opcode was not recognized we'll assume a Size of 4 bytes 642 // (unless there are fewer bytes left) 643 Size = Res ? (MaxInstBytesNum - Bytes.size()) 644 : std::min((size_t)4, Bytes_.size()); 645 return Res; 646 } 647 648 DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const { 649 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 650 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 651 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst) != -1) 652 // VOPC - insert clamp 653 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp); 654 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 655 int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst); 656 if (SDst != -1) { 657 // VOPC - insert VCC register as sdst 658 insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC), 659 AMDGPU::OpName::sdst); 660 } else { 661 // VOP1/2 - insert omod if present in instruction 662 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod); 663 } 664 } 665 return MCDisassembler::Success; 666 } 667 668 // We must check FI == literal to reject not genuine dpp8 insts, and we must 669 // first add optional MI operands to check FI 670 DecodeStatus AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const { 671 unsigned Opc = MI.getOpcode(); 672 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 673 674 // Insert dummy unused src modifiers. 675 if (MI.getNumOperands() < DescNumOps && 676 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1) 677 insertNamedMCOperand(MI, MCOperand::createImm(0), 678 AMDGPU::OpName::src0_modifiers); 679 680 if (MI.getNumOperands() < DescNumOps && 681 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers) != -1) 682 insertNamedMCOperand(MI, MCOperand::createImm(0), 683 AMDGPU::OpName::src1_modifiers); 684 685 return isValidDPP8(MI) ? MCDisassembler::Success : MCDisassembler::SoftFail; 686 } 687 688 // Note that before gfx10, the MIMG encoding provided no information about 689 // VADDR size. Consequently, decoded instructions always show address as if it 690 // has 1 dword, which could be not really so. 691 DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const { 692 693 int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 694 AMDGPU::OpName::vdst); 695 696 int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 697 AMDGPU::OpName::vdata); 698 int VAddr0Idx = 699 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 700 int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 701 AMDGPU::OpName::dmask); 702 703 int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 704 AMDGPU::OpName::tfe); 705 int D16Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 706 AMDGPU::OpName::d16); 707 708 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode()); 709 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = 710 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); 711 712 assert(VDataIdx != -1); 713 if (BaseOpcode->BVH) { 714 // Add A16 operand for intersect_ray instructions 715 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16) > -1) { 716 addOperand(MI, MCOperand::createImm(1)); 717 } 718 return MCDisassembler::Success; 719 } 720 721 bool IsAtomic = (VDstIdx != -1); 722 bool IsGather4 = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::Gather4; 723 bool IsNSA = false; 724 unsigned AddrSize = Info->VAddrDwords; 725 726 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 727 unsigned DimIdx = 728 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim); 729 int A16Idx = 730 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16); 731 const AMDGPU::MIMGDimInfo *Dim = 732 AMDGPU::getMIMGDimInfoByEncoding(MI.getOperand(DimIdx).getImm()); 733 const bool IsA16 = (A16Idx != -1 && MI.getOperand(A16Idx).getImm()); 734 735 AddrSize = 736 AMDGPU::getAddrSizeMIMGOp(BaseOpcode, Dim, IsA16, AMDGPU::hasG16(STI)); 737 738 IsNSA = Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA; 739 if (!IsNSA) { 740 if (AddrSize > 8) 741 AddrSize = 16; 742 } else { 743 if (AddrSize > Info->VAddrDwords) { 744 // The NSA encoding does not contain enough operands for the combination 745 // of base opcode / dimension. Should this be an error? 746 return MCDisassembler::Success; 747 } 748 } 749 } 750 751 unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf; 752 unsigned DstSize = IsGather4 ? 4 : std::max(countPopulation(DMask), 1u); 753 754 bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm(); 755 if (D16 && AMDGPU::hasPackedD16(STI)) { 756 DstSize = (DstSize + 1) / 2; 757 } 758 759 if (TFEIdx != -1 && MI.getOperand(TFEIdx).getImm()) 760 DstSize += 1; 761 762 if (DstSize == Info->VDataDwords && AddrSize == Info->VAddrDwords) 763 return MCDisassembler::Success; 764 765 int NewOpcode = 766 AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize); 767 if (NewOpcode == -1) 768 return MCDisassembler::Success; 769 770 // Widen the register to the correct number of enabled channels. 771 unsigned NewVdata = AMDGPU::NoRegister; 772 if (DstSize != Info->VDataDwords) { 773 auto DataRCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass; 774 775 // Get first subregister of VData 776 unsigned Vdata0 = MI.getOperand(VDataIdx).getReg(); 777 unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0); 778 Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0; 779 780 NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0, 781 &MRI.getRegClass(DataRCID)); 782 if (NewVdata == AMDGPU::NoRegister) { 783 // It's possible to encode this such that the low register + enabled 784 // components exceeds the register count. 785 return MCDisassembler::Success; 786 } 787 } 788 789 unsigned NewVAddr0 = AMDGPU::NoRegister; 790 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10] && !IsNSA && 791 AddrSize != Info->VAddrDwords) { 792 unsigned VAddr0 = MI.getOperand(VAddr0Idx).getReg(); 793 unsigned VAddrSub0 = MRI.getSubReg(VAddr0, AMDGPU::sub0); 794 VAddr0 = (VAddrSub0 != 0) ? VAddrSub0 : VAddr0; 795 796 auto AddrRCID = MCII->get(NewOpcode).OpInfo[VAddr0Idx].RegClass; 797 NewVAddr0 = MRI.getMatchingSuperReg(VAddr0, AMDGPU::sub0, 798 &MRI.getRegClass(AddrRCID)); 799 if (NewVAddr0 == AMDGPU::NoRegister) 800 return MCDisassembler::Success; 801 } 802 803 MI.setOpcode(NewOpcode); 804 805 if (NewVdata != AMDGPU::NoRegister) { 806 MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata); 807 808 if (IsAtomic) { 809 // Atomic operations have an additional operand (a copy of data) 810 MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata); 811 } 812 } 813 814 if (NewVAddr0 != AMDGPU::NoRegister) { 815 MI.getOperand(VAddr0Idx) = MCOperand::createReg(NewVAddr0); 816 } else if (IsNSA) { 817 assert(AddrSize <= Info->VAddrDwords); 818 MI.erase(MI.begin() + VAddr0Idx + AddrSize, 819 MI.begin() + VAddr0Idx + Info->VAddrDwords); 820 } 821 822 return MCDisassembler::Success; 823 } 824 825 DecodeStatus AMDGPUDisassembler::convertFMAanyK(MCInst &MI, 826 int ImmLitIdx) const { 827 assert(HasLiteral && "Should have decoded a literal"); 828 const MCInstrDesc &Desc = MCII->get(MI.getOpcode()); 829 unsigned DescNumOps = Desc.getNumOperands(); 830 assert(DescNumOps == MI.getNumOperands()); 831 for (unsigned I = 0; I < DescNumOps; ++I) { 832 auto &Op = MI.getOperand(I); 833 auto OpType = Desc.OpInfo[I].OperandType; 834 bool IsDeferredOp = (OpType == AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED || 835 OpType == AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED); 836 if (Op.isImm() && Op.getImm() == AMDGPU::EncValues::LITERAL_CONST && 837 IsDeferredOp) 838 Op.setImm(Literal); 839 } 840 return MCDisassembler::Success; 841 } 842 843 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { 844 return getContext().getRegisterInfo()-> 845 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); 846 } 847 848 inline 849 MCOperand AMDGPUDisassembler::errOperand(unsigned V, 850 const Twine& ErrMsg) const { 851 *CommentStream << "Error: " + ErrMsg; 852 853 // ToDo: add support for error operands to MCInst.h 854 // return MCOperand::createError(V); 855 return MCOperand(); 856 } 857 858 inline 859 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const { 860 return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI)); 861 } 862 863 inline 864 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, 865 unsigned Val) const { 866 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; 867 if (Val >= RegCl.getNumRegs()) 868 return errOperand(Val, Twine(getRegClassName(RegClassID)) + 869 ": unknown register " + Twine(Val)); 870 return createRegOperand(RegCl.getRegister(Val)); 871 } 872 873 inline 874 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID, 875 unsigned Val) const { 876 // ToDo: SI/CI have 104 SGPRs, VI - 102 877 // Valery: here we accepting as much as we can, let assembler sort it out 878 int shift = 0; 879 switch (SRegClassID) { 880 case AMDGPU::SGPR_32RegClassID: 881 case AMDGPU::TTMP_32RegClassID: 882 break; 883 case AMDGPU::SGPR_64RegClassID: 884 case AMDGPU::TTMP_64RegClassID: 885 shift = 1; 886 break; 887 case AMDGPU::SGPR_128RegClassID: 888 case AMDGPU::TTMP_128RegClassID: 889 // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in 890 // this bundle? 891 case AMDGPU::SGPR_256RegClassID: 892 case AMDGPU::TTMP_256RegClassID: 893 // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in 894 // this bundle? 895 case AMDGPU::SGPR_512RegClassID: 896 case AMDGPU::TTMP_512RegClassID: 897 shift = 2; 898 break; 899 // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in 900 // this bundle? 901 default: 902 llvm_unreachable("unhandled register class"); 903 } 904 905 if (Val % (1 << shift)) { 906 *CommentStream << "Warning: " << getRegClassName(SRegClassID) 907 << ": scalar reg isn't aligned " << Val; 908 } 909 910 return createRegOperand(SRegClassID, Val >> shift); 911 } 912 913 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const { 914 return decodeSrcOp(OPW32, Val); 915 } 916 917 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const { 918 return decodeSrcOp(OPW64, Val); 919 } 920 921 MCOperand AMDGPUDisassembler::decodeOperand_VS_128(unsigned Val) const { 922 return decodeSrcOp(OPW128, Val); 923 } 924 925 MCOperand AMDGPUDisassembler::decodeOperand_VSrc16(unsigned Val) const { 926 return decodeSrcOp(OPW16, Val); 927 } 928 929 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV216(unsigned Val) const { 930 return decodeSrcOp(OPWV216, Val); 931 } 932 933 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV232(unsigned Val) const { 934 return decodeSrcOp(OPWV232, Val); 935 } 936 937 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const { 938 // Some instructions have operand restrictions beyond what the encoding 939 // allows. Some ordinarily VSrc_32 operands are VGPR_32, so clear the extra 940 // high bit. 941 Val &= 255; 942 943 return createRegOperand(AMDGPU::VGPR_32RegClassID, Val); 944 } 945 946 MCOperand AMDGPUDisassembler::decodeOperand_VRegOrLds_32(unsigned Val) const { 947 return decodeSrcOp(OPW32, Val); 948 } 949 950 MCOperand AMDGPUDisassembler::decodeOperand_AGPR_32(unsigned Val) const { 951 return createRegOperand(AMDGPU::AGPR_32RegClassID, Val & 255); 952 } 953 954 MCOperand AMDGPUDisassembler::decodeOperand_AReg_64(unsigned Val) const { 955 return createRegOperand(AMDGPU::AReg_64RegClassID, Val & 255); 956 } 957 958 MCOperand AMDGPUDisassembler::decodeOperand_AReg_128(unsigned Val) const { 959 return createRegOperand(AMDGPU::AReg_128RegClassID, Val & 255); 960 } 961 962 MCOperand AMDGPUDisassembler::decodeOperand_AReg_256(unsigned Val) const { 963 return createRegOperand(AMDGPU::AReg_256RegClassID, Val & 255); 964 } 965 966 MCOperand AMDGPUDisassembler::decodeOperand_AReg_512(unsigned Val) const { 967 return createRegOperand(AMDGPU::AReg_512RegClassID, Val & 255); 968 } 969 970 MCOperand AMDGPUDisassembler::decodeOperand_AReg_1024(unsigned Val) const { 971 return createRegOperand(AMDGPU::AReg_1024RegClassID, Val & 255); 972 } 973 974 MCOperand AMDGPUDisassembler::decodeOperand_AV_32(unsigned Val) const { 975 return decodeSrcOp(OPW32, Val); 976 } 977 978 MCOperand AMDGPUDisassembler::decodeOperand_AV_64(unsigned Val) const { 979 return decodeSrcOp(OPW64, Val); 980 } 981 982 MCOperand AMDGPUDisassembler::decodeOperand_AV_128(unsigned Val) const { 983 return decodeSrcOp(OPW128, Val); 984 } 985 986 MCOperand AMDGPUDisassembler::decodeOperand_AV_512(unsigned Val) const { 987 return decodeSrcOp(OPW512, Val); 988 } 989 990 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const { 991 return createRegOperand(AMDGPU::VReg_64RegClassID, Val); 992 } 993 994 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const { 995 return createRegOperand(AMDGPU::VReg_96RegClassID, Val); 996 } 997 998 MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const { 999 return createRegOperand(AMDGPU::VReg_128RegClassID, Val); 1000 } 1001 1002 MCOperand AMDGPUDisassembler::decodeOperand_VReg_256(unsigned Val) const { 1003 return createRegOperand(AMDGPU::VReg_256RegClassID, Val); 1004 } 1005 1006 MCOperand AMDGPUDisassembler::decodeOperand_VReg_512(unsigned Val) const { 1007 return createRegOperand(AMDGPU::VReg_512RegClassID, Val); 1008 } 1009 1010 MCOperand AMDGPUDisassembler::decodeOperand_VReg_1024(unsigned Val) const { 1011 return createRegOperand(AMDGPU::VReg_1024RegClassID, Val); 1012 } 1013 1014 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const { 1015 // table-gen generated disassembler doesn't care about operand types 1016 // leaving only registry class so SSrc_32 operand turns into SReg_32 1017 // and therefore we accept immediates and literals here as well 1018 return decodeSrcOp(OPW32, Val); 1019 } 1020 1021 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0_XEXEC( 1022 unsigned Val) const { 1023 // SReg_32_XM0 is SReg_32 without M0 or EXEC_LO/EXEC_HI 1024 return decodeOperand_SReg_32(Val); 1025 } 1026 1027 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XEXEC_HI( 1028 unsigned Val) const { 1029 // SReg_32_XM0 is SReg_32 without EXEC_HI 1030 return decodeOperand_SReg_32(Val); 1031 } 1032 1033 MCOperand AMDGPUDisassembler::decodeOperand_SRegOrLds_32(unsigned Val) const { 1034 // table-gen generated disassembler doesn't care about operand types 1035 // leaving only registry class so SSrc_32 operand turns into SReg_32 1036 // and therefore we accept immediates and literals here as well 1037 return decodeSrcOp(OPW32, Val); 1038 } 1039 1040 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const { 1041 return decodeSrcOp(OPW64, Val); 1042 } 1043 1044 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64_XEXEC(unsigned Val) const { 1045 return decodeSrcOp(OPW64, Val); 1046 } 1047 1048 MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const { 1049 return decodeSrcOp(OPW128, Val); 1050 } 1051 1052 MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const { 1053 return decodeDstOp(OPW256, Val); 1054 } 1055 1056 MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const { 1057 return decodeDstOp(OPW512, Val); 1058 } 1059 1060 // Decode Literals for insts which always have a literal in the encoding 1061 MCOperand 1062 AMDGPUDisassembler::decodeMandatoryLiteralConstant(unsigned Val) const { 1063 if (HasLiteral) { 1064 if (Literal != Val) 1065 return errOperand(Val, "More than one unique literal is illegal"); 1066 } 1067 HasLiteral = true; 1068 Literal = Val; 1069 return MCOperand::createImm(Literal); 1070 } 1071 1072 MCOperand AMDGPUDisassembler::decodeLiteralConstant() const { 1073 // For now all literal constants are supposed to be unsigned integer 1074 // ToDo: deal with signed/unsigned 64-bit integer constants 1075 // ToDo: deal with float/double constants 1076 if (!HasLiteral) { 1077 if (Bytes.size() < 4) { 1078 return errOperand(0, "cannot read literal, inst bytes left " + 1079 Twine(Bytes.size())); 1080 } 1081 HasLiteral = true; 1082 Literal = eatBytes<uint32_t>(Bytes); 1083 } 1084 return MCOperand::createImm(Literal); 1085 } 1086 1087 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) { 1088 using namespace AMDGPU::EncValues; 1089 1090 assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX); 1091 return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ? 1092 (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) : 1093 (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm))); 1094 // Cast prevents negative overflow. 1095 } 1096 1097 static int64_t getInlineImmVal32(unsigned Imm) { 1098 switch (Imm) { 1099 case 240: 1100 return FloatToBits(0.5f); 1101 case 241: 1102 return FloatToBits(-0.5f); 1103 case 242: 1104 return FloatToBits(1.0f); 1105 case 243: 1106 return FloatToBits(-1.0f); 1107 case 244: 1108 return FloatToBits(2.0f); 1109 case 245: 1110 return FloatToBits(-2.0f); 1111 case 246: 1112 return FloatToBits(4.0f); 1113 case 247: 1114 return FloatToBits(-4.0f); 1115 case 248: // 1 / (2 * PI) 1116 return 0x3e22f983; 1117 default: 1118 llvm_unreachable("invalid fp inline imm"); 1119 } 1120 } 1121 1122 static int64_t getInlineImmVal64(unsigned Imm) { 1123 switch (Imm) { 1124 case 240: 1125 return DoubleToBits(0.5); 1126 case 241: 1127 return DoubleToBits(-0.5); 1128 case 242: 1129 return DoubleToBits(1.0); 1130 case 243: 1131 return DoubleToBits(-1.0); 1132 case 244: 1133 return DoubleToBits(2.0); 1134 case 245: 1135 return DoubleToBits(-2.0); 1136 case 246: 1137 return DoubleToBits(4.0); 1138 case 247: 1139 return DoubleToBits(-4.0); 1140 case 248: // 1 / (2 * PI) 1141 return 0x3fc45f306dc9c882; 1142 default: 1143 llvm_unreachable("invalid fp inline imm"); 1144 } 1145 } 1146 1147 static int64_t getInlineImmVal16(unsigned Imm) { 1148 switch (Imm) { 1149 case 240: 1150 return 0x3800; 1151 case 241: 1152 return 0xB800; 1153 case 242: 1154 return 0x3C00; 1155 case 243: 1156 return 0xBC00; 1157 case 244: 1158 return 0x4000; 1159 case 245: 1160 return 0xC000; 1161 case 246: 1162 return 0x4400; 1163 case 247: 1164 return 0xC400; 1165 case 248: // 1 / (2 * PI) 1166 return 0x3118; 1167 default: 1168 llvm_unreachable("invalid fp inline imm"); 1169 } 1170 } 1171 1172 MCOperand AMDGPUDisassembler::decodeFPImmed(OpWidthTy Width, unsigned Imm) { 1173 assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN 1174 && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX); 1175 1176 // ToDo: case 248: 1/(2*PI) - is allowed only on VI 1177 switch (Width) { 1178 case OPW32: 1179 case OPW128: // splat constants 1180 case OPW512: 1181 case OPW1024: 1182 case OPWV232: 1183 return MCOperand::createImm(getInlineImmVal32(Imm)); 1184 case OPW64: 1185 case OPW256: 1186 return MCOperand::createImm(getInlineImmVal64(Imm)); 1187 case OPW16: 1188 case OPWV216: 1189 return MCOperand::createImm(getInlineImmVal16(Imm)); 1190 default: 1191 llvm_unreachable("implement me"); 1192 } 1193 } 1194 1195 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const { 1196 using namespace AMDGPU; 1197 1198 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1199 switch (Width) { 1200 default: // fall 1201 case OPW32: 1202 case OPW16: 1203 case OPWV216: 1204 return VGPR_32RegClassID; 1205 case OPW64: 1206 case OPWV232: return VReg_64RegClassID; 1207 case OPW96: return VReg_96RegClassID; 1208 case OPW128: return VReg_128RegClassID; 1209 case OPW160: return VReg_160RegClassID; 1210 case OPW256: return VReg_256RegClassID; 1211 case OPW512: return VReg_512RegClassID; 1212 case OPW1024: return VReg_1024RegClassID; 1213 } 1214 } 1215 1216 unsigned AMDGPUDisassembler::getAgprClassId(const OpWidthTy Width) const { 1217 using namespace AMDGPU; 1218 1219 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1220 switch (Width) { 1221 default: // fall 1222 case OPW32: 1223 case OPW16: 1224 case OPWV216: 1225 return AGPR_32RegClassID; 1226 case OPW64: 1227 case OPWV232: return AReg_64RegClassID; 1228 case OPW96: return AReg_96RegClassID; 1229 case OPW128: return AReg_128RegClassID; 1230 case OPW160: return AReg_160RegClassID; 1231 case OPW256: return AReg_256RegClassID; 1232 case OPW512: return AReg_512RegClassID; 1233 case OPW1024: return AReg_1024RegClassID; 1234 } 1235 } 1236 1237 1238 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const { 1239 using namespace AMDGPU; 1240 1241 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1242 switch (Width) { 1243 default: // fall 1244 case OPW32: 1245 case OPW16: 1246 case OPWV216: 1247 return SGPR_32RegClassID; 1248 case OPW64: 1249 case OPWV232: return SGPR_64RegClassID; 1250 case OPW96: return SGPR_96RegClassID; 1251 case OPW128: return SGPR_128RegClassID; 1252 case OPW160: return SGPR_160RegClassID; 1253 case OPW256: return SGPR_256RegClassID; 1254 case OPW512: return SGPR_512RegClassID; 1255 } 1256 } 1257 1258 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const { 1259 using namespace AMDGPU; 1260 1261 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1262 switch (Width) { 1263 default: // fall 1264 case OPW32: 1265 case OPW16: 1266 case OPWV216: 1267 return TTMP_32RegClassID; 1268 case OPW64: 1269 case OPWV232: return TTMP_64RegClassID; 1270 case OPW128: return TTMP_128RegClassID; 1271 case OPW256: return TTMP_256RegClassID; 1272 case OPW512: return TTMP_512RegClassID; 1273 } 1274 } 1275 1276 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const { 1277 using namespace AMDGPU::EncValues; 1278 1279 unsigned TTmpMin = isGFX9Plus() ? TTMP_GFX9PLUS_MIN : TTMP_VI_MIN; 1280 unsigned TTmpMax = isGFX9Plus() ? TTMP_GFX9PLUS_MAX : TTMP_VI_MAX; 1281 1282 return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1; 1283 } 1284 1285 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val, 1286 bool MandatoryLiteral) const { 1287 using namespace AMDGPU::EncValues; 1288 1289 assert(Val < 1024); // enum10 1290 1291 bool IsAGPR = Val & 512; 1292 Val &= 511; 1293 1294 if (VGPR_MIN <= Val && Val <= VGPR_MAX) { 1295 return createRegOperand(IsAGPR ? getAgprClassId(Width) 1296 : getVgprClassId(Width), Val - VGPR_MIN); 1297 } 1298 if (Val <= SGPR_MAX) { 1299 // "SGPR_MIN <= Val" is always true and causes compilation warning. 1300 static_assert(SGPR_MIN == 0, ""); 1301 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1302 } 1303 1304 int TTmpIdx = getTTmpIdx(Val); 1305 if (TTmpIdx >= 0) { 1306 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1307 } 1308 1309 if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX) 1310 return decodeIntImmed(Val); 1311 1312 if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX) 1313 return decodeFPImmed(Width, Val); 1314 1315 if (Val == LITERAL_CONST) { 1316 if (MandatoryLiteral) 1317 // Keep a sentinel value for deferred setting 1318 return MCOperand::createImm(LITERAL_CONST); 1319 else 1320 return decodeLiteralConstant(); 1321 } 1322 1323 switch (Width) { 1324 case OPW32: 1325 case OPW16: 1326 case OPWV216: 1327 return decodeSpecialReg32(Val); 1328 case OPW64: 1329 case OPWV232: 1330 return decodeSpecialReg64(Val); 1331 default: 1332 llvm_unreachable("unexpected immediate type"); 1333 } 1334 } 1335 1336 MCOperand AMDGPUDisassembler::decodeDstOp(const OpWidthTy Width, unsigned Val) const { 1337 using namespace AMDGPU::EncValues; 1338 1339 assert(Val < 128); 1340 assert(Width == OPW256 || Width == OPW512); 1341 1342 if (Val <= SGPR_MAX) { 1343 // "SGPR_MIN <= Val" is always true and causes compilation warning. 1344 static_assert(SGPR_MIN == 0, ""); 1345 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1346 } 1347 1348 int TTmpIdx = getTTmpIdx(Val); 1349 if (TTmpIdx >= 0) { 1350 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1351 } 1352 1353 llvm_unreachable("unknown dst register"); 1354 } 1355 1356 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { 1357 using namespace AMDGPU; 1358 1359 switch (Val) { 1360 case 102: return createRegOperand(FLAT_SCR_LO); 1361 case 103: return createRegOperand(FLAT_SCR_HI); 1362 case 104: return createRegOperand(XNACK_MASK_LO); 1363 case 105: return createRegOperand(XNACK_MASK_HI); 1364 case 106: return createRegOperand(VCC_LO); 1365 case 107: return createRegOperand(VCC_HI); 1366 case 108: return createRegOperand(TBA_LO); 1367 case 109: return createRegOperand(TBA_HI); 1368 case 110: return createRegOperand(TMA_LO); 1369 case 111: return createRegOperand(TMA_HI); 1370 case 124: return createRegOperand(M0); 1371 case 125: return createRegOperand(SGPR_NULL); 1372 case 126: return createRegOperand(EXEC_LO); 1373 case 127: return createRegOperand(EXEC_HI); 1374 case 235: return createRegOperand(SRC_SHARED_BASE); 1375 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1376 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1377 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1378 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1379 case 251: return createRegOperand(SRC_VCCZ); 1380 case 252: return createRegOperand(SRC_EXECZ); 1381 case 253: return createRegOperand(SRC_SCC); 1382 case 254: return createRegOperand(LDS_DIRECT); 1383 default: break; 1384 } 1385 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1386 } 1387 1388 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { 1389 using namespace AMDGPU; 1390 1391 switch (Val) { 1392 case 102: return createRegOperand(FLAT_SCR); 1393 case 104: return createRegOperand(XNACK_MASK); 1394 case 106: return createRegOperand(VCC); 1395 case 108: return createRegOperand(TBA); 1396 case 110: return createRegOperand(TMA); 1397 case 125: return createRegOperand(SGPR_NULL); 1398 case 126: return createRegOperand(EXEC); 1399 case 235: return createRegOperand(SRC_SHARED_BASE); 1400 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1401 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1402 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1403 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1404 case 251: return createRegOperand(SRC_VCCZ); 1405 case 252: return createRegOperand(SRC_EXECZ); 1406 case 253: return createRegOperand(SRC_SCC); 1407 default: break; 1408 } 1409 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1410 } 1411 1412 MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width, 1413 const unsigned Val) const { 1414 using namespace AMDGPU::SDWA; 1415 using namespace AMDGPU::EncValues; 1416 1417 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 1418 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 1419 // XXX: cast to int is needed to avoid stupid warning: 1420 // compare with unsigned is always true 1421 if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) && 1422 Val <= SDWA9EncValues::SRC_VGPR_MAX) { 1423 return createRegOperand(getVgprClassId(Width), 1424 Val - SDWA9EncValues::SRC_VGPR_MIN); 1425 } 1426 if (SDWA9EncValues::SRC_SGPR_MIN <= Val && 1427 Val <= (isGFX10Plus() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10 1428 : SDWA9EncValues::SRC_SGPR_MAX_SI)) { 1429 return createSRegOperand(getSgprClassId(Width), 1430 Val - SDWA9EncValues::SRC_SGPR_MIN); 1431 } 1432 if (SDWA9EncValues::SRC_TTMP_MIN <= Val && 1433 Val <= SDWA9EncValues::SRC_TTMP_MAX) { 1434 return createSRegOperand(getTtmpClassId(Width), 1435 Val - SDWA9EncValues::SRC_TTMP_MIN); 1436 } 1437 1438 const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN; 1439 1440 if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX) 1441 return decodeIntImmed(SVal); 1442 1443 if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX) 1444 return decodeFPImmed(Width, SVal); 1445 1446 return decodeSpecialReg32(SVal); 1447 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 1448 return createRegOperand(getVgprClassId(Width), Val); 1449 } 1450 llvm_unreachable("unsupported target"); 1451 } 1452 1453 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const { 1454 return decodeSDWASrc(OPW16, Val); 1455 } 1456 1457 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const { 1458 return decodeSDWASrc(OPW32, Val); 1459 } 1460 1461 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const { 1462 using namespace AMDGPU::SDWA; 1463 1464 assert((STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 1465 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) && 1466 "SDWAVopcDst should be present only on GFX9+"); 1467 1468 bool IsWave64 = STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64]; 1469 1470 if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) { 1471 Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK; 1472 1473 int TTmpIdx = getTTmpIdx(Val); 1474 if (TTmpIdx >= 0) { 1475 auto TTmpClsId = getTtmpClassId(IsWave64 ? OPW64 : OPW32); 1476 return createSRegOperand(TTmpClsId, TTmpIdx); 1477 } else if (Val > SGPR_MAX) { 1478 return IsWave64 ? decodeSpecialReg64(Val) 1479 : decodeSpecialReg32(Val); 1480 } else { 1481 return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val); 1482 } 1483 } else { 1484 return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO); 1485 } 1486 } 1487 1488 MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const { 1489 return STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ? 1490 decodeOperand_SReg_64(Val) : decodeOperand_SReg_32(Val); 1491 } 1492 1493 bool AMDGPUDisassembler::isVI() const { 1494 return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]; 1495 } 1496 1497 bool AMDGPUDisassembler::isGFX9() const { return AMDGPU::isGFX9(STI); } 1498 1499 bool AMDGPUDisassembler::isGFX90A() const { 1500 return STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]; 1501 } 1502 1503 bool AMDGPUDisassembler::isGFX9Plus() const { return AMDGPU::isGFX9Plus(STI); } 1504 1505 bool AMDGPUDisassembler::isGFX10() const { return AMDGPU::isGFX10(STI); } 1506 1507 bool AMDGPUDisassembler::isGFX10Plus() const { 1508 return AMDGPU::isGFX10Plus(STI); 1509 } 1510 1511 bool AMDGPUDisassembler::hasArchitectedFlatScratch() const { 1512 return STI.getFeatureBits()[AMDGPU::FeatureArchitectedFlatScratch]; 1513 } 1514 1515 //===----------------------------------------------------------------------===// 1516 // AMDGPU specific symbol handling 1517 //===----------------------------------------------------------------------===// 1518 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1519 do { \ 1520 KdStream << Indent << DIRECTIVE " " \ 1521 << ((FourByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 1522 } while (0) 1523 1524 // NOLINTNEXTLINE(readability-identifier-naming) 1525 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1( 1526 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1527 using namespace amdhsa; 1528 StringRef Indent = "\t"; 1529 1530 // We cannot accurately backward compute #VGPRs used from 1531 // GRANULATED_WORKITEM_VGPR_COUNT. But we are concerned with getting the same 1532 // value of GRANULATED_WORKITEM_VGPR_COUNT in the reassembled binary. So we 1533 // simply calculate the inverse of what the assembler does. 1534 1535 uint32_t GranulatedWorkitemVGPRCount = 1536 (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT) >> 1537 COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT_SHIFT; 1538 1539 uint32_t NextFreeVGPR = (GranulatedWorkitemVGPRCount + 1) * 1540 AMDGPU::IsaInfo::getVGPREncodingGranule(&STI); 1541 1542 KdStream << Indent << ".amdhsa_next_free_vgpr " << NextFreeVGPR << '\n'; 1543 1544 // We cannot backward compute values used to calculate 1545 // GRANULATED_WAVEFRONT_SGPR_COUNT. Hence the original values for following 1546 // directives can't be computed: 1547 // .amdhsa_reserve_vcc 1548 // .amdhsa_reserve_flat_scratch 1549 // .amdhsa_reserve_xnack_mask 1550 // They take their respective default values if not specified in the assembly. 1551 // 1552 // GRANULATED_WAVEFRONT_SGPR_COUNT 1553 // = f(NEXT_FREE_SGPR + VCC + FLAT_SCRATCH + XNACK_MASK) 1554 // 1555 // We compute the inverse as though all directives apart from NEXT_FREE_SGPR 1556 // are set to 0. So while disassembling we consider that: 1557 // 1558 // GRANULATED_WAVEFRONT_SGPR_COUNT 1559 // = f(NEXT_FREE_SGPR + 0 + 0 + 0) 1560 // 1561 // The disassembler cannot recover the original values of those 3 directives. 1562 1563 uint32_t GranulatedWavefrontSGPRCount = 1564 (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT) >> 1565 COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT_SHIFT; 1566 1567 if (isGFX10Plus() && GranulatedWavefrontSGPRCount) 1568 return MCDisassembler::Fail; 1569 1570 uint32_t NextFreeSGPR = (GranulatedWavefrontSGPRCount + 1) * 1571 AMDGPU::IsaInfo::getSGPREncodingGranule(&STI); 1572 1573 KdStream << Indent << ".amdhsa_reserve_vcc " << 0 << '\n'; 1574 if (!hasArchitectedFlatScratch()) 1575 KdStream << Indent << ".amdhsa_reserve_flat_scratch " << 0 << '\n'; 1576 KdStream << Indent << ".amdhsa_reserve_xnack_mask " << 0 << '\n'; 1577 KdStream << Indent << ".amdhsa_next_free_sgpr " << NextFreeSGPR << "\n"; 1578 1579 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIORITY) 1580 return MCDisassembler::Fail; 1581 1582 PRINT_DIRECTIVE(".amdhsa_float_round_mode_32", 1583 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); 1584 PRINT_DIRECTIVE(".amdhsa_float_round_mode_16_64", 1585 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); 1586 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_32", 1587 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); 1588 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_16_64", 1589 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); 1590 1591 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIV) 1592 return MCDisassembler::Fail; 1593 1594 PRINT_DIRECTIVE(".amdhsa_dx10_clamp", COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP); 1595 1596 if (FourByteBuffer & COMPUTE_PGM_RSRC1_DEBUG_MODE) 1597 return MCDisassembler::Fail; 1598 1599 PRINT_DIRECTIVE(".amdhsa_ieee_mode", COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE); 1600 1601 if (FourByteBuffer & COMPUTE_PGM_RSRC1_BULKY) 1602 return MCDisassembler::Fail; 1603 1604 if (FourByteBuffer & COMPUTE_PGM_RSRC1_CDBG_USER) 1605 return MCDisassembler::Fail; 1606 1607 PRINT_DIRECTIVE(".amdhsa_fp16_overflow", COMPUTE_PGM_RSRC1_FP16_OVFL); 1608 1609 if (FourByteBuffer & COMPUTE_PGM_RSRC1_RESERVED0) 1610 return MCDisassembler::Fail; 1611 1612 if (isGFX10Plus()) { 1613 PRINT_DIRECTIVE(".amdhsa_workgroup_processor_mode", 1614 COMPUTE_PGM_RSRC1_WGP_MODE); 1615 PRINT_DIRECTIVE(".amdhsa_memory_ordered", COMPUTE_PGM_RSRC1_MEM_ORDERED); 1616 PRINT_DIRECTIVE(".amdhsa_forward_progress", COMPUTE_PGM_RSRC1_FWD_PROGRESS); 1617 } 1618 return MCDisassembler::Success; 1619 } 1620 1621 // NOLINTNEXTLINE(readability-identifier-naming) 1622 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2( 1623 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1624 using namespace amdhsa; 1625 StringRef Indent = "\t"; 1626 if (hasArchitectedFlatScratch()) 1627 PRINT_DIRECTIVE(".amdhsa_enable_private_segment", 1628 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1629 else 1630 PRINT_DIRECTIVE(".amdhsa_system_sgpr_private_segment_wavefront_offset", 1631 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1632 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_x", 1633 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); 1634 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_y", 1635 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); 1636 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_z", 1637 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); 1638 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_info", 1639 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); 1640 PRINT_DIRECTIVE(".amdhsa_system_vgpr_workitem_id", 1641 COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); 1642 1643 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_ADDRESS_WATCH) 1644 return MCDisassembler::Fail; 1645 1646 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_MEMORY) 1647 return MCDisassembler::Fail; 1648 1649 if (FourByteBuffer & COMPUTE_PGM_RSRC2_GRANULATED_LDS_SIZE) 1650 return MCDisassembler::Fail; 1651 1652 PRINT_DIRECTIVE( 1653 ".amdhsa_exception_fp_ieee_invalid_op", 1654 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); 1655 PRINT_DIRECTIVE(".amdhsa_exception_fp_denorm_src", 1656 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); 1657 PRINT_DIRECTIVE( 1658 ".amdhsa_exception_fp_ieee_div_zero", 1659 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); 1660 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_overflow", 1661 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); 1662 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_underflow", 1663 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); 1664 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_inexact", 1665 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); 1666 PRINT_DIRECTIVE(".amdhsa_exception_int_div_zero", 1667 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); 1668 1669 if (FourByteBuffer & COMPUTE_PGM_RSRC2_RESERVED0) 1670 return MCDisassembler::Fail; 1671 1672 return MCDisassembler::Success; 1673 } 1674 1675 #undef PRINT_DIRECTIVE 1676 1677 MCDisassembler::DecodeStatus 1678 AMDGPUDisassembler::decodeKernelDescriptorDirective( 1679 DataExtractor::Cursor &Cursor, ArrayRef<uint8_t> Bytes, 1680 raw_string_ostream &KdStream) const { 1681 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1682 do { \ 1683 KdStream << Indent << DIRECTIVE " " \ 1684 << ((TwoByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 1685 } while (0) 1686 1687 uint16_t TwoByteBuffer = 0; 1688 uint32_t FourByteBuffer = 0; 1689 1690 StringRef ReservedBytes; 1691 StringRef Indent = "\t"; 1692 1693 assert(Bytes.size() == 64); 1694 DataExtractor DE(Bytes, /*IsLittleEndian=*/true, /*AddressSize=*/8); 1695 1696 switch (Cursor.tell()) { 1697 case amdhsa::GROUP_SEGMENT_FIXED_SIZE_OFFSET: 1698 FourByteBuffer = DE.getU32(Cursor); 1699 KdStream << Indent << ".amdhsa_group_segment_fixed_size " << FourByteBuffer 1700 << '\n'; 1701 return MCDisassembler::Success; 1702 1703 case amdhsa::PRIVATE_SEGMENT_FIXED_SIZE_OFFSET: 1704 FourByteBuffer = DE.getU32(Cursor); 1705 KdStream << Indent << ".amdhsa_private_segment_fixed_size " 1706 << FourByteBuffer << '\n'; 1707 return MCDisassembler::Success; 1708 1709 case amdhsa::KERNARG_SIZE_OFFSET: 1710 FourByteBuffer = DE.getU32(Cursor); 1711 KdStream << Indent << ".amdhsa_kernarg_size " 1712 << FourByteBuffer << '\n'; 1713 return MCDisassembler::Success; 1714 1715 case amdhsa::RESERVED0_OFFSET: 1716 // 4 reserved bytes, must be 0. 1717 ReservedBytes = DE.getBytes(Cursor, 4); 1718 for (int I = 0; I < 4; ++I) { 1719 if (ReservedBytes[I] != 0) { 1720 return MCDisassembler::Fail; 1721 } 1722 } 1723 return MCDisassembler::Success; 1724 1725 case amdhsa::KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET: 1726 // KERNEL_CODE_ENTRY_BYTE_OFFSET 1727 // So far no directive controls this for Code Object V3, so simply skip for 1728 // disassembly. 1729 DE.skip(Cursor, 8); 1730 return MCDisassembler::Success; 1731 1732 case amdhsa::RESERVED1_OFFSET: 1733 // 20 reserved bytes, must be 0. 1734 ReservedBytes = DE.getBytes(Cursor, 20); 1735 for (int I = 0; I < 20; ++I) { 1736 if (ReservedBytes[I] != 0) { 1737 return MCDisassembler::Fail; 1738 } 1739 } 1740 return MCDisassembler::Success; 1741 1742 case amdhsa::COMPUTE_PGM_RSRC3_OFFSET: 1743 // COMPUTE_PGM_RSRC3 1744 // - Only set for GFX10, GFX6-9 have this to be 0. 1745 // - Currently no directives directly control this. 1746 FourByteBuffer = DE.getU32(Cursor); 1747 if (!isGFX10Plus() && FourByteBuffer) { 1748 return MCDisassembler::Fail; 1749 } 1750 return MCDisassembler::Success; 1751 1752 case amdhsa::COMPUTE_PGM_RSRC1_OFFSET: 1753 FourByteBuffer = DE.getU32(Cursor); 1754 if (decodeCOMPUTE_PGM_RSRC1(FourByteBuffer, KdStream) == 1755 MCDisassembler::Fail) { 1756 return MCDisassembler::Fail; 1757 } 1758 return MCDisassembler::Success; 1759 1760 case amdhsa::COMPUTE_PGM_RSRC2_OFFSET: 1761 FourByteBuffer = DE.getU32(Cursor); 1762 if (decodeCOMPUTE_PGM_RSRC2(FourByteBuffer, KdStream) == 1763 MCDisassembler::Fail) { 1764 return MCDisassembler::Fail; 1765 } 1766 return MCDisassembler::Success; 1767 1768 case amdhsa::KERNEL_CODE_PROPERTIES_OFFSET: 1769 using namespace amdhsa; 1770 TwoByteBuffer = DE.getU16(Cursor); 1771 1772 if (!hasArchitectedFlatScratch()) 1773 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_buffer", 1774 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); 1775 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_ptr", 1776 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); 1777 PRINT_DIRECTIVE(".amdhsa_user_sgpr_queue_ptr", 1778 KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); 1779 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_segment_ptr", 1780 KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); 1781 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_id", 1782 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); 1783 if (!hasArchitectedFlatScratch()) 1784 PRINT_DIRECTIVE(".amdhsa_user_sgpr_flat_scratch_init", 1785 KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); 1786 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_size", 1787 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); 1788 1789 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED0) 1790 return MCDisassembler::Fail; 1791 1792 // Reserved for GFX9 1793 if (isGFX9() && 1794 (TwoByteBuffer & KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32)) { 1795 return MCDisassembler::Fail; 1796 } else if (isGFX10Plus()) { 1797 PRINT_DIRECTIVE(".amdhsa_wavefront_size32", 1798 KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 1799 } 1800 1801 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED1) 1802 return MCDisassembler::Fail; 1803 1804 return MCDisassembler::Success; 1805 1806 case amdhsa::RESERVED2_OFFSET: 1807 // 6 bytes from here are reserved, must be 0. 1808 ReservedBytes = DE.getBytes(Cursor, 6); 1809 for (int I = 0; I < 6; ++I) { 1810 if (ReservedBytes[I] != 0) 1811 return MCDisassembler::Fail; 1812 } 1813 return MCDisassembler::Success; 1814 1815 default: 1816 llvm_unreachable("Unhandled index. Case statements cover everything."); 1817 return MCDisassembler::Fail; 1818 } 1819 #undef PRINT_DIRECTIVE 1820 } 1821 1822 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeKernelDescriptor( 1823 StringRef KdName, ArrayRef<uint8_t> Bytes, uint64_t KdAddress) const { 1824 // CP microcode requires the kernel descriptor to be 64 aligned. 1825 if (Bytes.size() != 64 || KdAddress % 64 != 0) 1826 return MCDisassembler::Fail; 1827 1828 std::string Kd; 1829 raw_string_ostream KdStream(Kd); 1830 KdStream << ".amdhsa_kernel " << KdName << '\n'; 1831 1832 DataExtractor::Cursor C(0); 1833 while (C && C.tell() < Bytes.size()) { 1834 MCDisassembler::DecodeStatus Status = 1835 decodeKernelDescriptorDirective(C, Bytes, KdStream); 1836 1837 cantFail(C.takeError()); 1838 1839 if (Status == MCDisassembler::Fail) 1840 return MCDisassembler::Fail; 1841 } 1842 KdStream << ".end_amdhsa_kernel\n"; 1843 outs() << KdStream.str(); 1844 return MCDisassembler::Success; 1845 } 1846 1847 Optional<MCDisassembler::DecodeStatus> 1848 AMDGPUDisassembler::onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, 1849 ArrayRef<uint8_t> Bytes, uint64_t Address, 1850 raw_ostream &CStream) const { 1851 // Right now only kernel descriptor needs to be handled. 1852 // We ignore all other symbols for target specific handling. 1853 // TODO: 1854 // Fix the spurious symbol issue for AMDGPU kernels. Exists for both Code 1855 // Object V2 and V3 when symbols are marked protected. 1856 1857 // amd_kernel_code_t for Code Object V2. 1858 if (Symbol.Type == ELF::STT_AMDGPU_HSA_KERNEL) { 1859 Size = 256; 1860 return MCDisassembler::Fail; 1861 } 1862 1863 // Code Object V3 kernel descriptors. 1864 StringRef Name = Symbol.Name; 1865 if (Symbol.Type == ELF::STT_OBJECT && Name.endswith(StringRef(".kd"))) { 1866 Size = 64; // Size = 64 regardless of success or failure. 1867 return decodeKernelDescriptor(Name.drop_back(3), Bytes, Address); 1868 } 1869 return None; 1870 } 1871 1872 //===----------------------------------------------------------------------===// 1873 // AMDGPUSymbolizer 1874 //===----------------------------------------------------------------------===// 1875 1876 // Try to find symbol name for specified label 1877 bool AMDGPUSymbolizer::tryAddingSymbolicOperand(MCInst &Inst, 1878 raw_ostream &/*cStream*/, int64_t Value, 1879 uint64_t /*Address*/, bool IsBranch, 1880 uint64_t /*Offset*/, uint64_t /*InstSize*/) { 1881 1882 if (!IsBranch) { 1883 return false; 1884 } 1885 1886 auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo); 1887 if (!Symbols) 1888 return false; 1889 1890 auto Result = llvm::find_if(*Symbols, [Value](const SymbolInfoTy &Val) { 1891 return Val.Addr == static_cast<uint64_t>(Value) && 1892 Val.Type == ELF::STT_NOTYPE; 1893 }); 1894 if (Result != Symbols->end()) { 1895 auto *Sym = Ctx.getOrCreateSymbol(Result->Name); 1896 const auto *Add = MCSymbolRefExpr::create(Sym, Ctx); 1897 Inst.addOperand(MCOperand::createExpr(Add)); 1898 return true; 1899 } 1900 // Add to list of referenced addresses, so caller can synthesize a label. 1901 ReferencedAddresses.push_back(static_cast<uint64_t>(Value)); 1902 return false; 1903 } 1904 1905 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream, 1906 int64_t Value, 1907 uint64_t Address) { 1908 llvm_unreachable("unimplemented"); 1909 } 1910 1911 //===----------------------------------------------------------------------===// 1912 // Initialization 1913 //===----------------------------------------------------------------------===// 1914 1915 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/, 1916 LLVMOpInfoCallback /*GetOpInfo*/, 1917 LLVMSymbolLookupCallback /*SymbolLookUp*/, 1918 void *DisInfo, 1919 MCContext *Ctx, 1920 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 1921 return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo); 1922 } 1923 1924 static MCDisassembler *createAMDGPUDisassembler(const Target &T, 1925 const MCSubtargetInfo &STI, 1926 MCContext &Ctx) { 1927 return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo()); 1928 } 1929 1930 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler() { 1931 TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(), 1932 createAMDGPUDisassembler); 1933 TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(), 1934 createAMDGPUSymbolizer); 1935 } 1936