1 //===-- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA --------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 //===----------------------------------------------------------------------===//
11 //
12 /// \file
13 ///
14 /// This file contains definition for AMDGPU ISA disassembler
15 //
16 //===----------------------------------------------------------------------===//
17 
18 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)?
19 
20 #include "AMDGPUDisassembler.h"
21 #include "AMDGPU.h"
22 #include "AMDGPURegisterInfo.h"
23 #include "SIDefines.h"
24 #include "Utils/AMDGPUBaseInfo.h"
25 
26 #include "llvm/MC/MCContext.h"
27 #include "llvm/MC/MCFixedLenDisassembler.h"
28 #include "llvm/MC/MCInst.h"
29 #include "llvm/MC/MCInstrDesc.h"
30 #include "llvm/MC/MCSubtargetInfo.h"
31 #include "llvm/Support/ELF.h"
32 #include "llvm/Support/Endian.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/TargetRegistry.h"
35 
36 
37 using namespace llvm;
38 
39 #define DEBUG_TYPE "amdgpu-disassembler"
40 
41 typedef llvm::MCDisassembler::DecodeStatus DecodeStatus;
42 
43 
44 inline static MCDisassembler::DecodeStatus
45 addOperand(MCInst &Inst, const MCOperand& Opnd) {
46   Inst.addOperand(Opnd);
47   return Opnd.isValid() ?
48     MCDisassembler::Success :
49     MCDisassembler::SoftFail;
50 }
51 
52 static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm,
53                                        uint64_t Addr, const void *Decoder) {
54   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
55 
56   APInt SignedOffset(18, Imm * 4, true);
57   int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue();
58 
59   if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2))
60     return MCDisassembler::Success;
61   return addOperand(Inst, MCOperand::createImm(Imm));
62 }
63 
64 #define DECODE_OPERAND2(RegClass, DecName) \
65 static DecodeStatus Decode##RegClass##RegisterClass(MCInst &Inst, \
66                                                     unsigned Imm, \
67                                                     uint64_t /*Addr*/, \
68                                                     const void *Decoder) { \
69   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); \
70   return addOperand(Inst, DAsm->decodeOperand_##DecName(Imm)); \
71 }
72 
73 #define DECODE_OPERAND(RegClass) DECODE_OPERAND2(RegClass, RegClass)
74 
75 DECODE_OPERAND(VGPR_32)
76 DECODE_OPERAND(VS_32)
77 DECODE_OPERAND(VS_64)
78 
79 DECODE_OPERAND(VReg_64)
80 DECODE_OPERAND(VReg_96)
81 DECODE_OPERAND(VReg_128)
82 
83 DECODE_OPERAND(SReg_32)
84 DECODE_OPERAND(SReg_32_XM0)
85 DECODE_OPERAND(SReg_64)
86 DECODE_OPERAND(SReg_128)
87 DECODE_OPERAND(SReg_256)
88 DECODE_OPERAND(SReg_512)
89 
90 #define GET_SUBTARGETINFO_ENUM
91 #include "AMDGPUGenSubtargetInfo.inc"
92 #undef GET_SUBTARGETINFO_ENUM
93 
94 #include "AMDGPUGenDisassemblerTables.inc"
95 
96 //===----------------------------------------------------------------------===//
97 //
98 //===----------------------------------------------------------------------===//
99 
100 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) {
101   assert(Bytes.size() >= sizeof(T));
102   const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data());
103   Bytes = Bytes.slice(sizeof(T));
104   return Res;
105 }
106 
107 DecodeStatus AMDGPUDisassembler::tryDecodeInst(const uint8_t* Table,
108                                                MCInst &MI,
109                                                uint64_t Inst,
110                                                uint64_t Address) const {
111   assert(MI.getOpcode() == 0);
112   assert(MI.getNumOperands() == 0);
113   MCInst TmpInst;
114   const auto SavedBytes = Bytes;
115   if (decodeInstruction(Table, TmpInst, Inst, Address, this, STI)) {
116     MI = TmpInst;
117     return MCDisassembler::Success;
118   }
119   Bytes = SavedBytes;
120   return MCDisassembler::Fail;
121 }
122 
123 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
124                                                 ArrayRef<uint8_t> Bytes_,
125                                                 uint64_t Address,
126                                                 raw_ostream &WS,
127                                                 raw_ostream &CS) const {
128   CommentStream = &CS;
129 
130   // ToDo: AMDGPUDisassembler supports only VI ISA.
131   assert(AMDGPU::isVI(STI) && "Can disassemble only VI ISA.");
132 
133   const unsigned MaxInstBytesNum = (std::min)((size_t)8, Bytes_.size());
134   Bytes = Bytes_.slice(0, MaxInstBytesNum);
135 
136   DecodeStatus Res = MCDisassembler::Fail;
137   do {
138     // ToDo: better to switch encoding length using some bit predicate
139     // but it is unknown yet, so try all we can
140 
141     // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2
142     // encodings
143     if (Bytes.size() >= 8) {
144       const uint64_t QW = eatBytes<uint64_t>(Bytes);
145       Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address);
146       if (Res) break;
147 
148       Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address);
149       if (Res) break;
150     }
151 
152     // Reinitialize Bytes as DPP64 could have eaten too much
153     Bytes = Bytes_.slice(0, MaxInstBytesNum);
154 
155     // Try decode 32-bit instruction
156     if (Bytes.size() < 4) break;
157     const uint32_t DW = eatBytes<uint32_t>(Bytes);
158     Res = tryDecodeInst(DecoderTableVI32, MI, DW, Address);
159     if (Res) break;
160 
161     Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address);
162     if (Res) break;
163 
164     if (Bytes.size() < 4) break;
165     const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW;
166     Res = tryDecodeInst(DecoderTableVI64, MI, QW, Address);
167     if (Res) break;
168 
169     Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address);
170   } while (false);
171 
172   Size = Res ? (MaxInstBytesNum - Bytes.size()) : 0;
173   return Res;
174 }
175 
176 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const {
177   return getContext().getRegisterInfo()->
178     getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]);
179 }
180 
181 inline
182 MCOperand AMDGPUDisassembler::errOperand(unsigned V,
183                                          const Twine& ErrMsg) const {
184   *CommentStream << "Error: " + ErrMsg;
185 
186   // ToDo: add support for error operands to MCInst.h
187   // return MCOperand::createError(V);
188   return MCOperand();
189 }
190 
191 inline
192 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const {
193   return MCOperand::createReg(RegId);
194 }
195 
196 inline
197 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID,
198                                                unsigned Val) const {
199   const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID];
200   if (Val >= RegCl.getNumRegs())
201     return errOperand(Val, Twine(getRegClassName(RegClassID)) +
202                            ": unknown register " + Twine(Val));
203   return createRegOperand(RegCl.getRegister(Val));
204 }
205 
206 inline
207 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID,
208                                                 unsigned Val) const {
209   // ToDo: SI/CI have 104 SGPRs, VI - 102
210   // Valery: here we accepting as much as we can, let assembler sort it out
211   int shift = 0;
212   switch (SRegClassID) {
213   case AMDGPU::SGPR_32RegClassID:
214   case AMDGPU::TTMP_32RegClassID:
215     break;
216   case AMDGPU::SGPR_64RegClassID:
217   case AMDGPU::TTMP_64RegClassID:
218     shift = 1;
219     break;
220   case AMDGPU::SGPR_128RegClassID:
221   case AMDGPU::TTMP_128RegClassID:
222   // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in
223   // this bundle?
224   case AMDGPU::SReg_256RegClassID:
225   // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in
226   // this bundle?
227   case AMDGPU::SReg_512RegClassID:
228     shift = 2;
229     break;
230   // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in
231   // this bundle?
232   default:
233     llvm_unreachable("unhandled register class");
234   }
235 
236   if (Val % (1 << shift)) {
237     *CommentStream << "Warning: " << getRegClassName(SRegClassID)
238                    << ": scalar reg isn't aligned " << Val;
239   }
240 
241   return createRegOperand(SRegClassID, Val >> shift);
242 }
243 
244 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const {
245   return decodeSrcOp(OPW32, Val);
246 }
247 
248 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const {
249   return decodeSrcOp(OPW64, Val);
250 }
251 
252 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const {
253   // Some instructions have operand restrictions beyond what the encoding
254   // allows. Some ordinarily VSrc_32 operands are VGPR_32, so clear the extra
255   // high bit.
256   Val &= 255;
257 
258   return createRegOperand(AMDGPU::VGPR_32RegClassID, Val);
259 }
260 
261 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const {
262   return createRegOperand(AMDGPU::VReg_64RegClassID, Val);
263 }
264 
265 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const {
266   return createRegOperand(AMDGPU::VReg_96RegClassID, Val);
267 }
268 
269 MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const {
270   return createRegOperand(AMDGPU::VReg_128RegClassID, Val);
271 }
272 
273 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const {
274   // table-gen generated disassembler doesn't care about operand types
275   // leaving only registry class so SSrc_32 operand turns into SReg_32
276   // and therefore we accept immediates and literals here as well
277   return decodeSrcOp(OPW32, Val);
278 }
279 
280 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0(unsigned Val) const {
281   // SReg_32_XM0 is SReg_32 without M0
282   return decodeOperand_SReg_32(Val);
283 }
284 
285 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const {
286   // see decodeOperand_SReg_32 comment
287   return decodeSrcOp(OPW64, Val);
288 }
289 
290 MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const {
291   return decodeSrcOp(OPW128, Val);
292 }
293 
294 MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const {
295   return createSRegOperand(AMDGPU::SReg_256RegClassID, Val);
296 }
297 
298 MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const {
299   return createSRegOperand(AMDGPU::SReg_512RegClassID, Val);
300 }
301 
302 
303 MCOperand AMDGPUDisassembler::decodeLiteralConstant() const {
304   // For now all literal constants are supposed to be unsigned integer
305   // ToDo: deal with signed/unsigned 64-bit integer constants
306   // ToDo: deal with float/double constants
307   if (Bytes.size() < 4)
308     return errOperand(0, "cannot read literal, inst bytes left " +
309                          Twine(Bytes.size()));
310   return MCOperand::createImm(eatBytes<uint32_t>(Bytes));
311 }
312 
313 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) {
314   using namespace AMDGPU::EncValues;
315   assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX);
316   return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ?
317     (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) :
318     (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm)));
319       // Cast prevents negative overflow.
320 }
321 
322 MCOperand AMDGPUDisassembler::decodeFPImmed(bool Is32, unsigned Imm) {
323   assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN
324       && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX);
325   // ToDo: case 248: 1/(2*PI) - is allowed only on VI
326   // ToDo: AMDGPUInstPrinter does not support 1/(2*PI). It consider 1/(2*PI) as
327   // literal constant.
328   float V = 0.0f;
329   switch (Imm) {
330   case 240: V =  0.5f; break;
331   case 241: V = -0.5f; break;
332   case 242: V =  1.0f; break;
333   case 243: V = -1.0f; break;
334   case 244: V =  2.0f; break;
335   case 245: V = -2.0f; break;
336   case 246: V =  4.0f; break;
337   case 247: V = -4.0f; break;
338   case 248: return MCOperand::createImm(Is32 ?         // 1/(2*PI)
339                                           0x3e22f983 :
340                                           0x3fc45f306dc9c882);
341   default: break;
342   }
343   return MCOperand::createImm(Is32? FloatToBits(V) : DoubleToBits(V));
344 }
345 
346 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const {
347   using namespace AMDGPU;
348   assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
349   switch (Width) {
350   default: // fall
351   case OPW32: return VGPR_32RegClassID;
352   case OPW64: return VReg_64RegClassID;
353   case OPW128: return VReg_128RegClassID;
354   }
355 }
356 
357 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const {
358   using namespace AMDGPU;
359   assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
360   switch (Width) {
361   default: // fall
362   case OPW32: return SGPR_32RegClassID;
363   case OPW64: return SGPR_64RegClassID;
364   case OPW128: return SGPR_128RegClassID;
365   }
366 }
367 
368 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const {
369   using namespace AMDGPU;
370   assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
371   switch (Width) {
372   default: // fall
373   case OPW32: return TTMP_32RegClassID;
374   case OPW64: return TTMP_64RegClassID;
375   case OPW128: return TTMP_128RegClassID;
376   }
377 }
378 
379 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val) const {
380   using namespace AMDGPU::EncValues;
381   assert(Val < 512); // enum9
382 
383   if (VGPR_MIN <= Val && Val <= VGPR_MAX) {
384     return createRegOperand(getVgprClassId(Width), Val - VGPR_MIN);
385   }
386   if (Val <= SGPR_MAX) {
387     assert(SGPR_MIN == 0); // "SGPR_MIN <= Val" is always true and causes compilation warning.
388     return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN);
389   }
390   if (TTMP_MIN <= Val && Val <= TTMP_MAX) {
391     return createSRegOperand(getTtmpClassId(Width), Val - TTMP_MIN);
392   }
393 
394   assert(Width == OPW32 || Width == OPW64);
395   const bool Is32 = (Width == OPW32);
396 
397   if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX)
398     return decodeIntImmed(Val);
399 
400   if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX)
401     return decodeFPImmed(Is32, Val);
402 
403   if (Val == LITERAL_CONST)
404     return decodeLiteralConstant();
405 
406   return Is32 ? decodeSpecialReg32(Val) : decodeSpecialReg64(Val);
407 }
408 
409 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const {
410   using namespace AMDGPU;
411   switch (Val) {
412   case 102: return createRegOperand(getMCReg(FLAT_SCR_LO, STI));
413   case 103: return createRegOperand(getMCReg(FLAT_SCR_HI, STI));
414     // ToDo: no support for xnack_mask_lo/_hi register
415   case 104:
416   case 105: break;
417   case 106: return createRegOperand(VCC_LO);
418   case 107: return createRegOperand(VCC_HI);
419   case 108: return createRegOperand(TBA_LO);
420   case 109: return createRegOperand(TBA_HI);
421   case 110: return createRegOperand(TMA_LO);
422   case 111: return createRegOperand(TMA_HI);
423   case 124: return createRegOperand(M0);
424   case 126: return createRegOperand(EXEC_LO);
425   case 127: return createRegOperand(EXEC_HI);
426     // ToDo: no support for vccz register
427   case 251: break;
428     // ToDo: no support for execz register
429   case 252: break;
430   case 253: return createRegOperand(SCC);
431   default: break;
432   }
433   return errOperand(Val, "unknown operand encoding " + Twine(Val));
434 }
435 
436 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const {
437   using namespace AMDGPU;
438   switch (Val) {
439   case 102: return createRegOperand(getMCReg(FLAT_SCR, STI));
440   case 106: return createRegOperand(VCC);
441   case 108: return createRegOperand(TBA);
442   case 110: return createRegOperand(TMA);
443   case 126: return createRegOperand(EXEC);
444   default: break;
445   }
446   return errOperand(Val, "unknown operand encoding " + Twine(Val));
447 }
448 
449 //===----------------------------------------------------------------------===//
450 // AMDGPUSymbolizer
451 //===----------------------------------------------------------------------===//
452 
453 // Try to find symbol name for specified label
454 bool AMDGPUSymbolizer::tryAddingSymbolicOperand(MCInst &Inst,
455                                 raw_ostream &/*cStream*/, int64_t Value,
456                                 uint64_t /*Address*/, bool IsBranch,
457                                 uint64_t /*Offset*/, uint64_t /*InstSize*/) {
458   typedef std::tuple<uint64_t, StringRef, uint8_t> SymbolInfoTy;
459   typedef std::vector<SymbolInfoTy> SectionSymbolsTy;
460 
461   if (!IsBranch) {
462     return false;
463   }
464 
465   auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo);
466   auto Result = std::find_if(Symbols->begin(), Symbols->end(),
467                              [Value](const SymbolInfoTy& Val) {
468                                 return std::get<0>(Val) == static_cast<uint64_t>(Value)
469                                     && std::get<2>(Val) == ELF::STT_NOTYPE;
470                              });
471   if (Result != Symbols->end()) {
472     auto *Sym = Ctx.getOrCreateSymbol(std::get<1>(*Result));
473     const auto *Add = MCSymbolRefExpr::create(Sym, Ctx);
474     Inst.addOperand(MCOperand::createExpr(Add));
475     return true;
476   }
477   return false;
478 }
479 
480 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream,
481                                                        int64_t Value,
482                                                        uint64_t Address) {
483   llvm_unreachable("unimplemented");
484 }
485 
486 //===----------------------------------------------------------------------===//
487 // Initialization
488 //===----------------------------------------------------------------------===//
489 
490 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/,
491                               LLVMOpInfoCallback /*GetOpInfo*/,
492                               LLVMSymbolLookupCallback /*SymbolLookUp*/,
493                               void *DisInfo,
494                               MCContext *Ctx,
495                               std::unique_ptr<MCRelocationInfo> &&RelInfo) {
496   return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo);
497 }
498 
499 static MCDisassembler *createAMDGPUDisassembler(const Target &T,
500                                                 const MCSubtargetInfo &STI,
501                                                 MCContext &Ctx) {
502   return new AMDGPUDisassembler(STI, Ctx);
503 }
504 
505 extern "C" void LLVMInitializeAMDGPUDisassembler() {
506   TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(),
507                                          createAMDGPUDisassembler);
508   TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(),
509                                        createAMDGPUSymbolizer);
510 }
511