1 //===-- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA --------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 //===----------------------------------------------------------------------===//
11 //
12 /// \file
13 ///
14 /// This file contains definition for AMDGPU ISA disassembler
15 //
16 //===----------------------------------------------------------------------===//
17 
18 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)?
19 
20 #include "AMDGPUDisassembler.h"
21 #include "AMDGPU.h"
22 #include "AMDGPURegisterInfo.h"
23 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
24 #include "SIDefines.h"
25 #include "Utils/AMDGPUBaseInfo.h"
26 
27 #include "llvm/BinaryFormat/ELF.h"
28 #include "llvm/MC/MCContext.h"
29 #include "llvm/MC/MCFixedLenDisassembler.h"
30 #include "llvm/MC/MCInst.h"
31 #include "llvm/MC/MCInstrDesc.h"
32 #include "llvm/MC/MCSubtargetInfo.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/Endian.h"
35 #include "llvm/Support/TargetRegistry.h"
36 
37 using namespace llvm;
38 
39 #define DEBUG_TYPE "amdgpu-disassembler"
40 
41 typedef llvm::MCDisassembler::DecodeStatus DecodeStatus;
42 
43 
44 inline static MCDisassembler::DecodeStatus
45 addOperand(MCInst &Inst, const MCOperand& Opnd) {
46   Inst.addOperand(Opnd);
47   return Opnd.isValid() ?
48     MCDisassembler::Success :
49     MCDisassembler::SoftFail;
50 }
51 
52 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op,
53                                 uint16_t NameIdx) {
54   int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx);
55   if (OpIdx != -1) {
56     auto I = MI.begin();
57     std::advance(I, OpIdx);
58     MI.insert(I, Op);
59   }
60   return OpIdx;
61 }
62 
63 static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm,
64                                        uint64_t Addr, const void *Decoder) {
65   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
66 
67   APInt SignedOffset(18, Imm * 4, true);
68   int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue();
69 
70   if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2))
71     return MCDisassembler::Success;
72   return addOperand(Inst, MCOperand::createImm(Imm));
73 }
74 
75 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \
76 static DecodeStatus StaticDecoderName(MCInst &Inst, \
77                                        unsigned Imm, \
78                                        uint64_t /*Addr*/, \
79                                        const void *Decoder) { \
80   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); \
81   return addOperand(Inst, DAsm->DecoderName(Imm)); \
82 }
83 
84 #define DECODE_OPERAND_REG(RegClass) \
85 DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass)
86 
87 DECODE_OPERAND_REG(VGPR_32)
88 DECODE_OPERAND_REG(VS_32)
89 DECODE_OPERAND_REG(VS_64)
90 DECODE_OPERAND_REG(VS_128)
91 
92 DECODE_OPERAND_REG(VReg_64)
93 DECODE_OPERAND_REG(VReg_96)
94 DECODE_OPERAND_REG(VReg_128)
95 
96 DECODE_OPERAND_REG(SReg_32)
97 DECODE_OPERAND_REG(SReg_32_XM0_XEXEC)
98 DECODE_OPERAND_REG(SReg_32_XEXEC_HI)
99 DECODE_OPERAND_REG(SReg_64)
100 DECODE_OPERAND_REG(SReg_64_XEXEC)
101 DECODE_OPERAND_REG(SReg_128)
102 DECODE_OPERAND_REG(SReg_256)
103 DECODE_OPERAND_REG(SReg_512)
104 
105 
106 static DecodeStatus decodeOperand_VSrc16(MCInst &Inst,
107                                          unsigned Imm,
108                                          uint64_t Addr,
109                                          const void *Decoder) {
110   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
111   return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm));
112 }
113 
114 static DecodeStatus decodeOperand_VSrcV216(MCInst &Inst,
115                                          unsigned Imm,
116                                          uint64_t Addr,
117                                          const void *Decoder) {
118   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
119   return addOperand(Inst, DAsm->decodeOperand_VSrcV216(Imm));
120 }
121 
122 #define DECODE_SDWA(DecName) \
123 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName)
124 
125 DECODE_SDWA(Src32)
126 DECODE_SDWA(Src16)
127 DECODE_SDWA(VopcDst)
128 
129 #include "AMDGPUGenDisassemblerTables.inc"
130 
131 //===----------------------------------------------------------------------===//
132 //
133 //===----------------------------------------------------------------------===//
134 
135 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) {
136   assert(Bytes.size() >= sizeof(T));
137   const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data());
138   Bytes = Bytes.slice(sizeof(T));
139   return Res;
140 }
141 
142 DecodeStatus AMDGPUDisassembler::tryDecodeInst(const uint8_t* Table,
143                                                MCInst &MI,
144                                                uint64_t Inst,
145                                                uint64_t Address) const {
146   assert(MI.getOpcode() == 0);
147   assert(MI.getNumOperands() == 0);
148   MCInst TmpInst;
149   HasLiteral = false;
150   const auto SavedBytes = Bytes;
151   if (decodeInstruction(Table, TmpInst, Inst, Address, this, STI)) {
152     MI = TmpInst;
153     return MCDisassembler::Success;
154   }
155   Bytes = SavedBytes;
156   return MCDisassembler::Fail;
157 }
158 
159 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
160                                                 ArrayRef<uint8_t> Bytes_,
161                                                 uint64_t Address,
162                                                 raw_ostream &WS,
163                                                 raw_ostream &CS) const {
164   CommentStream = &CS;
165   bool IsSDWA = false;
166 
167   // ToDo: AMDGPUDisassembler supports only VI ISA.
168   if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding])
169     report_fatal_error("Disassembly not yet supported for subtarget");
170 
171   const unsigned MaxInstBytesNum = (std::min)((size_t)8, Bytes_.size());
172   Bytes = Bytes_.slice(0, MaxInstBytesNum);
173 
174   DecodeStatus Res = MCDisassembler::Fail;
175   do {
176     // ToDo: better to switch encoding length using some bit predicate
177     // but it is unknown yet, so try all we can
178 
179     // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2
180     // encodings
181     if (Bytes.size() >= 8) {
182       const uint64_t QW = eatBytes<uint64_t>(Bytes);
183       Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address);
184       if (Res) break;
185 
186       Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address);
187       if (Res) { IsSDWA = true;  break; }
188 
189       Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address);
190       if (Res) { IsSDWA = true;  break; }
191     }
192 
193     // Reinitialize Bytes as DPP64 could have eaten too much
194     Bytes = Bytes_.slice(0, MaxInstBytesNum);
195 
196     // Try decode 32-bit instruction
197     if (Bytes.size() < 4) break;
198     const uint32_t DW = eatBytes<uint32_t>(Bytes);
199     Res = tryDecodeInst(DecoderTableVI32, MI, DW, Address);
200     if (Res) break;
201 
202     Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address);
203     if (Res) break;
204 
205     if (Bytes.size() < 4) break;
206     const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW;
207     Res = tryDecodeInst(DecoderTableVI64, MI, QW, Address);
208     if (Res) break;
209 
210     Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address);
211   } while (false);
212 
213   if (Res && (MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi ||
214               MI.getOpcode() == AMDGPU::V_MAC_F32_e64_si ||
215               MI.getOpcode() == AMDGPU::V_MAC_F16_e64_vi)) {
216     // Insert dummy unused src2_modifiers.
217     insertNamedMCOperand(MI, MCOperand::createImm(0),
218                          AMDGPU::OpName::src2_modifiers);
219   }
220 
221   if (Res && IsSDWA)
222     Res = convertSDWAInst(MI);
223 
224   Size = Res ? (MaxInstBytesNum - Bytes.size()) : 0;
225   return Res;
226 }
227 
228 DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const {
229   if (STI.getFeatureBits()[AMDGPU::FeatureGFX9]) {
230     if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst) != -1)
231       // VOPC - insert clamp
232       insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp);
233   } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) {
234     int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst);
235     if (SDst != -1) {
236       // VOPC - insert VCC register as sdst
237       insertNamedMCOperand(MI, MCOperand::createReg(AMDGPU::VCC),
238                            AMDGPU::OpName::sdst);
239     } else {
240       // VOP1/2 - insert omod if present in instruction
241       insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod);
242     }
243   }
244   return MCDisassembler::Success;
245 }
246 
247 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const {
248   return getContext().getRegisterInfo()->
249     getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]);
250 }
251 
252 inline
253 MCOperand AMDGPUDisassembler::errOperand(unsigned V,
254                                          const Twine& ErrMsg) const {
255   *CommentStream << "Error: " + ErrMsg;
256 
257   // ToDo: add support for error operands to MCInst.h
258   // return MCOperand::createError(V);
259   return MCOperand();
260 }
261 
262 inline
263 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const {
264   return MCOperand::createReg(RegId);
265 }
266 
267 inline
268 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID,
269                                                unsigned Val) const {
270   const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID];
271   if (Val >= RegCl.getNumRegs())
272     return errOperand(Val, Twine(getRegClassName(RegClassID)) +
273                            ": unknown register " + Twine(Val));
274   return createRegOperand(RegCl.getRegister(Val));
275 }
276 
277 inline
278 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID,
279                                                 unsigned Val) const {
280   // ToDo: SI/CI have 104 SGPRs, VI - 102
281   // Valery: here we accepting as much as we can, let assembler sort it out
282   int shift = 0;
283   switch (SRegClassID) {
284   case AMDGPU::SGPR_32RegClassID:
285   case AMDGPU::TTMP_32RegClassID:
286     break;
287   case AMDGPU::SGPR_64RegClassID:
288   case AMDGPU::TTMP_64RegClassID:
289     shift = 1;
290     break;
291   case AMDGPU::SGPR_128RegClassID:
292   case AMDGPU::TTMP_128RegClassID:
293   // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in
294   // this bundle?
295   case AMDGPU::SReg_256RegClassID:
296   // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in
297   // this bundle?
298   case AMDGPU::SReg_512RegClassID:
299     shift = 2;
300     break;
301   // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in
302   // this bundle?
303   default:
304     llvm_unreachable("unhandled register class");
305   }
306 
307   if (Val % (1 << shift)) {
308     *CommentStream << "Warning: " << getRegClassName(SRegClassID)
309                    << ": scalar reg isn't aligned " << Val;
310   }
311 
312   return createRegOperand(SRegClassID, Val >> shift);
313 }
314 
315 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const {
316   return decodeSrcOp(OPW32, Val);
317 }
318 
319 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const {
320   return decodeSrcOp(OPW64, Val);
321 }
322 
323 MCOperand AMDGPUDisassembler::decodeOperand_VS_128(unsigned Val) const {
324   return decodeSrcOp(OPW128, Val);
325 }
326 
327 MCOperand AMDGPUDisassembler::decodeOperand_VSrc16(unsigned Val) const {
328   return decodeSrcOp(OPW16, Val);
329 }
330 
331 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV216(unsigned Val) const {
332   return decodeSrcOp(OPWV216, Val);
333 }
334 
335 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const {
336   // Some instructions have operand restrictions beyond what the encoding
337   // allows. Some ordinarily VSrc_32 operands are VGPR_32, so clear the extra
338   // high bit.
339   Val &= 255;
340 
341   return createRegOperand(AMDGPU::VGPR_32RegClassID, Val);
342 }
343 
344 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const {
345   return createRegOperand(AMDGPU::VReg_64RegClassID, Val);
346 }
347 
348 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const {
349   return createRegOperand(AMDGPU::VReg_96RegClassID, Val);
350 }
351 
352 MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const {
353   return createRegOperand(AMDGPU::VReg_128RegClassID, Val);
354 }
355 
356 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const {
357   // table-gen generated disassembler doesn't care about operand types
358   // leaving only registry class so SSrc_32 operand turns into SReg_32
359   // and therefore we accept immediates and literals here as well
360   return decodeSrcOp(OPW32, Val);
361 }
362 
363 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0_XEXEC(
364   unsigned Val) const {
365   // SReg_32_XM0 is SReg_32 without M0 or EXEC_LO/EXEC_HI
366   return decodeOperand_SReg_32(Val);
367 }
368 
369 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XEXEC_HI(
370   unsigned Val) const {
371   // SReg_32_XM0 is SReg_32 without EXEC_HI
372   return decodeOperand_SReg_32(Val);
373 }
374 
375 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const {
376   return decodeSrcOp(OPW64, Val);
377 }
378 
379 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64_XEXEC(unsigned Val) const {
380   return decodeSrcOp(OPW64, Val);
381 }
382 
383 MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const {
384   return decodeSrcOp(OPW128, Val);
385 }
386 
387 MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const {
388   return createSRegOperand(AMDGPU::SReg_256RegClassID, Val);
389 }
390 
391 MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const {
392   return createSRegOperand(AMDGPU::SReg_512RegClassID, Val);
393 }
394 
395 
396 MCOperand AMDGPUDisassembler::decodeLiteralConstant() const {
397   // For now all literal constants are supposed to be unsigned integer
398   // ToDo: deal with signed/unsigned 64-bit integer constants
399   // ToDo: deal with float/double constants
400   if (!HasLiteral) {
401     if (Bytes.size() < 4) {
402       return errOperand(0, "cannot read literal, inst bytes left " +
403                         Twine(Bytes.size()));
404     }
405     HasLiteral = true;
406     Literal = eatBytes<uint32_t>(Bytes);
407   }
408   return MCOperand::createImm(Literal);
409 }
410 
411 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) {
412   using namespace AMDGPU::EncValues;
413   assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX);
414   return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ?
415     (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) :
416     (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm)));
417       // Cast prevents negative overflow.
418 }
419 
420 static int64_t getInlineImmVal32(unsigned Imm) {
421   switch (Imm) {
422   case 240:
423     return FloatToBits(0.5f);
424   case 241:
425     return FloatToBits(-0.5f);
426   case 242:
427     return FloatToBits(1.0f);
428   case 243:
429     return FloatToBits(-1.0f);
430   case 244:
431     return FloatToBits(2.0f);
432   case 245:
433     return FloatToBits(-2.0f);
434   case 246:
435     return FloatToBits(4.0f);
436   case 247:
437     return FloatToBits(-4.0f);
438   case 248: // 1 / (2 * PI)
439     return 0x3e22f983;
440   default:
441     llvm_unreachable("invalid fp inline imm");
442   }
443 }
444 
445 static int64_t getInlineImmVal64(unsigned Imm) {
446   switch (Imm) {
447   case 240:
448     return DoubleToBits(0.5);
449   case 241:
450     return DoubleToBits(-0.5);
451   case 242:
452     return DoubleToBits(1.0);
453   case 243:
454     return DoubleToBits(-1.0);
455   case 244:
456     return DoubleToBits(2.0);
457   case 245:
458     return DoubleToBits(-2.0);
459   case 246:
460     return DoubleToBits(4.0);
461   case 247:
462     return DoubleToBits(-4.0);
463   case 248: // 1 / (2 * PI)
464     return 0x3fc45f306dc9c882;
465   default:
466     llvm_unreachable("invalid fp inline imm");
467   }
468 }
469 
470 static int64_t getInlineImmVal16(unsigned Imm) {
471   switch (Imm) {
472   case 240:
473     return 0x3800;
474   case 241:
475     return 0xB800;
476   case 242:
477     return 0x3C00;
478   case 243:
479     return 0xBC00;
480   case 244:
481     return 0x4000;
482   case 245:
483     return 0xC000;
484   case 246:
485     return 0x4400;
486   case 247:
487     return 0xC400;
488   case 248: // 1 / (2 * PI)
489     return 0x3118;
490   default:
491     llvm_unreachable("invalid fp inline imm");
492   }
493 }
494 
495 MCOperand AMDGPUDisassembler::decodeFPImmed(OpWidthTy Width, unsigned Imm) {
496   assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN
497       && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX);
498 
499   // ToDo: case 248: 1/(2*PI) - is allowed only on VI
500   switch (Width) {
501   case OPW32:
502     return MCOperand::createImm(getInlineImmVal32(Imm));
503   case OPW64:
504     return MCOperand::createImm(getInlineImmVal64(Imm));
505   case OPW16:
506   case OPWV216:
507     return MCOperand::createImm(getInlineImmVal16(Imm));
508   default:
509     llvm_unreachable("implement me");
510   }
511 }
512 
513 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const {
514   using namespace AMDGPU;
515   assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
516   switch (Width) {
517   default: // fall
518   case OPW32:
519   case OPW16:
520   case OPWV216:
521     return VGPR_32RegClassID;
522   case OPW64: return VReg_64RegClassID;
523   case OPW128: return VReg_128RegClassID;
524   }
525 }
526 
527 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const {
528   using namespace AMDGPU;
529   assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
530   switch (Width) {
531   default: // fall
532   case OPW32:
533   case OPW16:
534   case OPWV216:
535     return SGPR_32RegClassID;
536   case OPW64: return SGPR_64RegClassID;
537   case OPW128: return SGPR_128RegClassID;
538   }
539 }
540 
541 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const {
542   using namespace AMDGPU;
543   assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
544   switch (Width) {
545   default: // fall
546   case OPW32:
547   case OPW16:
548   case OPWV216:
549     return TTMP_32RegClassID;
550   case OPW64: return TTMP_64RegClassID;
551   case OPW128: return TTMP_128RegClassID;
552   }
553 }
554 
555 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val) const {
556   using namespace AMDGPU::EncValues;
557   assert(Val < 512); // enum9
558 
559   if (VGPR_MIN <= Val && Val <= VGPR_MAX) {
560     return createRegOperand(getVgprClassId(Width), Val - VGPR_MIN);
561   }
562   if (Val <= SGPR_MAX) {
563     assert(SGPR_MIN == 0); // "SGPR_MIN <= Val" is always true and causes compilation warning.
564     return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN);
565   }
566   if (TTMP_MIN <= Val && Val <= TTMP_MAX) {
567     return createSRegOperand(getTtmpClassId(Width), Val - TTMP_MIN);
568   }
569 
570   if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX)
571     return decodeIntImmed(Val);
572 
573   if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX)
574     return decodeFPImmed(Width, Val);
575 
576   if (Val == LITERAL_CONST)
577     return decodeLiteralConstant();
578 
579   switch (Width) {
580   case OPW32:
581   case OPW16:
582   case OPWV216:
583     return decodeSpecialReg32(Val);
584   case OPW64:
585     return decodeSpecialReg64(Val);
586   default:
587     llvm_unreachable("unexpected immediate type");
588   }
589 }
590 
591 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const {
592   using namespace AMDGPU;
593   switch (Val) {
594   case 102: return createRegOperand(getMCReg(FLAT_SCR_LO, STI));
595   case 103: return createRegOperand(getMCReg(FLAT_SCR_HI, STI));
596     // ToDo: no support for xnack_mask_lo/_hi register
597   case 104:
598   case 105: break;
599   case 106: return createRegOperand(VCC_LO);
600   case 107: return createRegOperand(VCC_HI);
601   case 108: return createRegOperand(TBA_LO);
602   case 109: return createRegOperand(TBA_HI);
603   case 110: return createRegOperand(TMA_LO);
604   case 111: return createRegOperand(TMA_HI);
605   case 124: return createRegOperand(M0);
606   case 126: return createRegOperand(EXEC_LO);
607   case 127: return createRegOperand(EXEC_HI);
608   case 235: return createRegOperand(SRC_SHARED_BASE);
609   case 236: return createRegOperand(SRC_SHARED_LIMIT);
610   case 237: return createRegOperand(SRC_PRIVATE_BASE);
611   case 238: return createRegOperand(SRC_PRIVATE_LIMIT);
612     // TODO: SRC_POPS_EXITING_WAVE_ID
613     // ToDo: no support for vccz register
614   case 251: break;
615     // ToDo: no support for execz register
616   case 252: break;
617   case 253: return createRegOperand(SCC);
618   default: break;
619   }
620   return errOperand(Val, "unknown operand encoding " + Twine(Val));
621 }
622 
623 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const {
624   using namespace AMDGPU;
625   switch (Val) {
626   case 102: return createRegOperand(getMCReg(FLAT_SCR, STI));
627   case 106: return createRegOperand(VCC);
628   case 108: return createRegOperand(TBA);
629   case 110: return createRegOperand(TMA);
630   case 126: return createRegOperand(EXEC);
631   default: break;
632   }
633   return errOperand(Val, "unknown operand encoding " + Twine(Val));
634 }
635 
636 MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width,
637                                             unsigned Val) const {
638   using namespace AMDGPU::SDWA;
639 
640   if (STI.getFeatureBits()[AMDGPU::FeatureGFX9]) {
641     // XXX: static_cast<int> is needed to avoid stupid warning:
642     // compare with unsigned is always true
643     if (SDWA9EncValues::SRC_VGPR_MIN <= static_cast<int>(Val) &&
644         Val <= SDWA9EncValues::SRC_VGPR_MAX) {
645       return createRegOperand(getVgprClassId(Width),
646                               Val - SDWA9EncValues::SRC_VGPR_MIN);
647     }
648     if (SDWA9EncValues::SRC_SGPR_MIN <= Val &&
649         Val <= SDWA9EncValues::SRC_SGPR_MAX) {
650       return createSRegOperand(getSgprClassId(Width),
651                                Val - SDWA9EncValues::SRC_SGPR_MIN);
652     }
653 
654     return decodeSpecialReg32(Val - SDWA9EncValues::SRC_SGPR_MIN);
655   } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) {
656     return createRegOperand(getVgprClassId(Width), Val);
657   }
658   llvm_unreachable("unsupported target");
659 }
660 
661 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const {
662   return decodeSDWASrc(OPW16, Val);
663 }
664 
665 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const {
666   return decodeSDWASrc(OPW32, Val);
667 }
668 
669 
670 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const {
671   using namespace AMDGPU::SDWA;
672 
673   assert(STI.getFeatureBits()[AMDGPU::FeatureGFX9] &&
674          "SDWAVopcDst should be present only on GFX9");
675   if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) {
676     Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK;
677     if (Val > AMDGPU::EncValues::SGPR_MAX) {
678       return decodeSpecialReg64(Val);
679     } else {
680       return createSRegOperand(getSgprClassId(OPW64), Val);
681     }
682   } else {
683     return createRegOperand(AMDGPU::VCC);
684   }
685 }
686 
687 //===----------------------------------------------------------------------===//
688 // AMDGPUSymbolizer
689 //===----------------------------------------------------------------------===//
690 
691 // Try to find symbol name for specified label
692 bool AMDGPUSymbolizer::tryAddingSymbolicOperand(MCInst &Inst,
693                                 raw_ostream &/*cStream*/, int64_t Value,
694                                 uint64_t /*Address*/, bool IsBranch,
695                                 uint64_t /*Offset*/, uint64_t /*InstSize*/) {
696   typedef std::tuple<uint64_t, StringRef, uint8_t> SymbolInfoTy;
697   typedef std::vector<SymbolInfoTy> SectionSymbolsTy;
698 
699   if (!IsBranch) {
700     return false;
701   }
702 
703   auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo);
704   auto Result = std::find_if(Symbols->begin(), Symbols->end(),
705                              [Value](const SymbolInfoTy& Val) {
706                                 return std::get<0>(Val) == static_cast<uint64_t>(Value)
707                                     && std::get<2>(Val) == ELF::STT_NOTYPE;
708                              });
709   if (Result != Symbols->end()) {
710     auto *Sym = Ctx.getOrCreateSymbol(std::get<1>(*Result));
711     const auto *Add = MCSymbolRefExpr::create(Sym, Ctx);
712     Inst.addOperand(MCOperand::createExpr(Add));
713     return true;
714   }
715   return false;
716 }
717 
718 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream,
719                                                        int64_t Value,
720                                                        uint64_t Address) {
721   llvm_unreachable("unimplemented");
722 }
723 
724 //===----------------------------------------------------------------------===//
725 // Initialization
726 //===----------------------------------------------------------------------===//
727 
728 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/,
729                               LLVMOpInfoCallback /*GetOpInfo*/,
730                               LLVMSymbolLookupCallback /*SymbolLookUp*/,
731                               void *DisInfo,
732                               MCContext *Ctx,
733                               std::unique_ptr<MCRelocationInfo> &&RelInfo) {
734   return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo);
735 }
736 
737 static MCDisassembler *createAMDGPUDisassembler(const Target &T,
738                                                 const MCSubtargetInfo &STI,
739                                                 MCContext &Ctx) {
740   return new AMDGPUDisassembler(STI, Ctx);
741 }
742 
743 extern "C" void LLVMInitializeAMDGPUDisassembler() {
744   TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(),
745                                          createAMDGPUDisassembler);
746   TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(),
747                                        createAMDGPUSymbolizer);
748 }
749