1 //===-- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA --------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 //===----------------------------------------------------------------------===//
11 //
12 /// \file
13 ///
14 /// This file contains definition for AMDGPU ISA disassembler
15 //
16 //===----------------------------------------------------------------------===//
17 
18 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)?
19 
20 #include "AMDGPUDisassembler.h"
21 #include "AMDGPU.h"
22 #include "AMDGPURegisterInfo.h"
23 #include "SIDefines.h"
24 #include "Utils/AMDGPUBaseInfo.h"
25 
26 #include "llvm/MC/MCContext.h"
27 #include "llvm/MC/MCFixedLenDisassembler.h"
28 #include "llvm/MC/MCInst.h"
29 #include "llvm/MC/MCInstrDesc.h"
30 #include "llvm/MC/MCSubtargetInfo.h"
31 #include "llvm/Support/Endian.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/TargetRegistry.h"
34 
35 
36 using namespace llvm;
37 
38 #define DEBUG_TYPE "amdgpu-disassembler"
39 
40 typedef llvm::MCDisassembler::DecodeStatus DecodeStatus;
41 
42 
43 inline static MCDisassembler::DecodeStatus
44 addOperand(MCInst &Inst, const MCOperand& Opnd) {
45   Inst.addOperand(Opnd);
46   return Opnd.isValid() ?
47     MCDisassembler::Success :
48     MCDisassembler::SoftFail;
49 }
50 
51 #define DECODE_OPERAND2(RegClass, DecName) \
52 static DecodeStatus Decode##RegClass##RegisterClass(MCInst &Inst, \
53                                                     unsigned Imm, \
54                                                     uint64_t /*Addr*/, \
55                                                     const void *Decoder) { \
56   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); \
57   return addOperand(Inst, DAsm->decodeOperand_##DecName(Imm)); \
58 }
59 
60 #define DECODE_OPERAND(RegClass) DECODE_OPERAND2(RegClass, RegClass)
61 
62 DECODE_OPERAND(VGPR_32)
63 DECODE_OPERAND(VS_32)
64 DECODE_OPERAND(VS_64)
65 
66 DECODE_OPERAND(VReg_64)
67 DECODE_OPERAND(VReg_96)
68 DECODE_OPERAND(VReg_128)
69 
70 DECODE_OPERAND(SReg_32)
71 DECODE_OPERAND(SReg_32_XM0)
72 DECODE_OPERAND(SReg_64)
73 DECODE_OPERAND(SReg_128)
74 DECODE_OPERAND(SReg_256)
75 DECODE_OPERAND(SReg_512)
76 
77 #define GET_SUBTARGETINFO_ENUM
78 #include "AMDGPUGenSubtargetInfo.inc"
79 #undef GET_SUBTARGETINFO_ENUM
80 
81 #include "AMDGPUGenDisassemblerTables.inc"
82 
83 //===----------------------------------------------------------------------===//
84 //
85 //===----------------------------------------------------------------------===//
86 
87 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) {
88   assert(Bytes.size() >= sizeof(T));
89   const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data());
90   Bytes = Bytes.slice(sizeof(T));
91   return Res;
92 }
93 
94 DecodeStatus AMDGPUDisassembler::tryDecodeInst(const uint8_t* Table,
95                                                MCInst &MI,
96                                                uint64_t Inst,
97                                                uint64_t Address) const {
98   assert(MI.getOpcode() == 0);
99   assert(MI.getNumOperands() == 0);
100   MCInst TmpInst;
101   const auto SavedBytes = Bytes;
102   if (decodeInstruction(Table, TmpInst, Inst, Address, this, STI)) {
103     MI = TmpInst;
104     return MCDisassembler::Success;
105   }
106   Bytes = SavedBytes;
107   return MCDisassembler::Fail;
108 }
109 
110 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
111                                                 ArrayRef<uint8_t> Bytes_,
112                                                 uint64_t Address,
113                                                 raw_ostream &WS,
114                                                 raw_ostream &CS) const {
115   CommentStream = &CS;
116 
117   // ToDo: AMDGPUDisassembler supports only VI ISA.
118   assert(AMDGPU::isVI(STI) && "Can disassemble only VI ISA.");
119 
120   const unsigned MaxInstBytesNum = (std::min)((size_t)8, Bytes_.size());
121   Bytes = Bytes_.slice(0, MaxInstBytesNum);
122 
123   DecodeStatus Res = MCDisassembler::Fail;
124   do {
125     // ToDo: better to switch encoding length using some bit predicate
126     // but it is unknown yet, so try all we can
127 
128     // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2
129     // encodings
130     if (Bytes.size() >= 8) {
131       const uint64_t QW = eatBytes<uint64_t>(Bytes);
132       Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address);
133       if (Res) break;
134 
135       Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address);
136       if (Res) break;
137     }
138 
139     // Reinitialize Bytes as DPP64 could have eaten too much
140     Bytes = Bytes_.slice(0, MaxInstBytesNum);
141 
142     // Try decode 32-bit instruction
143     if (Bytes.size() < 4) break;
144     const uint32_t DW = eatBytes<uint32_t>(Bytes);
145     Res = tryDecodeInst(DecoderTableVI32, MI, DW, Address);
146     if (Res) break;
147 
148     Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address);
149     if (Res) break;
150 
151     if (Bytes.size() < 4) break;
152     const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW;
153     Res = tryDecodeInst(DecoderTableVI64, MI, QW, Address);
154     if (Res) break;
155 
156     Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address);
157   } while (false);
158 
159   Size = Res ? (MaxInstBytesNum - Bytes.size()) : 0;
160   return Res;
161 }
162 
163 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const {
164   return getContext().getRegisterInfo()->
165     getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]);
166 }
167 
168 inline
169 MCOperand AMDGPUDisassembler::errOperand(unsigned V,
170                                          const Twine& ErrMsg) const {
171   *CommentStream << "Error: " + ErrMsg;
172 
173   // ToDo: add support for error operands to MCInst.h
174   // return MCOperand::createError(V);
175   return MCOperand();
176 }
177 
178 inline
179 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const {
180   return MCOperand::createReg(RegId);
181 }
182 
183 inline
184 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID,
185                                                unsigned Val) const {
186   const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID];
187   if (Val >= RegCl.getNumRegs())
188     return errOperand(Val, Twine(getRegClassName(RegClassID)) +
189                            ": unknown register " + Twine(Val));
190   return createRegOperand(RegCl.getRegister(Val));
191 }
192 
193 inline
194 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID,
195                                                 unsigned Val) const {
196   // ToDo: SI/CI have 104 SGPRs, VI - 102
197   // Valery: here we accepting as much as we can, let assembler sort it out
198   int shift = 0;
199   switch (SRegClassID) {
200   case AMDGPU::SGPR_32RegClassID:
201   case AMDGPU::TTMP_32RegClassID:
202     break;
203   case AMDGPU::SGPR_64RegClassID:
204   case AMDGPU::TTMP_64RegClassID:
205     shift = 1;
206     break;
207   case AMDGPU::SGPR_128RegClassID:
208   case AMDGPU::TTMP_128RegClassID:
209   // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in
210   // this bundle?
211   case AMDGPU::SReg_256RegClassID:
212   // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in
213   // this bundle?
214   case AMDGPU::SReg_512RegClassID:
215     shift = 2;
216     break;
217   // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in
218   // this bundle?
219   default:
220     assert(false);
221     break;
222   }
223   if (Val % (1 << shift))
224     *CommentStream << "Warning: " << getRegClassName(SRegClassID)
225                    << ": scalar reg isn't aligned " << Val;
226   return createRegOperand(SRegClassID, Val >> shift);
227 }
228 
229 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const {
230   return decodeSrcOp(OPW32, Val);
231 }
232 
233 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const {
234   return decodeSrcOp(OPW64, Val);
235 }
236 
237 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const {
238   // Some instructions have operand restrictions beyond what the encoding
239   // allows. Some ordinarily VSrc_32 operands are VGPR_32, so clear the extra
240   // high bit.
241   Val &= 255;
242 
243   return createRegOperand(AMDGPU::VGPR_32RegClassID, Val);
244 }
245 
246 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const {
247   return createRegOperand(AMDGPU::VReg_64RegClassID, Val);
248 }
249 
250 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const {
251   return createRegOperand(AMDGPU::VReg_96RegClassID, Val);
252 }
253 
254 MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const {
255   return createRegOperand(AMDGPU::VReg_128RegClassID, Val);
256 }
257 
258 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const {
259   // table-gen generated disassembler doesn't care about operand types
260   // leaving only registry class so SSrc_32 operand turns into SReg_32
261   // and therefore we accept immediates and literals here as well
262   return decodeSrcOp(OPW32, Val);
263 }
264 
265 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0(unsigned Val) const {
266   // SReg_32_XM0 is SReg_32 without M0
267   return decodeOperand_SReg_32(Val);
268 }
269 
270 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const {
271   // see decodeOperand_SReg_32 comment
272   return decodeSrcOp(OPW64, Val);
273 }
274 
275 MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const {
276   return decodeSrcOp(OPW128, Val);
277 }
278 
279 MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const {
280   return createSRegOperand(AMDGPU::SReg_256RegClassID, Val);
281 }
282 
283 MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const {
284   return createSRegOperand(AMDGPU::SReg_512RegClassID, Val);
285 }
286 
287 
288 MCOperand AMDGPUDisassembler::decodeLiteralConstant() const {
289   // For now all literal constants are supposed to be unsigned integer
290   // ToDo: deal with signed/unsigned 64-bit integer constants
291   // ToDo: deal with float/double constants
292   if (Bytes.size() < 4)
293     return errOperand(0, "cannot read literal, inst bytes left " +
294                          Twine(Bytes.size()));
295   return MCOperand::createImm(eatBytes<uint32_t>(Bytes));
296 }
297 
298 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) {
299   using namespace AMDGPU::EncValues;
300   assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX);
301   return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ?
302     (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) :
303     (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm)));
304       // Cast prevents negative overflow.
305 }
306 
307 MCOperand AMDGPUDisassembler::decodeFPImmed(bool Is32, unsigned Imm) {
308   assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN
309       && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX);
310   // ToDo: case 248: 1/(2*PI) - is allowed only on VI
311   // ToDo: AMDGPUInstPrinter does not support 1/(2*PI). It consider 1/(2*PI) as
312   // literal constant.
313   float V = 0.0f;
314   switch (Imm) {
315   case 240: V =  0.5f; break;
316   case 241: V = -0.5f; break;
317   case 242: V =  1.0f; break;
318   case 243: V = -1.0f; break;
319   case 244: V =  2.0f; break;
320   case 245: V = -2.0f; break;
321   case 246: V =  4.0f; break;
322   case 247: V = -4.0f; break;
323   case 248: return MCOperand::createImm(Is32 ?         // 1/(2*PI)
324                                           0x3e22f983 :
325                                           0x3fc45f306dc9c882);
326   default: break;
327   }
328   return MCOperand::createImm(Is32? FloatToBits(V) : DoubleToBits(V));
329 }
330 
331 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const {
332   using namespace AMDGPU;
333   assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
334   switch (Width) {
335   default: // fall
336   case OPW32: return VGPR_32RegClassID;
337   case OPW64: return VReg_64RegClassID;
338   case OPW128: return VReg_128RegClassID;
339   }
340 }
341 
342 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const {
343   using namespace AMDGPU;
344   assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
345   switch (Width) {
346   default: // fall
347   case OPW32: return SGPR_32RegClassID;
348   case OPW64: return SGPR_64RegClassID;
349   case OPW128: return SGPR_128RegClassID;
350   }
351 }
352 
353 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const {
354   using namespace AMDGPU;
355   assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
356   switch (Width) {
357   default: // fall
358   case OPW32: return TTMP_32RegClassID;
359   case OPW64: return TTMP_64RegClassID;
360   case OPW128: return TTMP_128RegClassID;
361   }
362 }
363 
364 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val) const {
365   using namespace AMDGPU::EncValues;
366   assert(Val < 512); // enum9
367 
368   if (VGPR_MIN <= Val && Val <= VGPR_MAX) {
369     return createRegOperand(getVgprClassId(Width), Val - VGPR_MIN);
370   }
371   if (Val <= SGPR_MAX) {
372     assert(SGPR_MIN == 0); // "SGPR_MIN <= Val" is always true and causes compilation warning.
373     return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN);
374   }
375   if (TTMP_MIN <= Val && Val <= TTMP_MAX) {
376     return createSRegOperand(getTtmpClassId(Width), Val - TTMP_MIN);
377   }
378 
379   assert(Width == OPW32 || Width == OPW64);
380   const bool Is32 = (Width == OPW32);
381 
382   if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX)
383     return decodeIntImmed(Val);
384 
385   if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX)
386     return decodeFPImmed(Is32, Val);
387 
388   if (Val == LITERAL_CONST)
389     return decodeLiteralConstant();
390 
391   return Is32 ? decodeSpecialReg32(Val) : decodeSpecialReg64(Val);
392 }
393 
394 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const {
395   using namespace AMDGPU;
396   switch (Val) {
397   case 102: return createRegOperand(getMCReg(FLAT_SCR_LO, STI));
398   case 103: return createRegOperand(getMCReg(FLAT_SCR_HI, STI));
399     // ToDo: no support for xnack_mask_lo/_hi register
400   case 104:
401   case 105: break;
402   case 106: return createRegOperand(VCC_LO);
403   case 107: return createRegOperand(VCC_HI);
404   case 108: return createRegOperand(TBA_LO);
405   case 109: return createRegOperand(TBA_HI);
406   case 110: return createRegOperand(TMA_LO);
407   case 111: return createRegOperand(TMA_HI);
408   case 124: return createRegOperand(M0);
409   case 126: return createRegOperand(EXEC_LO);
410   case 127: return createRegOperand(EXEC_HI);
411     // ToDo: no support for vccz register
412   case 251: break;
413     // ToDo: no support for execz register
414   case 252: break;
415   case 253: return createRegOperand(SCC);
416   default: break;
417   }
418   return errOperand(Val, "unknown operand encoding " + Twine(Val));
419 }
420 
421 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const {
422   using namespace AMDGPU;
423   switch (Val) {
424   case 102: return createRegOperand(getMCReg(FLAT_SCR, STI));
425   case 106: return createRegOperand(VCC);
426   case 108: return createRegOperand(TBA);
427   case 110: return createRegOperand(TMA);
428   case 126: return createRegOperand(EXEC);
429   default: break;
430   }
431   return errOperand(Val, "unknown operand encoding " + Twine(Val));
432 }
433 
434 static MCDisassembler *createAMDGPUDisassembler(const Target &T,
435                                                 const MCSubtargetInfo &STI,
436                                                 MCContext &Ctx) {
437   return new AMDGPUDisassembler(STI, Ctx);
438 }
439 
440 extern "C" void LLVMInitializeAMDGPUDisassembler() {
441   TargetRegistry::RegisterMCDisassembler(TheGCNTarget, createAMDGPUDisassembler);
442 }
443