1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 //===----------------------------------------------------------------------===// 10 // 11 /// \file 12 /// 13 /// This file contains definition for AMDGPU ISA disassembler 14 // 15 //===----------------------------------------------------------------------===// 16 17 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)? 18 19 #include "Disassembler/AMDGPUDisassembler.h" 20 #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 21 #include "TargetInfo/AMDGPUTargetInfo.h" 22 #include "Utils/AMDGPUBaseInfo.h" 23 #include "llvm-c/DisassemblerTypes.h" 24 #include "llvm/MC/MCAsmInfo.h" 25 #include "llvm/MC/MCContext.h" 26 #include "llvm/MC/MCExpr.h" 27 #include "llvm/MC/MCFixedLenDisassembler.h" 28 #include "llvm/Support/AMDHSAKernelDescriptor.h" 29 #include "llvm/Support/TargetRegistry.h" 30 31 using namespace llvm; 32 33 #define DEBUG_TYPE "amdgpu-disassembler" 34 35 #define SGPR_MAX \ 36 (isGFX10Plus() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \ 37 : AMDGPU::EncValues::SGPR_MAX_SI) 38 39 using DecodeStatus = llvm::MCDisassembler::DecodeStatus; 40 41 AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI, 42 MCContext &Ctx, 43 MCInstrInfo const *MCII) : 44 MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()), 45 TargetMaxInstBytes(Ctx.getAsmInfo()->getMaxInstLength(&STI)) { 46 47 // ToDo: AMDGPUDisassembler supports only VI ISA. 48 if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding] && !isGFX10Plus()) 49 report_fatal_error("Disassembly not yet supported for subtarget"); 50 } 51 52 inline static MCDisassembler::DecodeStatus 53 addOperand(MCInst &Inst, const MCOperand& Opnd) { 54 Inst.addOperand(Opnd); 55 return Opnd.isValid() ? 56 MCDisassembler::Success : 57 MCDisassembler::Fail; 58 } 59 60 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, 61 uint16_t NameIdx) { 62 int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx); 63 if (OpIdx != -1) { 64 auto I = MI.begin(); 65 std::advance(I, OpIdx); 66 MI.insert(I, Op); 67 } 68 return OpIdx; 69 } 70 71 static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm, 72 uint64_t Addr, const void *Decoder) { 73 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 74 75 // Our branches take a simm16, but we need two extra bits to account for the 76 // factor of 4. 77 APInt SignedOffset(18, Imm * 4, true); 78 int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue(); 79 80 if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2)) 81 return MCDisassembler::Success; 82 return addOperand(Inst, MCOperand::createImm(Imm)); 83 } 84 85 static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, 86 uint64_t Addr, const void *Decoder) { 87 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 88 int64_t Offset; 89 if (DAsm->isVI()) { // VI supports 20-bit unsigned offsets. 90 Offset = Imm & 0xFFFFF; 91 } else { // GFX9+ supports 21-bit signed offsets. 92 Offset = SignExtend64<21>(Imm); 93 } 94 return addOperand(Inst, MCOperand::createImm(Offset)); 95 } 96 97 static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, 98 uint64_t Addr, const void *Decoder) { 99 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 100 return addOperand(Inst, DAsm->decodeBoolReg(Val)); 101 } 102 103 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \ 104 static DecodeStatus StaticDecoderName(MCInst &Inst, \ 105 unsigned Imm, \ 106 uint64_t /*Addr*/, \ 107 const void *Decoder) { \ 108 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); \ 109 return addOperand(Inst, DAsm->DecoderName(Imm)); \ 110 } 111 112 #define DECODE_OPERAND_REG(RegClass) \ 113 DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass) 114 115 DECODE_OPERAND_REG(VGPR_32) 116 DECODE_OPERAND_REG(VRegOrLds_32) 117 DECODE_OPERAND_REG(VS_32) 118 DECODE_OPERAND_REG(VS_64) 119 DECODE_OPERAND_REG(VS_128) 120 121 DECODE_OPERAND_REG(VReg_64) 122 DECODE_OPERAND_REG(VReg_96) 123 DECODE_OPERAND_REG(VReg_128) 124 DECODE_OPERAND_REG(VReg_256) 125 DECODE_OPERAND_REG(VReg_512) 126 127 DECODE_OPERAND_REG(SReg_32) 128 DECODE_OPERAND_REG(SReg_32_XM0_XEXEC) 129 DECODE_OPERAND_REG(SReg_32_XEXEC_HI) 130 DECODE_OPERAND_REG(SRegOrLds_32) 131 DECODE_OPERAND_REG(SReg_64) 132 DECODE_OPERAND_REG(SReg_64_XEXEC) 133 DECODE_OPERAND_REG(SReg_128) 134 DECODE_OPERAND_REG(SReg_256) 135 DECODE_OPERAND_REG(SReg_512) 136 137 DECODE_OPERAND_REG(AGPR_32) 138 DECODE_OPERAND_REG(AReg_128) 139 DECODE_OPERAND_REG(AReg_512) 140 DECODE_OPERAND_REG(AReg_1024) 141 DECODE_OPERAND_REG(AV_32) 142 DECODE_OPERAND_REG(AV_64) 143 144 static DecodeStatus decodeOperand_VSrc16(MCInst &Inst, 145 unsigned Imm, 146 uint64_t Addr, 147 const void *Decoder) { 148 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 149 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); 150 } 151 152 static DecodeStatus decodeOperand_VSrcV216(MCInst &Inst, 153 unsigned Imm, 154 uint64_t Addr, 155 const void *Decoder) { 156 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 157 return addOperand(Inst, DAsm->decodeOperand_VSrcV216(Imm)); 158 } 159 160 static DecodeStatus decodeOperand_VS_16(MCInst &Inst, 161 unsigned Imm, 162 uint64_t Addr, 163 const void *Decoder) { 164 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 165 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); 166 } 167 168 static DecodeStatus decodeOperand_VS_32(MCInst &Inst, 169 unsigned Imm, 170 uint64_t Addr, 171 const void *Decoder) { 172 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 173 return addOperand(Inst, DAsm->decodeOperand_VS_32(Imm)); 174 } 175 176 static DecodeStatus decodeOperand_AReg_128(MCInst &Inst, 177 unsigned Imm, 178 uint64_t Addr, 179 const void *Decoder) { 180 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 181 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm | 512)); 182 } 183 184 static DecodeStatus decodeOperand_AReg_512(MCInst &Inst, 185 unsigned Imm, 186 uint64_t Addr, 187 const void *Decoder) { 188 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 189 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm | 512)); 190 } 191 192 static DecodeStatus decodeOperand_AReg_1024(MCInst &Inst, 193 unsigned Imm, 194 uint64_t Addr, 195 const void *Decoder) { 196 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 197 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm | 512)); 198 } 199 200 static DecodeStatus decodeOperand_SReg_32(MCInst &Inst, 201 unsigned Imm, 202 uint64_t Addr, 203 const void *Decoder) { 204 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 205 return addOperand(Inst, DAsm->decodeOperand_SReg_32(Imm)); 206 } 207 208 static DecodeStatus decodeOperand_VGPR_32(MCInst &Inst, 209 unsigned Imm, 210 uint64_t Addr, 211 const void *Decoder) { 212 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 213 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW32, Imm)); 214 } 215 216 #define DECODE_SDWA(DecName) \ 217 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName) 218 219 DECODE_SDWA(Src32) 220 DECODE_SDWA(Src16) 221 DECODE_SDWA(VopcDst) 222 223 #include "AMDGPUGenDisassemblerTables.inc" 224 225 //===----------------------------------------------------------------------===// 226 // 227 //===----------------------------------------------------------------------===// 228 229 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) { 230 assert(Bytes.size() >= sizeof(T)); 231 const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data()); 232 Bytes = Bytes.slice(sizeof(T)); 233 return Res; 234 } 235 236 DecodeStatus AMDGPUDisassembler::tryDecodeInst(const uint8_t* Table, 237 MCInst &MI, 238 uint64_t Inst, 239 uint64_t Address) const { 240 assert(MI.getOpcode() == 0); 241 assert(MI.getNumOperands() == 0); 242 MCInst TmpInst; 243 HasLiteral = false; 244 const auto SavedBytes = Bytes; 245 if (decodeInstruction(Table, TmpInst, Inst, Address, this, STI)) { 246 MI = TmpInst; 247 return MCDisassembler::Success; 248 } 249 Bytes = SavedBytes; 250 return MCDisassembler::Fail; 251 } 252 253 static bool isValidDPP8(const MCInst &MI) { 254 using namespace llvm::AMDGPU::DPP; 255 int FiIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::fi); 256 assert(FiIdx != -1); 257 if ((unsigned)FiIdx >= MI.getNumOperands()) 258 return false; 259 unsigned Fi = MI.getOperand(FiIdx).getImm(); 260 return Fi == DPP8_FI_0 || Fi == DPP8_FI_1; 261 } 262 263 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 264 ArrayRef<uint8_t> Bytes_, 265 uint64_t Address, 266 raw_ostream &CS) const { 267 CommentStream = &CS; 268 bool IsSDWA = false; 269 270 unsigned MaxInstBytesNum = std::min((size_t)TargetMaxInstBytes, Bytes_.size()); 271 Bytes = Bytes_.slice(0, MaxInstBytesNum); 272 273 DecodeStatus Res = MCDisassembler::Fail; 274 do { 275 // ToDo: better to switch encoding length using some bit predicate 276 // but it is unknown yet, so try all we can 277 278 // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2 279 // encodings 280 if (Bytes.size() >= 8) { 281 const uint64_t QW = eatBytes<uint64_t>(Bytes); 282 283 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) { 284 Res = tryDecodeInst(DecoderTableGFX10_B64, MI, QW, Address); 285 if (Res) { 286 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dpp8) 287 == -1) 288 break; 289 if (convertDPP8Inst(MI) == MCDisassembler::Success) 290 break; 291 MI = MCInst(); // clear 292 } 293 } 294 295 Res = tryDecodeInst(DecoderTableDPP864, MI, QW, Address); 296 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 297 break; 298 299 MI = MCInst(); // clear 300 301 Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address); 302 if (Res) break; 303 304 Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address); 305 if (Res) { IsSDWA = true; break; } 306 307 Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address); 308 if (Res) { IsSDWA = true; break; } 309 310 Res = tryDecodeInst(DecoderTableSDWA1064, MI, QW, Address); 311 if (Res) { IsSDWA = true; break; } 312 313 if (STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem]) { 314 Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address); 315 if (Res) 316 break; 317 } 318 319 // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and 320 // v_mad_mixhi_f16 for FMA variants. Try to decode using this special 321 // table first so we print the correct name. 322 if (STI.getFeatureBits()[AMDGPU::FeatureFmaMixInsts]) { 323 Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address); 324 if (Res) 325 break; 326 } 327 } 328 329 // Reinitialize Bytes as DPP64 could have eaten too much 330 Bytes = Bytes_.slice(0, MaxInstBytesNum); 331 332 // Try decode 32-bit instruction 333 if (Bytes.size() < 4) break; 334 const uint32_t DW = eatBytes<uint32_t>(Bytes); 335 Res = tryDecodeInst(DecoderTableGFX832, MI, DW, Address); 336 if (Res) break; 337 338 Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address); 339 if (Res) break; 340 341 Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address); 342 if (Res) break; 343 344 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) { 345 Res = tryDecodeInst(DecoderTableGFX10_B32, MI, DW, Address); 346 if (Res) break; 347 } 348 349 Res = tryDecodeInst(DecoderTableGFX1032, MI, DW, Address); 350 if (Res) break; 351 352 if (Bytes.size() < 4) break; 353 const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW; 354 Res = tryDecodeInst(DecoderTableGFX864, MI, QW, Address); 355 if (Res) break; 356 357 Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address); 358 if (Res) break; 359 360 Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address); 361 if (Res) break; 362 363 Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address); 364 } while (false); 365 366 if (Res && (MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi || 367 MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx6_gfx7 || 368 MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx10 || 369 MI.getOpcode() == AMDGPU::V_MAC_LEGACY_F32_e64_gfx6_gfx7 || 370 MI.getOpcode() == AMDGPU::V_MAC_LEGACY_F32_e64_gfx10 || 371 MI.getOpcode() == AMDGPU::V_MAC_F16_e64_vi || 372 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_vi || 373 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_gfx10 || 374 MI.getOpcode() == AMDGPU::V_FMAC_LEGACY_F32_e64_gfx10 || 375 MI.getOpcode() == AMDGPU::V_FMAC_F16_e64_gfx10)) { 376 // Insert dummy unused src2_modifiers. 377 insertNamedMCOperand(MI, MCOperand::createImm(0), 378 AMDGPU::OpName::src2_modifiers); 379 } 380 381 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 382 (SIInstrFlags::MUBUF | SIInstrFlags::FLAT)) && 383 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::glc1) != -1) { 384 insertNamedMCOperand(MI, MCOperand::createImm(1), AMDGPU::OpName::glc1); 385 } 386 387 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) { 388 int VAddr0Idx = 389 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 390 int RsrcIdx = 391 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc); 392 unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1; 393 if (VAddr0Idx >= 0 && NSAArgs > 0) { 394 unsigned NSAWords = (NSAArgs + 3) / 4; 395 if (Bytes.size() < 4 * NSAWords) { 396 Res = MCDisassembler::Fail; 397 } else { 398 for (unsigned i = 0; i < NSAArgs; ++i) { 399 MI.insert(MI.begin() + VAddr0Idx + 1 + i, 400 decodeOperand_VGPR_32(Bytes[i])); 401 } 402 Bytes = Bytes.slice(4 * NSAWords); 403 } 404 } 405 406 if (Res) 407 Res = convertMIMGInst(MI); 408 } 409 410 if (Res && IsSDWA) 411 Res = convertSDWAInst(MI); 412 413 int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 414 AMDGPU::OpName::vdst_in); 415 if (VDstIn_Idx != -1) { 416 int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx, 417 MCOI::OperandConstraint::TIED_TO); 418 if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx || 419 !MI.getOperand(VDstIn_Idx).isReg() || 420 MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) { 421 if (MI.getNumOperands() > (unsigned)VDstIn_Idx) 422 MI.erase(&MI.getOperand(VDstIn_Idx)); 423 insertNamedMCOperand(MI, 424 MCOperand::createReg(MI.getOperand(Tied).getReg()), 425 AMDGPU::OpName::vdst_in); 426 } 427 } 428 429 // if the opcode was not recognized we'll assume a Size of 4 bytes 430 // (unless there are fewer bytes left) 431 Size = Res ? (MaxInstBytesNum - Bytes.size()) 432 : std::min((size_t)4, Bytes_.size()); 433 return Res; 434 } 435 436 DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const { 437 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 438 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 439 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst) != -1) 440 // VOPC - insert clamp 441 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp); 442 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 443 int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst); 444 if (SDst != -1) { 445 // VOPC - insert VCC register as sdst 446 insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC), 447 AMDGPU::OpName::sdst); 448 } else { 449 // VOP1/2 - insert omod if present in instruction 450 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod); 451 } 452 } 453 return MCDisassembler::Success; 454 } 455 456 DecodeStatus AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const { 457 unsigned Opc = MI.getOpcode(); 458 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 459 460 // Insert dummy unused src modifiers. 461 if (MI.getNumOperands() < DescNumOps && 462 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1) 463 insertNamedMCOperand(MI, MCOperand::createImm(0), 464 AMDGPU::OpName::src0_modifiers); 465 466 if (MI.getNumOperands() < DescNumOps && 467 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers) != -1) 468 insertNamedMCOperand(MI, MCOperand::createImm(0), 469 AMDGPU::OpName::src1_modifiers); 470 471 return isValidDPP8(MI) ? MCDisassembler::Success : MCDisassembler::SoftFail; 472 } 473 474 // Note that before gfx10, the MIMG encoding provided no information about 475 // VADDR size. Consequently, decoded instructions always show address as if it 476 // has 1 dword, which could be not really so. 477 DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const { 478 479 int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 480 AMDGPU::OpName::vdst); 481 482 int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 483 AMDGPU::OpName::vdata); 484 int VAddr0Idx = 485 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 486 int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 487 AMDGPU::OpName::dmask); 488 489 int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 490 AMDGPU::OpName::tfe); 491 int D16Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 492 AMDGPU::OpName::d16); 493 494 assert(VDataIdx != -1); 495 if (DMaskIdx == -1 || TFEIdx == -1) {// intersect_ray 496 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16) > -1) { 497 assert(MI.getOpcode() == AMDGPU::IMAGE_BVH_INTERSECT_RAY_a16_sa || 498 MI.getOpcode() == AMDGPU::IMAGE_BVH_INTERSECT_RAY_a16_nsa || 499 MI.getOpcode() == AMDGPU::IMAGE_BVH64_INTERSECT_RAY_a16_sa || 500 MI.getOpcode() == AMDGPU::IMAGE_BVH64_INTERSECT_RAY_a16_nsa); 501 addOperand(MI, MCOperand::createImm(1)); 502 } 503 return MCDisassembler::Success; 504 } 505 506 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode()); 507 bool IsAtomic = (VDstIdx != -1); 508 bool IsGather4 = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::Gather4; 509 510 bool IsNSA = false; 511 unsigned AddrSize = Info->VAddrDwords; 512 513 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 514 unsigned DimIdx = 515 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim); 516 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = 517 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); 518 const AMDGPU::MIMGDimInfo *Dim = 519 AMDGPU::getMIMGDimInfoByEncoding(MI.getOperand(DimIdx).getImm()); 520 521 AddrSize = BaseOpcode->NumExtraArgs + 522 (BaseOpcode->Gradients ? Dim->NumGradients : 0) + 523 (BaseOpcode->Coordinates ? Dim->NumCoords : 0) + 524 (BaseOpcode->LodOrClampOrMip ? 1 : 0); 525 IsNSA = Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA; 526 if (!IsNSA) { 527 if (AddrSize > 8) 528 AddrSize = 16; 529 else if (AddrSize > 4) 530 AddrSize = 8; 531 } else { 532 if (AddrSize > Info->VAddrDwords) { 533 // The NSA encoding does not contain enough operands for the combination 534 // of base opcode / dimension. Should this be an error? 535 return MCDisassembler::Success; 536 } 537 } 538 } 539 540 unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf; 541 unsigned DstSize = IsGather4 ? 4 : std::max(countPopulation(DMask), 1u); 542 543 bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm(); 544 if (D16 && AMDGPU::hasPackedD16(STI)) { 545 DstSize = (DstSize + 1) / 2; 546 } 547 548 // FIXME: Add tfe support 549 if (MI.getOperand(TFEIdx).getImm()) 550 return MCDisassembler::Success; 551 552 if (DstSize == Info->VDataDwords && AddrSize == Info->VAddrDwords) 553 return MCDisassembler::Success; 554 555 int NewOpcode = 556 AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize); 557 if (NewOpcode == -1) 558 return MCDisassembler::Success; 559 560 // Widen the register to the correct number of enabled channels. 561 unsigned NewVdata = AMDGPU::NoRegister; 562 if (DstSize != Info->VDataDwords) { 563 auto DataRCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass; 564 565 // Get first subregister of VData 566 unsigned Vdata0 = MI.getOperand(VDataIdx).getReg(); 567 unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0); 568 Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0; 569 570 NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0, 571 &MRI.getRegClass(DataRCID)); 572 if (NewVdata == AMDGPU::NoRegister) { 573 // It's possible to encode this such that the low register + enabled 574 // components exceeds the register count. 575 return MCDisassembler::Success; 576 } 577 } 578 579 unsigned NewVAddr0 = AMDGPU::NoRegister; 580 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10] && !IsNSA && 581 AddrSize != Info->VAddrDwords) { 582 unsigned VAddr0 = MI.getOperand(VAddr0Idx).getReg(); 583 unsigned VAddrSub0 = MRI.getSubReg(VAddr0, AMDGPU::sub0); 584 VAddr0 = (VAddrSub0 != 0) ? VAddrSub0 : VAddr0; 585 586 auto AddrRCID = MCII->get(NewOpcode).OpInfo[VAddr0Idx].RegClass; 587 NewVAddr0 = MRI.getMatchingSuperReg(VAddr0, AMDGPU::sub0, 588 &MRI.getRegClass(AddrRCID)); 589 if (NewVAddr0 == AMDGPU::NoRegister) 590 return MCDisassembler::Success; 591 } 592 593 MI.setOpcode(NewOpcode); 594 595 if (NewVdata != AMDGPU::NoRegister) { 596 MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata); 597 598 if (IsAtomic) { 599 // Atomic operations have an additional operand (a copy of data) 600 MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata); 601 } 602 } 603 604 if (NewVAddr0 != AMDGPU::NoRegister) { 605 MI.getOperand(VAddr0Idx) = MCOperand::createReg(NewVAddr0); 606 } else if (IsNSA) { 607 assert(AddrSize <= Info->VAddrDwords); 608 MI.erase(MI.begin() + VAddr0Idx + AddrSize, 609 MI.begin() + VAddr0Idx + Info->VAddrDwords); 610 } 611 612 return MCDisassembler::Success; 613 } 614 615 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { 616 return getContext().getRegisterInfo()-> 617 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); 618 } 619 620 inline 621 MCOperand AMDGPUDisassembler::errOperand(unsigned V, 622 const Twine& ErrMsg) const { 623 *CommentStream << "Error: " + ErrMsg; 624 625 // ToDo: add support for error operands to MCInst.h 626 // return MCOperand::createError(V); 627 return MCOperand(); 628 } 629 630 inline 631 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const { 632 return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI)); 633 } 634 635 inline 636 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, 637 unsigned Val) const { 638 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; 639 if (Val >= RegCl.getNumRegs()) 640 return errOperand(Val, Twine(getRegClassName(RegClassID)) + 641 ": unknown register " + Twine(Val)); 642 return createRegOperand(RegCl.getRegister(Val)); 643 } 644 645 inline 646 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID, 647 unsigned Val) const { 648 // ToDo: SI/CI have 104 SGPRs, VI - 102 649 // Valery: here we accepting as much as we can, let assembler sort it out 650 int shift = 0; 651 switch (SRegClassID) { 652 case AMDGPU::SGPR_32RegClassID: 653 case AMDGPU::TTMP_32RegClassID: 654 break; 655 case AMDGPU::SGPR_64RegClassID: 656 case AMDGPU::TTMP_64RegClassID: 657 shift = 1; 658 break; 659 case AMDGPU::SGPR_128RegClassID: 660 case AMDGPU::TTMP_128RegClassID: 661 // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in 662 // this bundle? 663 case AMDGPU::SGPR_256RegClassID: 664 case AMDGPU::TTMP_256RegClassID: 665 // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in 666 // this bundle? 667 case AMDGPU::SGPR_512RegClassID: 668 case AMDGPU::TTMP_512RegClassID: 669 shift = 2; 670 break; 671 // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in 672 // this bundle? 673 default: 674 llvm_unreachable("unhandled register class"); 675 } 676 677 if (Val % (1 << shift)) { 678 *CommentStream << "Warning: " << getRegClassName(SRegClassID) 679 << ": scalar reg isn't aligned " << Val; 680 } 681 682 return createRegOperand(SRegClassID, Val >> shift); 683 } 684 685 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const { 686 return decodeSrcOp(OPW32, Val); 687 } 688 689 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const { 690 return decodeSrcOp(OPW64, Val); 691 } 692 693 MCOperand AMDGPUDisassembler::decodeOperand_VS_128(unsigned Val) const { 694 return decodeSrcOp(OPW128, Val); 695 } 696 697 MCOperand AMDGPUDisassembler::decodeOperand_VSrc16(unsigned Val) const { 698 return decodeSrcOp(OPW16, Val); 699 } 700 701 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV216(unsigned Val) const { 702 return decodeSrcOp(OPWV216, Val); 703 } 704 705 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const { 706 // Some instructions have operand restrictions beyond what the encoding 707 // allows. Some ordinarily VSrc_32 operands are VGPR_32, so clear the extra 708 // high bit. 709 Val &= 255; 710 711 return createRegOperand(AMDGPU::VGPR_32RegClassID, Val); 712 } 713 714 MCOperand AMDGPUDisassembler::decodeOperand_VRegOrLds_32(unsigned Val) const { 715 return decodeSrcOp(OPW32, Val); 716 } 717 718 MCOperand AMDGPUDisassembler::decodeOperand_AGPR_32(unsigned Val) const { 719 return createRegOperand(AMDGPU::AGPR_32RegClassID, Val & 255); 720 } 721 722 MCOperand AMDGPUDisassembler::decodeOperand_AReg_128(unsigned Val) const { 723 return createRegOperand(AMDGPU::AReg_128RegClassID, Val & 255); 724 } 725 726 MCOperand AMDGPUDisassembler::decodeOperand_AReg_512(unsigned Val) const { 727 return createRegOperand(AMDGPU::AReg_512RegClassID, Val & 255); 728 } 729 730 MCOperand AMDGPUDisassembler::decodeOperand_AReg_1024(unsigned Val) const { 731 return createRegOperand(AMDGPU::AReg_1024RegClassID, Val & 255); 732 } 733 734 MCOperand AMDGPUDisassembler::decodeOperand_AV_32(unsigned Val) const { 735 return decodeSrcOp(OPW32, Val); 736 } 737 738 MCOperand AMDGPUDisassembler::decodeOperand_AV_64(unsigned Val) const { 739 return decodeSrcOp(OPW64, Val); 740 } 741 742 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const { 743 return createRegOperand(AMDGPU::VReg_64RegClassID, Val); 744 } 745 746 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const { 747 return createRegOperand(AMDGPU::VReg_96RegClassID, Val); 748 } 749 750 MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const { 751 return createRegOperand(AMDGPU::VReg_128RegClassID, Val); 752 } 753 754 MCOperand AMDGPUDisassembler::decodeOperand_VReg_256(unsigned Val) const { 755 return createRegOperand(AMDGPU::VReg_256RegClassID, Val); 756 } 757 758 MCOperand AMDGPUDisassembler::decodeOperand_VReg_512(unsigned Val) const { 759 return createRegOperand(AMDGPU::VReg_512RegClassID, Val); 760 } 761 762 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const { 763 // table-gen generated disassembler doesn't care about operand types 764 // leaving only registry class so SSrc_32 operand turns into SReg_32 765 // and therefore we accept immediates and literals here as well 766 return decodeSrcOp(OPW32, Val); 767 } 768 769 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0_XEXEC( 770 unsigned Val) const { 771 // SReg_32_XM0 is SReg_32 without M0 or EXEC_LO/EXEC_HI 772 return decodeOperand_SReg_32(Val); 773 } 774 775 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XEXEC_HI( 776 unsigned Val) const { 777 // SReg_32_XM0 is SReg_32 without EXEC_HI 778 return decodeOperand_SReg_32(Val); 779 } 780 781 MCOperand AMDGPUDisassembler::decodeOperand_SRegOrLds_32(unsigned Val) const { 782 // table-gen generated disassembler doesn't care about operand types 783 // leaving only registry class so SSrc_32 operand turns into SReg_32 784 // and therefore we accept immediates and literals here as well 785 return decodeSrcOp(OPW32, Val); 786 } 787 788 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const { 789 return decodeSrcOp(OPW64, Val); 790 } 791 792 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64_XEXEC(unsigned Val) const { 793 return decodeSrcOp(OPW64, Val); 794 } 795 796 MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const { 797 return decodeSrcOp(OPW128, Val); 798 } 799 800 MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const { 801 return decodeDstOp(OPW256, Val); 802 } 803 804 MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const { 805 return decodeDstOp(OPW512, Val); 806 } 807 808 MCOperand AMDGPUDisassembler::decodeLiteralConstant() const { 809 // For now all literal constants are supposed to be unsigned integer 810 // ToDo: deal with signed/unsigned 64-bit integer constants 811 // ToDo: deal with float/double constants 812 if (!HasLiteral) { 813 if (Bytes.size() < 4) { 814 return errOperand(0, "cannot read literal, inst bytes left " + 815 Twine(Bytes.size())); 816 } 817 HasLiteral = true; 818 Literal = eatBytes<uint32_t>(Bytes); 819 } 820 return MCOperand::createImm(Literal); 821 } 822 823 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) { 824 using namespace AMDGPU::EncValues; 825 826 assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX); 827 return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ? 828 (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) : 829 (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm))); 830 // Cast prevents negative overflow. 831 } 832 833 static int64_t getInlineImmVal32(unsigned Imm) { 834 switch (Imm) { 835 case 240: 836 return FloatToBits(0.5f); 837 case 241: 838 return FloatToBits(-0.5f); 839 case 242: 840 return FloatToBits(1.0f); 841 case 243: 842 return FloatToBits(-1.0f); 843 case 244: 844 return FloatToBits(2.0f); 845 case 245: 846 return FloatToBits(-2.0f); 847 case 246: 848 return FloatToBits(4.0f); 849 case 247: 850 return FloatToBits(-4.0f); 851 case 248: // 1 / (2 * PI) 852 return 0x3e22f983; 853 default: 854 llvm_unreachable("invalid fp inline imm"); 855 } 856 } 857 858 static int64_t getInlineImmVal64(unsigned Imm) { 859 switch (Imm) { 860 case 240: 861 return DoubleToBits(0.5); 862 case 241: 863 return DoubleToBits(-0.5); 864 case 242: 865 return DoubleToBits(1.0); 866 case 243: 867 return DoubleToBits(-1.0); 868 case 244: 869 return DoubleToBits(2.0); 870 case 245: 871 return DoubleToBits(-2.0); 872 case 246: 873 return DoubleToBits(4.0); 874 case 247: 875 return DoubleToBits(-4.0); 876 case 248: // 1 / (2 * PI) 877 return 0x3fc45f306dc9c882; 878 default: 879 llvm_unreachable("invalid fp inline imm"); 880 } 881 } 882 883 static int64_t getInlineImmVal16(unsigned Imm) { 884 switch (Imm) { 885 case 240: 886 return 0x3800; 887 case 241: 888 return 0xB800; 889 case 242: 890 return 0x3C00; 891 case 243: 892 return 0xBC00; 893 case 244: 894 return 0x4000; 895 case 245: 896 return 0xC000; 897 case 246: 898 return 0x4400; 899 case 247: 900 return 0xC400; 901 case 248: // 1 / (2 * PI) 902 return 0x3118; 903 default: 904 llvm_unreachable("invalid fp inline imm"); 905 } 906 } 907 908 MCOperand AMDGPUDisassembler::decodeFPImmed(OpWidthTy Width, unsigned Imm) { 909 assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN 910 && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX); 911 912 // ToDo: case 248: 1/(2*PI) - is allowed only on VI 913 switch (Width) { 914 case OPW32: 915 case OPW128: // splat constants 916 case OPW512: 917 case OPW1024: 918 return MCOperand::createImm(getInlineImmVal32(Imm)); 919 case OPW64: 920 return MCOperand::createImm(getInlineImmVal64(Imm)); 921 case OPW16: 922 case OPWV216: 923 return MCOperand::createImm(getInlineImmVal16(Imm)); 924 default: 925 llvm_unreachable("implement me"); 926 } 927 } 928 929 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const { 930 using namespace AMDGPU; 931 932 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 933 switch (Width) { 934 default: // fall 935 case OPW32: 936 case OPW16: 937 case OPWV216: 938 return VGPR_32RegClassID; 939 case OPW64: return VReg_64RegClassID; 940 case OPW128: return VReg_128RegClassID; 941 } 942 } 943 944 unsigned AMDGPUDisassembler::getAgprClassId(const OpWidthTy Width) const { 945 using namespace AMDGPU; 946 947 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 948 switch (Width) { 949 default: // fall 950 case OPW32: 951 case OPW16: 952 case OPWV216: 953 return AGPR_32RegClassID; 954 case OPW64: return AReg_64RegClassID; 955 case OPW128: return AReg_128RegClassID; 956 case OPW256: return AReg_256RegClassID; 957 case OPW512: return AReg_512RegClassID; 958 case OPW1024: return AReg_1024RegClassID; 959 } 960 } 961 962 963 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const { 964 using namespace AMDGPU; 965 966 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 967 switch (Width) { 968 default: // fall 969 case OPW32: 970 case OPW16: 971 case OPWV216: 972 return SGPR_32RegClassID; 973 case OPW64: return SGPR_64RegClassID; 974 case OPW128: return SGPR_128RegClassID; 975 case OPW256: return SGPR_256RegClassID; 976 case OPW512: return SGPR_512RegClassID; 977 } 978 } 979 980 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const { 981 using namespace AMDGPU; 982 983 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 984 switch (Width) { 985 default: // fall 986 case OPW32: 987 case OPW16: 988 case OPWV216: 989 return TTMP_32RegClassID; 990 case OPW64: return TTMP_64RegClassID; 991 case OPW128: return TTMP_128RegClassID; 992 case OPW256: return TTMP_256RegClassID; 993 case OPW512: return TTMP_512RegClassID; 994 } 995 } 996 997 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const { 998 using namespace AMDGPU::EncValues; 999 1000 unsigned TTmpMin = isGFX9Plus() ? TTMP_GFX9_GFX10_MIN : TTMP_VI_MIN; 1001 unsigned TTmpMax = isGFX9Plus() ? TTMP_GFX9_GFX10_MAX : TTMP_VI_MAX; 1002 1003 return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1; 1004 } 1005 1006 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val) const { 1007 using namespace AMDGPU::EncValues; 1008 1009 assert(Val < 1024); // enum10 1010 1011 bool IsAGPR = Val & 512; 1012 Val &= 511; 1013 1014 if (VGPR_MIN <= Val && Val <= VGPR_MAX) { 1015 return createRegOperand(IsAGPR ? getAgprClassId(Width) 1016 : getVgprClassId(Width), Val - VGPR_MIN); 1017 } 1018 if (Val <= SGPR_MAX) { 1019 assert(SGPR_MIN == 0); // "SGPR_MIN <= Val" is always true and causes compilation warning. 1020 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1021 } 1022 1023 int TTmpIdx = getTTmpIdx(Val); 1024 if (TTmpIdx >= 0) { 1025 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1026 } 1027 1028 if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX) 1029 return decodeIntImmed(Val); 1030 1031 if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX) 1032 return decodeFPImmed(Width, Val); 1033 1034 if (Val == LITERAL_CONST) 1035 return decodeLiteralConstant(); 1036 1037 switch (Width) { 1038 case OPW32: 1039 case OPW16: 1040 case OPWV216: 1041 return decodeSpecialReg32(Val); 1042 case OPW64: 1043 return decodeSpecialReg64(Val); 1044 default: 1045 llvm_unreachable("unexpected immediate type"); 1046 } 1047 } 1048 1049 MCOperand AMDGPUDisassembler::decodeDstOp(const OpWidthTy Width, unsigned Val) const { 1050 using namespace AMDGPU::EncValues; 1051 1052 assert(Val < 128); 1053 assert(Width == OPW256 || Width == OPW512); 1054 1055 if (Val <= SGPR_MAX) { 1056 assert(SGPR_MIN == 0); // "SGPR_MIN <= Val" is always true and causes compilation warning. 1057 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1058 } 1059 1060 int TTmpIdx = getTTmpIdx(Val); 1061 if (TTmpIdx >= 0) { 1062 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1063 } 1064 1065 llvm_unreachable("unknown dst register"); 1066 } 1067 1068 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { 1069 using namespace AMDGPU; 1070 1071 switch (Val) { 1072 case 102: return createRegOperand(FLAT_SCR_LO); 1073 case 103: return createRegOperand(FLAT_SCR_HI); 1074 case 104: return createRegOperand(XNACK_MASK_LO); 1075 case 105: return createRegOperand(XNACK_MASK_HI); 1076 case 106: return createRegOperand(VCC_LO); 1077 case 107: return createRegOperand(VCC_HI); 1078 case 108: return createRegOperand(TBA_LO); 1079 case 109: return createRegOperand(TBA_HI); 1080 case 110: return createRegOperand(TMA_LO); 1081 case 111: return createRegOperand(TMA_HI); 1082 case 124: return createRegOperand(M0); 1083 case 125: return createRegOperand(SGPR_NULL); 1084 case 126: return createRegOperand(EXEC_LO); 1085 case 127: return createRegOperand(EXEC_HI); 1086 case 235: return createRegOperand(SRC_SHARED_BASE); 1087 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1088 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1089 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1090 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1091 case 251: return createRegOperand(SRC_VCCZ); 1092 case 252: return createRegOperand(SRC_EXECZ); 1093 case 253: return createRegOperand(SRC_SCC); 1094 case 254: return createRegOperand(LDS_DIRECT); 1095 default: break; 1096 } 1097 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1098 } 1099 1100 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { 1101 using namespace AMDGPU; 1102 1103 switch (Val) { 1104 case 102: return createRegOperand(FLAT_SCR); 1105 case 104: return createRegOperand(XNACK_MASK); 1106 case 106: return createRegOperand(VCC); 1107 case 108: return createRegOperand(TBA); 1108 case 110: return createRegOperand(TMA); 1109 case 125: return createRegOperand(SGPR_NULL); 1110 case 126: return createRegOperand(EXEC); 1111 case 235: return createRegOperand(SRC_SHARED_BASE); 1112 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1113 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1114 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1115 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1116 case 251: return createRegOperand(SRC_VCCZ); 1117 case 252: return createRegOperand(SRC_EXECZ); 1118 case 253: return createRegOperand(SRC_SCC); 1119 default: break; 1120 } 1121 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1122 } 1123 1124 MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width, 1125 const unsigned Val) const { 1126 using namespace AMDGPU::SDWA; 1127 using namespace AMDGPU::EncValues; 1128 1129 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 1130 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 1131 // XXX: cast to int is needed to avoid stupid warning: 1132 // compare with unsigned is always true 1133 if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) && 1134 Val <= SDWA9EncValues::SRC_VGPR_MAX) { 1135 return createRegOperand(getVgprClassId(Width), 1136 Val - SDWA9EncValues::SRC_VGPR_MIN); 1137 } 1138 if (SDWA9EncValues::SRC_SGPR_MIN <= Val && 1139 Val <= (isGFX10Plus() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10 1140 : SDWA9EncValues::SRC_SGPR_MAX_SI)) { 1141 return createSRegOperand(getSgprClassId(Width), 1142 Val - SDWA9EncValues::SRC_SGPR_MIN); 1143 } 1144 if (SDWA9EncValues::SRC_TTMP_MIN <= Val && 1145 Val <= SDWA9EncValues::SRC_TTMP_MAX) { 1146 return createSRegOperand(getTtmpClassId(Width), 1147 Val - SDWA9EncValues::SRC_TTMP_MIN); 1148 } 1149 1150 const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN; 1151 1152 if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX) 1153 return decodeIntImmed(SVal); 1154 1155 if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX) 1156 return decodeFPImmed(Width, SVal); 1157 1158 return decodeSpecialReg32(SVal); 1159 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 1160 return createRegOperand(getVgprClassId(Width), Val); 1161 } 1162 llvm_unreachable("unsupported target"); 1163 } 1164 1165 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const { 1166 return decodeSDWASrc(OPW16, Val); 1167 } 1168 1169 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const { 1170 return decodeSDWASrc(OPW32, Val); 1171 } 1172 1173 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const { 1174 using namespace AMDGPU::SDWA; 1175 1176 assert((STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 1177 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) && 1178 "SDWAVopcDst should be present only on GFX9+"); 1179 1180 bool IsWave64 = STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64]; 1181 1182 if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) { 1183 Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK; 1184 1185 int TTmpIdx = getTTmpIdx(Val); 1186 if (TTmpIdx >= 0) { 1187 auto TTmpClsId = getTtmpClassId(IsWave64 ? OPW64 : OPW32); 1188 return createSRegOperand(TTmpClsId, TTmpIdx); 1189 } else if (Val > SGPR_MAX) { 1190 return IsWave64 ? decodeSpecialReg64(Val) 1191 : decodeSpecialReg32(Val); 1192 } else { 1193 return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val); 1194 } 1195 } else { 1196 return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO); 1197 } 1198 } 1199 1200 MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const { 1201 return STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ? 1202 decodeOperand_SReg_64(Val) : decodeOperand_SReg_32(Val); 1203 } 1204 1205 bool AMDGPUDisassembler::isVI() const { 1206 return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]; 1207 } 1208 1209 bool AMDGPUDisassembler::isGFX9() const { return AMDGPU::isGFX9(STI); } 1210 1211 bool AMDGPUDisassembler::isGFX9Plus() const { return AMDGPU::isGFX9Plus(STI); } 1212 1213 bool AMDGPUDisassembler::isGFX10() const { return AMDGPU::isGFX10(STI); } 1214 1215 bool AMDGPUDisassembler::isGFX10Plus() const { 1216 return AMDGPU::isGFX10Plus(STI); 1217 } 1218 1219 //===----------------------------------------------------------------------===// 1220 // AMDGPU specific symbol handling 1221 //===----------------------------------------------------------------------===// 1222 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1223 do { \ 1224 KdStream << Indent << DIRECTIVE " " \ 1225 << ((FourByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 1226 } while (0) 1227 1228 // NOLINTNEXTLINE(readability-identifier-naming) 1229 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1( 1230 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1231 using namespace amdhsa; 1232 StringRef Indent = "\t"; 1233 1234 // We cannot accurately backward compute #VGPRs used from 1235 // GRANULATED_WORKITEM_VGPR_COUNT. But we are concerned with getting the same 1236 // value of GRANULATED_WORKITEM_VGPR_COUNT in the reassembled binary. So we 1237 // simply calculate the inverse of what the assembler does. 1238 1239 uint32_t GranulatedWorkitemVGPRCount = 1240 (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT) >> 1241 COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT_SHIFT; 1242 1243 uint32_t NextFreeVGPR = (GranulatedWorkitemVGPRCount + 1) * 1244 AMDGPU::IsaInfo::getVGPREncodingGranule(&STI); 1245 1246 KdStream << Indent << ".amdhsa_next_free_vgpr " << NextFreeVGPR << '\n'; 1247 1248 // We cannot backward compute values used to calculate 1249 // GRANULATED_WAVEFRONT_SGPR_COUNT. Hence the original values for following 1250 // directives can't be computed: 1251 // .amdhsa_reserve_vcc 1252 // .amdhsa_reserve_flat_scratch 1253 // .amdhsa_reserve_xnack_mask 1254 // They take their respective default values if not specified in the assembly. 1255 // 1256 // GRANULATED_WAVEFRONT_SGPR_COUNT 1257 // = f(NEXT_FREE_SGPR + VCC + FLAT_SCRATCH + XNACK_MASK) 1258 // 1259 // We compute the inverse as though all directives apart from NEXT_FREE_SGPR 1260 // are set to 0. So while disassembling we consider that: 1261 // 1262 // GRANULATED_WAVEFRONT_SGPR_COUNT 1263 // = f(NEXT_FREE_SGPR + 0 + 0 + 0) 1264 // 1265 // The disassembler cannot recover the original values of those 3 directives. 1266 1267 uint32_t GranulatedWavefrontSGPRCount = 1268 (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT) >> 1269 COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT_SHIFT; 1270 1271 if (isGFX10Plus() && GranulatedWavefrontSGPRCount) 1272 return MCDisassembler::Fail; 1273 1274 uint32_t NextFreeSGPR = (GranulatedWavefrontSGPRCount + 1) * 1275 AMDGPU::IsaInfo::getSGPREncodingGranule(&STI); 1276 1277 KdStream << Indent << ".amdhsa_reserve_vcc " << 0 << '\n'; 1278 KdStream << Indent << ".amdhsa_reserve_flat_scratch " << 0 << '\n'; 1279 KdStream << Indent << ".amdhsa_reserve_xnack_mask " << 0 << '\n'; 1280 KdStream << Indent << ".amdhsa_next_free_sgpr " << NextFreeSGPR << "\n"; 1281 1282 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIORITY) 1283 return MCDisassembler::Fail; 1284 1285 PRINT_DIRECTIVE(".amdhsa_float_round_mode_32", 1286 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); 1287 PRINT_DIRECTIVE(".amdhsa_float_round_mode_16_64", 1288 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); 1289 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_32", 1290 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); 1291 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_16_64", 1292 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); 1293 1294 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIV) 1295 return MCDisassembler::Fail; 1296 1297 PRINT_DIRECTIVE(".amdhsa_dx10_clamp", COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP); 1298 1299 if (FourByteBuffer & COMPUTE_PGM_RSRC1_DEBUG_MODE) 1300 return MCDisassembler::Fail; 1301 1302 PRINT_DIRECTIVE(".amdhsa_ieee_mode", COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE); 1303 1304 if (FourByteBuffer & COMPUTE_PGM_RSRC1_BULKY) 1305 return MCDisassembler::Fail; 1306 1307 if (FourByteBuffer & COMPUTE_PGM_RSRC1_CDBG_USER) 1308 return MCDisassembler::Fail; 1309 1310 PRINT_DIRECTIVE(".amdhsa_fp16_overflow", COMPUTE_PGM_RSRC1_FP16_OVFL); 1311 1312 if (FourByteBuffer & COMPUTE_PGM_RSRC1_RESERVED0) 1313 return MCDisassembler::Fail; 1314 1315 if (isGFX10Plus()) { 1316 PRINT_DIRECTIVE(".amdhsa_workgroup_processor_mode", 1317 COMPUTE_PGM_RSRC1_WGP_MODE); 1318 PRINT_DIRECTIVE(".amdhsa_memory_ordered", COMPUTE_PGM_RSRC1_MEM_ORDERED); 1319 PRINT_DIRECTIVE(".amdhsa_forward_progress", COMPUTE_PGM_RSRC1_FWD_PROGRESS); 1320 } 1321 return MCDisassembler::Success; 1322 } 1323 1324 // NOLINTNEXTLINE(readability-identifier-naming) 1325 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2( 1326 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1327 using namespace amdhsa; 1328 StringRef Indent = "\t"; 1329 PRINT_DIRECTIVE( 1330 ".amdhsa_system_sgpr_private_segment_wavefront_offset", 1331 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1332 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_x", 1333 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); 1334 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_y", 1335 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); 1336 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_z", 1337 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); 1338 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_info", 1339 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); 1340 PRINT_DIRECTIVE(".amdhsa_system_vgpr_workitem_id", 1341 COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); 1342 1343 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_ADDRESS_WATCH) 1344 return MCDisassembler::Fail; 1345 1346 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_MEMORY) 1347 return MCDisassembler::Fail; 1348 1349 if (FourByteBuffer & COMPUTE_PGM_RSRC2_GRANULATED_LDS_SIZE) 1350 return MCDisassembler::Fail; 1351 1352 PRINT_DIRECTIVE( 1353 ".amdhsa_exception_fp_ieee_invalid_op", 1354 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); 1355 PRINT_DIRECTIVE(".amdhsa_exception_fp_denorm_src", 1356 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); 1357 PRINT_DIRECTIVE( 1358 ".amdhsa_exception_fp_ieee_div_zero", 1359 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); 1360 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_overflow", 1361 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); 1362 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_underflow", 1363 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); 1364 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_inexact", 1365 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); 1366 PRINT_DIRECTIVE(".amdhsa_exception_int_div_zero", 1367 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); 1368 1369 if (FourByteBuffer & COMPUTE_PGM_RSRC2_RESERVED0) 1370 return MCDisassembler::Fail; 1371 1372 return MCDisassembler::Success; 1373 } 1374 1375 #undef PRINT_DIRECTIVE 1376 1377 MCDisassembler::DecodeStatus 1378 AMDGPUDisassembler::decodeKernelDescriptorDirective( 1379 DataExtractor::Cursor &Cursor, ArrayRef<uint8_t> Bytes, 1380 raw_string_ostream &KdStream) const { 1381 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1382 do { \ 1383 KdStream << Indent << DIRECTIVE " " \ 1384 << ((TwoByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 1385 } while (0) 1386 1387 uint16_t TwoByteBuffer = 0; 1388 uint32_t FourByteBuffer = 0; 1389 uint64_t EightByteBuffer = 0; 1390 1391 StringRef ReservedBytes; 1392 StringRef Indent = "\t"; 1393 1394 assert(Bytes.size() == 64); 1395 DataExtractor DE(Bytes, /*IsLittleEndian=*/true, /*AddressSize=*/8); 1396 1397 switch (Cursor.tell()) { 1398 case amdhsa::GROUP_SEGMENT_FIXED_SIZE_OFFSET: 1399 FourByteBuffer = DE.getU32(Cursor); 1400 KdStream << Indent << ".amdhsa_group_segment_fixed_size " << FourByteBuffer 1401 << '\n'; 1402 return MCDisassembler::Success; 1403 1404 case amdhsa::PRIVATE_SEGMENT_FIXED_SIZE_OFFSET: 1405 FourByteBuffer = DE.getU32(Cursor); 1406 KdStream << Indent << ".amdhsa_private_segment_fixed_size " 1407 << FourByteBuffer << '\n'; 1408 return MCDisassembler::Success; 1409 1410 case amdhsa::RESERVED0_OFFSET: 1411 // 8 reserved bytes, must be 0. 1412 EightByteBuffer = DE.getU64(Cursor); 1413 if (EightByteBuffer) { 1414 return MCDisassembler::Fail; 1415 } 1416 return MCDisassembler::Success; 1417 1418 case amdhsa::KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET: 1419 // KERNEL_CODE_ENTRY_BYTE_OFFSET 1420 // So far no directive controls this for Code Object V3, so simply skip for 1421 // disassembly. 1422 DE.skip(Cursor, 8); 1423 return MCDisassembler::Success; 1424 1425 case amdhsa::RESERVED1_OFFSET: 1426 // 20 reserved bytes, must be 0. 1427 ReservedBytes = DE.getBytes(Cursor, 20); 1428 for (int I = 0; I < 20; ++I) { 1429 if (ReservedBytes[I] != 0) { 1430 return MCDisassembler::Fail; 1431 } 1432 } 1433 return MCDisassembler::Success; 1434 1435 case amdhsa::COMPUTE_PGM_RSRC3_OFFSET: 1436 // COMPUTE_PGM_RSRC3 1437 // - Only set for GFX10, GFX6-9 have this to be 0. 1438 // - Currently no directives directly control this. 1439 FourByteBuffer = DE.getU32(Cursor); 1440 if (!isGFX10Plus() && FourByteBuffer) { 1441 return MCDisassembler::Fail; 1442 } 1443 return MCDisassembler::Success; 1444 1445 case amdhsa::COMPUTE_PGM_RSRC1_OFFSET: 1446 FourByteBuffer = DE.getU32(Cursor); 1447 if (decodeCOMPUTE_PGM_RSRC1(FourByteBuffer, KdStream) == 1448 MCDisassembler::Fail) { 1449 return MCDisassembler::Fail; 1450 } 1451 return MCDisassembler::Success; 1452 1453 case amdhsa::COMPUTE_PGM_RSRC2_OFFSET: 1454 FourByteBuffer = DE.getU32(Cursor); 1455 if (decodeCOMPUTE_PGM_RSRC2(FourByteBuffer, KdStream) == 1456 MCDisassembler::Fail) { 1457 return MCDisassembler::Fail; 1458 } 1459 return MCDisassembler::Success; 1460 1461 case amdhsa::KERNEL_CODE_PROPERTIES_OFFSET: 1462 using namespace amdhsa; 1463 TwoByteBuffer = DE.getU16(Cursor); 1464 1465 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_buffer", 1466 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); 1467 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_ptr", 1468 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); 1469 PRINT_DIRECTIVE(".amdhsa_user_sgpr_queue_ptr", 1470 KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); 1471 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_segment_ptr", 1472 KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); 1473 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_id", 1474 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); 1475 PRINT_DIRECTIVE(".amdhsa_user_sgpr_flat_scratch_init", 1476 KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); 1477 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_size", 1478 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); 1479 1480 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED0) 1481 return MCDisassembler::Fail; 1482 1483 // Reserved for GFX9 1484 if (isGFX9() && 1485 (TwoByteBuffer & KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32)) { 1486 return MCDisassembler::Fail; 1487 } else if (isGFX10Plus()) { 1488 PRINT_DIRECTIVE(".amdhsa_wavefront_size32", 1489 KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 1490 } 1491 1492 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED1) 1493 return MCDisassembler::Fail; 1494 1495 return MCDisassembler::Success; 1496 1497 case amdhsa::RESERVED2_OFFSET: 1498 // 6 bytes from here are reserved, must be 0. 1499 ReservedBytes = DE.getBytes(Cursor, 6); 1500 for (int I = 0; I < 6; ++I) { 1501 if (ReservedBytes[I] != 0) 1502 return MCDisassembler::Fail; 1503 } 1504 return MCDisassembler::Success; 1505 1506 default: 1507 llvm_unreachable("Unhandled index. Case statements cover everything."); 1508 return MCDisassembler::Fail; 1509 } 1510 #undef PRINT_DIRECTIVE 1511 } 1512 1513 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeKernelDescriptor( 1514 StringRef KdName, ArrayRef<uint8_t> Bytes, uint64_t KdAddress) const { 1515 // CP microcode requires the kernel descriptor to be 64 aligned. 1516 if (Bytes.size() != 64 || KdAddress % 64 != 0) 1517 return MCDisassembler::Fail; 1518 1519 std::string Kd; 1520 raw_string_ostream KdStream(Kd); 1521 KdStream << ".amdhsa_kernel " << KdName << '\n'; 1522 1523 DataExtractor::Cursor C(0); 1524 while (C && C.tell() < Bytes.size()) { 1525 MCDisassembler::DecodeStatus Status = 1526 decodeKernelDescriptorDirective(C, Bytes, KdStream); 1527 1528 cantFail(C.takeError()); 1529 1530 if (Status == MCDisassembler::Fail) 1531 return MCDisassembler::Fail; 1532 } 1533 KdStream << ".end_amdhsa_kernel\n"; 1534 outs() << KdStream.str(); 1535 return MCDisassembler::Success; 1536 } 1537 1538 Optional<MCDisassembler::DecodeStatus> 1539 AMDGPUDisassembler::onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, 1540 ArrayRef<uint8_t> Bytes, uint64_t Address, 1541 raw_ostream &CStream) const { 1542 // Right now only kernel descriptor needs to be handled. 1543 // We ignore all other symbols for target specific handling. 1544 // TODO: 1545 // Fix the spurious symbol issue for AMDGPU kernels. Exists for both Code 1546 // Object V2 and V3 when symbols are marked protected. 1547 1548 // amd_kernel_code_t for Code Object V2. 1549 if (Symbol.Type == ELF::STT_AMDGPU_HSA_KERNEL) { 1550 Size = 256; 1551 return MCDisassembler::Fail; 1552 } 1553 1554 // Code Object V3 kernel descriptors. 1555 StringRef Name = Symbol.Name; 1556 if (Symbol.Type == ELF::STT_OBJECT && Name.endswith(StringRef(".kd"))) { 1557 Size = 64; // Size = 64 regardless of success or failure. 1558 return decodeKernelDescriptor(Name.drop_back(3), Bytes, Address); 1559 } 1560 return None; 1561 } 1562 1563 //===----------------------------------------------------------------------===// 1564 // AMDGPUSymbolizer 1565 //===----------------------------------------------------------------------===// 1566 1567 // Try to find symbol name for specified label 1568 bool AMDGPUSymbolizer::tryAddingSymbolicOperand(MCInst &Inst, 1569 raw_ostream &/*cStream*/, int64_t Value, 1570 uint64_t /*Address*/, bool IsBranch, 1571 uint64_t /*Offset*/, uint64_t /*InstSize*/) { 1572 1573 if (!IsBranch) { 1574 return false; 1575 } 1576 1577 auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo); 1578 if (!Symbols) 1579 return false; 1580 1581 auto Result = llvm::find_if(*Symbols, [Value](const SymbolInfoTy &Val) { 1582 return Val.Addr == static_cast<uint64_t>(Value) && 1583 Val.Type == ELF::STT_NOTYPE; 1584 }); 1585 if (Result != Symbols->end()) { 1586 auto *Sym = Ctx.getOrCreateSymbol(Result->Name); 1587 const auto *Add = MCSymbolRefExpr::create(Sym, Ctx); 1588 Inst.addOperand(MCOperand::createExpr(Add)); 1589 return true; 1590 } 1591 return false; 1592 } 1593 1594 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream, 1595 int64_t Value, 1596 uint64_t Address) { 1597 llvm_unreachable("unimplemented"); 1598 } 1599 1600 //===----------------------------------------------------------------------===// 1601 // Initialization 1602 //===----------------------------------------------------------------------===// 1603 1604 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/, 1605 LLVMOpInfoCallback /*GetOpInfo*/, 1606 LLVMSymbolLookupCallback /*SymbolLookUp*/, 1607 void *DisInfo, 1608 MCContext *Ctx, 1609 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 1610 return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo); 1611 } 1612 1613 static MCDisassembler *createAMDGPUDisassembler(const Target &T, 1614 const MCSubtargetInfo &STI, 1615 MCContext &Ctx) { 1616 return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo()); 1617 } 1618 1619 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler() { 1620 TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(), 1621 createAMDGPUDisassembler); 1622 TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(), 1623 createAMDGPUSymbolizer); 1624 } 1625