1 //===-- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA --------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 //===----------------------------------------------------------------------===//
11 //
12 /// \file
13 ///
14 /// This file contains definition for AMDGPU ISA disassembler
15 //
16 //===----------------------------------------------------------------------===//
17 
18 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)?
19 
20 #include "AMDGPUDisassembler.h"
21 #include "AMDGPU.h"
22 #include "AMDGPURegisterInfo.h"
23 #include "SIDefines.h"
24 #include "Utils/AMDGPUBaseInfo.h"
25 
26 #include "llvm/MC/MCContext.h"
27 #include "llvm/MC/MCFixedLenDisassembler.h"
28 #include "llvm/MC/MCInst.h"
29 #include "llvm/MC/MCInstrDesc.h"
30 #include "llvm/MC/MCSubtargetInfo.h"
31 #include "llvm/Support/ELF.h"
32 #include "llvm/Support/Endian.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/TargetRegistry.h"
35 
36 
37 using namespace llvm;
38 
39 #define DEBUG_TYPE "amdgpu-disassembler"
40 
41 typedef llvm::MCDisassembler::DecodeStatus DecodeStatus;
42 
43 
44 inline static MCDisassembler::DecodeStatus
45 addOperand(MCInst &Inst, const MCOperand& Opnd) {
46   Inst.addOperand(Opnd);
47   return Opnd.isValid() ?
48     MCDisassembler::Success :
49     MCDisassembler::SoftFail;
50 }
51 
52 static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm,
53                                        uint64_t Addr, const void *Decoder) {
54   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
55 
56   APInt SignedOffset(18, Imm * 4, true);
57   int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue();
58 
59   if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2))
60     return MCDisassembler::Success;
61   return addOperand(Inst, MCOperand::createImm(Imm));
62 }
63 
64 #define DECODE_OPERAND2(RegClass, DecName) \
65 static DecodeStatus Decode##RegClass##RegisterClass(MCInst &Inst, \
66                                                     unsigned Imm, \
67                                                     uint64_t /*Addr*/, \
68                                                     const void *Decoder) { \
69   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); \
70   return addOperand(Inst, DAsm->decodeOperand_##DecName(Imm)); \
71 }
72 
73 #define DECODE_OPERAND(RegClass) DECODE_OPERAND2(RegClass, RegClass)
74 
75 DECODE_OPERAND(VGPR_32)
76 DECODE_OPERAND(VS_32)
77 DECODE_OPERAND(VS_64)
78 
79 DECODE_OPERAND(VReg_64)
80 DECODE_OPERAND(VReg_96)
81 DECODE_OPERAND(VReg_128)
82 
83 DECODE_OPERAND(SReg_32)
84 DECODE_OPERAND(SReg_32_XM0_XEXEC)
85 DECODE_OPERAND(SReg_64)
86 DECODE_OPERAND(SReg_64_XEXEC)
87 DECODE_OPERAND(SReg_128)
88 DECODE_OPERAND(SReg_256)
89 DECODE_OPERAND(SReg_512)
90 
91 #define GET_SUBTARGETINFO_ENUM
92 #include "AMDGPUGenSubtargetInfo.inc"
93 #undef GET_SUBTARGETINFO_ENUM
94 
95 #include "AMDGPUGenDisassemblerTables.inc"
96 
97 //===----------------------------------------------------------------------===//
98 //
99 //===----------------------------------------------------------------------===//
100 
101 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) {
102   assert(Bytes.size() >= sizeof(T));
103   const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data());
104   Bytes = Bytes.slice(sizeof(T));
105   return Res;
106 }
107 
108 DecodeStatus AMDGPUDisassembler::tryDecodeInst(const uint8_t* Table,
109                                                MCInst &MI,
110                                                uint64_t Inst,
111                                                uint64_t Address) const {
112   assert(MI.getOpcode() == 0);
113   assert(MI.getNumOperands() == 0);
114   MCInst TmpInst;
115   const auto SavedBytes = Bytes;
116   if (decodeInstruction(Table, TmpInst, Inst, Address, this, STI)) {
117     MI = TmpInst;
118     return MCDisassembler::Success;
119   }
120   Bytes = SavedBytes;
121   return MCDisassembler::Fail;
122 }
123 
124 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
125                                                 ArrayRef<uint8_t> Bytes_,
126                                                 uint64_t Address,
127                                                 raw_ostream &WS,
128                                                 raw_ostream &CS) const {
129   CommentStream = &CS;
130 
131   // ToDo: AMDGPUDisassembler supports only VI ISA.
132   assert(AMDGPU::isVI(STI) && "Can disassemble only VI ISA.");
133 
134   const unsigned MaxInstBytesNum = (std::min)((size_t)8, Bytes_.size());
135   Bytes = Bytes_.slice(0, MaxInstBytesNum);
136 
137   DecodeStatus Res = MCDisassembler::Fail;
138   do {
139     // ToDo: better to switch encoding length using some bit predicate
140     // but it is unknown yet, so try all we can
141 
142     // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2
143     // encodings
144     if (Bytes.size() >= 8) {
145       const uint64_t QW = eatBytes<uint64_t>(Bytes);
146       Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address);
147       if (Res) break;
148 
149       Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address);
150       if (Res) break;
151     }
152 
153     // Reinitialize Bytes as DPP64 could have eaten too much
154     Bytes = Bytes_.slice(0, MaxInstBytesNum);
155 
156     // Try decode 32-bit instruction
157     if (Bytes.size() < 4) break;
158     const uint32_t DW = eatBytes<uint32_t>(Bytes);
159     Res = tryDecodeInst(DecoderTableVI32, MI, DW, Address);
160     if (Res) break;
161 
162     Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address);
163     if (Res) break;
164 
165     if (Bytes.size() < 4) break;
166     const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW;
167     Res = tryDecodeInst(DecoderTableVI64, MI, QW, Address);
168     if (Res) break;
169 
170     Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address);
171   } while (false);
172 
173   Size = Res ? (MaxInstBytesNum - Bytes.size()) : 0;
174   return Res;
175 }
176 
177 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const {
178   return getContext().getRegisterInfo()->
179     getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]);
180 }
181 
182 inline
183 MCOperand AMDGPUDisassembler::errOperand(unsigned V,
184                                          const Twine& ErrMsg) const {
185   *CommentStream << "Error: " + ErrMsg;
186 
187   // ToDo: add support for error operands to MCInst.h
188   // return MCOperand::createError(V);
189   return MCOperand();
190 }
191 
192 inline
193 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const {
194   return MCOperand::createReg(RegId);
195 }
196 
197 inline
198 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID,
199                                                unsigned Val) const {
200   const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID];
201   if (Val >= RegCl.getNumRegs())
202     return errOperand(Val, Twine(getRegClassName(RegClassID)) +
203                            ": unknown register " + Twine(Val));
204   return createRegOperand(RegCl.getRegister(Val));
205 }
206 
207 inline
208 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID,
209                                                 unsigned Val) const {
210   // ToDo: SI/CI have 104 SGPRs, VI - 102
211   // Valery: here we accepting as much as we can, let assembler sort it out
212   int shift = 0;
213   switch (SRegClassID) {
214   case AMDGPU::SGPR_32RegClassID:
215   case AMDGPU::TTMP_32RegClassID:
216     break;
217   case AMDGPU::SGPR_64RegClassID:
218   case AMDGPU::TTMP_64RegClassID:
219     shift = 1;
220     break;
221   case AMDGPU::SGPR_128RegClassID:
222   case AMDGPU::TTMP_128RegClassID:
223   // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in
224   // this bundle?
225   case AMDGPU::SReg_256RegClassID:
226   // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in
227   // this bundle?
228   case AMDGPU::SReg_512RegClassID:
229     shift = 2;
230     break;
231   // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in
232   // this bundle?
233   default:
234     llvm_unreachable("unhandled register class");
235   }
236 
237   if (Val % (1 << shift)) {
238     *CommentStream << "Warning: " << getRegClassName(SRegClassID)
239                    << ": scalar reg isn't aligned " << Val;
240   }
241 
242   return createRegOperand(SRegClassID, Val >> shift);
243 }
244 
245 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const {
246   return decodeSrcOp(OPW32, Val);
247 }
248 
249 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const {
250   return decodeSrcOp(OPW64, Val);
251 }
252 
253 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const {
254   // Some instructions have operand restrictions beyond what the encoding
255   // allows. Some ordinarily VSrc_32 operands are VGPR_32, so clear the extra
256   // high bit.
257   Val &= 255;
258 
259   return createRegOperand(AMDGPU::VGPR_32RegClassID, Val);
260 }
261 
262 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const {
263   return createRegOperand(AMDGPU::VReg_64RegClassID, Val);
264 }
265 
266 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const {
267   return createRegOperand(AMDGPU::VReg_96RegClassID, Val);
268 }
269 
270 MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const {
271   return createRegOperand(AMDGPU::VReg_128RegClassID, Val);
272 }
273 
274 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const {
275   // table-gen generated disassembler doesn't care about operand types
276   // leaving only registry class so SSrc_32 operand turns into SReg_32
277   // and therefore we accept immediates and literals here as well
278   return decodeSrcOp(OPW32, Val);
279 }
280 
281 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0_XEXEC(
282   unsigned Val) const {
283   // SReg_32_XM0 is SReg_32 without M0 or EXEC_LO/EXEC_HI
284   return decodeOperand_SReg_32(Val);
285 }
286 
287 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const {
288   return decodeSrcOp(OPW64, Val);
289 }
290 
291 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64_XEXEC(unsigned Val) const {
292   return decodeSrcOp(OPW64, Val);
293 }
294 
295 MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const {
296   return decodeSrcOp(OPW128, Val);
297 }
298 
299 MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const {
300   return createSRegOperand(AMDGPU::SReg_256RegClassID, Val);
301 }
302 
303 MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const {
304   return createSRegOperand(AMDGPU::SReg_512RegClassID, Val);
305 }
306 
307 
308 MCOperand AMDGPUDisassembler::decodeLiteralConstant() const {
309   // For now all literal constants are supposed to be unsigned integer
310   // ToDo: deal with signed/unsigned 64-bit integer constants
311   // ToDo: deal with float/double constants
312   if (Bytes.size() < 4)
313     return errOperand(0, "cannot read literal, inst bytes left " +
314                          Twine(Bytes.size()));
315   return MCOperand::createImm(eatBytes<uint32_t>(Bytes));
316 }
317 
318 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) {
319   using namespace AMDGPU::EncValues;
320   assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX);
321   return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ?
322     (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) :
323     (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm)));
324       // Cast prevents negative overflow.
325 }
326 
327 MCOperand AMDGPUDisassembler::decodeFPImmed(bool Is32, unsigned Imm) {
328   assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN
329       && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX);
330   // ToDo: case 248: 1/(2*PI) - is allowed only on VI
331   // ToDo: AMDGPUInstPrinter does not support 1/(2*PI). It consider 1/(2*PI) as
332   // literal constant.
333   float V = 0.0f;
334   switch (Imm) {
335   case 240: V =  0.5f; break;
336   case 241: V = -0.5f; break;
337   case 242: V =  1.0f; break;
338   case 243: V = -1.0f; break;
339   case 244: V =  2.0f; break;
340   case 245: V = -2.0f; break;
341   case 246: V =  4.0f; break;
342   case 247: V = -4.0f; break;
343   case 248: return MCOperand::createImm(Is32 ?         // 1/(2*PI)
344                                           0x3e22f983 :
345                                           0x3fc45f306dc9c882);
346   default: break;
347   }
348   return MCOperand::createImm(Is32? FloatToBits(V) : DoubleToBits(V));
349 }
350 
351 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const {
352   using namespace AMDGPU;
353   assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
354   switch (Width) {
355   default: // fall
356   case OPW32: return VGPR_32RegClassID;
357   case OPW64: return VReg_64RegClassID;
358   case OPW128: return VReg_128RegClassID;
359   }
360 }
361 
362 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const {
363   using namespace AMDGPU;
364   assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
365   switch (Width) {
366   default: // fall
367   case OPW32: return SGPR_32RegClassID;
368   case OPW64: return SGPR_64RegClassID;
369   case OPW128: return SGPR_128RegClassID;
370   }
371 }
372 
373 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const {
374   using namespace AMDGPU;
375   assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
376   switch (Width) {
377   default: // fall
378   case OPW32: return TTMP_32RegClassID;
379   case OPW64: return TTMP_64RegClassID;
380   case OPW128: return TTMP_128RegClassID;
381   }
382 }
383 
384 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val) const {
385   using namespace AMDGPU::EncValues;
386   assert(Val < 512); // enum9
387 
388   if (VGPR_MIN <= Val && Val <= VGPR_MAX) {
389     return createRegOperand(getVgprClassId(Width), Val - VGPR_MIN);
390   }
391   if (Val <= SGPR_MAX) {
392     assert(SGPR_MIN == 0); // "SGPR_MIN <= Val" is always true and causes compilation warning.
393     return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN);
394   }
395   if (TTMP_MIN <= Val && Val <= TTMP_MAX) {
396     return createSRegOperand(getTtmpClassId(Width), Val - TTMP_MIN);
397   }
398 
399   assert(Width == OPW32 || Width == OPW64);
400   const bool Is32 = (Width == OPW32);
401 
402   if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX)
403     return decodeIntImmed(Val);
404 
405   if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX)
406     return decodeFPImmed(Is32, Val);
407 
408   if (Val == LITERAL_CONST)
409     return decodeLiteralConstant();
410 
411   return Is32 ? decodeSpecialReg32(Val) : decodeSpecialReg64(Val);
412 }
413 
414 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const {
415   using namespace AMDGPU;
416   switch (Val) {
417   case 102: return createRegOperand(getMCReg(FLAT_SCR_LO, STI));
418   case 103: return createRegOperand(getMCReg(FLAT_SCR_HI, STI));
419     // ToDo: no support for xnack_mask_lo/_hi register
420   case 104:
421   case 105: break;
422   case 106: return createRegOperand(VCC_LO);
423   case 107: return createRegOperand(VCC_HI);
424   case 108: return createRegOperand(TBA_LO);
425   case 109: return createRegOperand(TBA_HI);
426   case 110: return createRegOperand(TMA_LO);
427   case 111: return createRegOperand(TMA_HI);
428   case 124: return createRegOperand(M0);
429   case 126: return createRegOperand(EXEC_LO);
430   case 127: return createRegOperand(EXEC_HI);
431     // ToDo: no support for vccz register
432   case 251: break;
433     // ToDo: no support for execz register
434   case 252: break;
435   case 253: return createRegOperand(SCC);
436   default: break;
437   }
438   return errOperand(Val, "unknown operand encoding " + Twine(Val));
439 }
440 
441 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const {
442   using namespace AMDGPU;
443   switch (Val) {
444   case 102: return createRegOperand(getMCReg(FLAT_SCR, STI));
445   case 106: return createRegOperand(VCC);
446   case 108: return createRegOperand(TBA);
447   case 110: return createRegOperand(TMA);
448   case 126: return createRegOperand(EXEC);
449   default: break;
450   }
451   return errOperand(Val, "unknown operand encoding " + Twine(Val));
452 }
453 
454 //===----------------------------------------------------------------------===//
455 // AMDGPUSymbolizer
456 //===----------------------------------------------------------------------===//
457 
458 // Try to find symbol name for specified label
459 bool AMDGPUSymbolizer::tryAddingSymbolicOperand(MCInst &Inst,
460                                 raw_ostream &/*cStream*/, int64_t Value,
461                                 uint64_t /*Address*/, bool IsBranch,
462                                 uint64_t /*Offset*/, uint64_t /*InstSize*/) {
463   typedef std::tuple<uint64_t, StringRef, uint8_t> SymbolInfoTy;
464   typedef std::vector<SymbolInfoTy> SectionSymbolsTy;
465 
466   if (!IsBranch) {
467     return false;
468   }
469 
470   auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo);
471   auto Result = std::find_if(Symbols->begin(), Symbols->end(),
472                              [Value](const SymbolInfoTy& Val) {
473                                 return std::get<0>(Val) == static_cast<uint64_t>(Value)
474                                     && std::get<2>(Val) == ELF::STT_NOTYPE;
475                              });
476   if (Result != Symbols->end()) {
477     auto *Sym = Ctx.getOrCreateSymbol(std::get<1>(*Result));
478     const auto *Add = MCSymbolRefExpr::create(Sym, Ctx);
479     Inst.addOperand(MCOperand::createExpr(Add));
480     return true;
481   }
482   return false;
483 }
484 
485 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream,
486                                                        int64_t Value,
487                                                        uint64_t Address) {
488   llvm_unreachable("unimplemented");
489 }
490 
491 //===----------------------------------------------------------------------===//
492 // Initialization
493 //===----------------------------------------------------------------------===//
494 
495 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/,
496                               LLVMOpInfoCallback /*GetOpInfo*/,
497                               LLVMSymbolLookupCallback /*SymbolLookUp*/,
498                               void *DisInfo,
499                               MCContext *Ctx,
500                               std::unique_ptr<MCRelocationInfo> &&RelInfo) {
501   return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo);
502 }
503 
504 static MCDisassembler *createAMDGPUDisassembler(const Target &T,
505                                                 const MCSubtargetInfo &STI,
506                                                 MCContext &Ctx) {
507   return new AMDGPUDisassembler(STI, Ctx);
508 }
509 
510 extern "C" void LLVMInitializeAMDGPUDisassembler() {
511   TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(),
512                                          createAMDGPUDisassembler);
513   TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(),
514                                        createAMDGPUSymbolizer);
515 }
516