1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //===----------------------------------------------------------------------===//
10 //
11 /// \file
12 ///
13 /// This file contains definition for AMDGPU ISA disassembler
14 //
15 //===----------------------------------------------------------------------===//
16 
17 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)?
18 
19 #include "Disassembler/AMDGPUDisassembler.h"
20 #include "AMDGPU.h"
21 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
22 #include "SIDefines.h"
23 #include "TargetInfo/AMDGPUTargetInfo.h"
24 #include "Utils/AMDGPUBaseInfo.h"
25 #include "llvm-c/Disassembler.h"
26 #include "llvm/ADT/APInt.h"
27 #include "llvm/ADT/ArrayRef.h"
28 #include "llvm/ADT/Twine.h"
29 #include "llvm/BinaryFormat/ELF.h"
30 #include "llvm/MC/MCAsmInfo.h"
31 #include "llvm/MC/MCContext.h"
32 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
33 #include "llvm/MC/MCExpr.h"
34 #include "llvm/MC/MCFixedLenDisassembler.h"
35 #include "llvm/MC/MCInst.h"
36 #include "llvm/MC/MCSubtargetInfo.h"
37 #include "llvm/Support/Endian.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/MathExtras.h"
40 #include "llvm/Support/TargetRegistry.h"
41 #include "llvm/Support/raw_ostream.h"
42 #include <algorithm>
43 #include <cassert>
44 #include <cstddef>
45 #include <cstdint>
46 #include <iterator>
47 #include <tuple>
48 #include <vector>
49 
50 using namespace llvm;
51 
52 #define DEBUG_TYPE "amdgpu-disassembler"
53 
54 #define SGPR_MAX (isGFX10() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \
55                             : AMDGPU::EncValues::SGPR_MAX_SI)
56 
57 using DecodeStatus = llvm::MCDisassembler::DecodeStatus;
58 
59 AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI,
60                                        MCContext &Ctx,
61                                        MCInstrInfo const *MCII) :
62   MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()),
63   TargetMaxInstBytes(Ctx.getAsmInfo()->getMaxInstLength(&STI)) {
64 
65   // ToDo: AMDGPUDisassembler supports only VI ISA.
66   if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding] && !isGFX10())
67     report_fatal_error("Disassembly not yet supported for subtarget");
68 }
69 
70 inline static MCDisassembler::DecodeStatus
71 addOperand(MCInst &Inst, const MCOperand& Opnd) {
72   Inst.addOperand(Opnd);
73   return Opnd.isValid() ?
74     MCDisassembler::Success :
75     MCDisassembler::Fail;
76 }
77 
78 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op,
79                                 uint16_t NameIdx) {
80   int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx);
81   if (OpIdx != -1) {
82     auto I = MI.begin();
83     std::advance(I, OpIdx);
84     MI.insert(I, Op);
85   }
86   return OpIdx;
87 }
88 
89 static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm,
90                                        uint64_t Addr, const void *Decoder) {
91   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
92 
93   // Our branches take a simm16, but we need two extra bits to account for the
94   // factor of 4.
95   APInt SignedOffset(18, Imm * 4, true);
96   int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue();
97 
98   if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2))
99     return MCDisassembler::Success;
100   return addOperand(Inst, MCOperand::createImm(Imm));
101 }
102 
103 static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm,
104                                      uint64_t Addr, const void *Decoder) {
105   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
106   int64_t Offset;
107   if (DAsm->isVI()) {         // VI supports 20-bit unsigned offsets.
108     Offset = Imm & 0xFFFFF;
109   } else {                    // GFX9+ supports 21-bit signed offsets.
110     Offset = SignExtend64<21>(Imm);
111   }
112   return addOperand(Inst, MCOperand::createImm(Offset));
113 }
114 
115 static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val,
116                                   uint64_t Addr, const void *Decoder) {
117   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
118   return addOperand(Inst, DAsm->decodeBoolReg(Val));
119 }
120 
121 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \
122 static DecodeStatus StaticDecoderName(MCInst &Inst, \
123                                        unsigned Imm, \
124                                        uint64_t /*Addr*/, \
125                                        const void *Decoder) { \
126   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); \
127   return addOperand(Inst, DAsm->DecoderName(Imm)); \
128 }
129 
130 #define DECODE_OPERAND_REG(RegClass) \
131 DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass)
132 
133 DECODE_OPERAND_REG(VGPR_32)
134 DECODE_OPERAND_REG(VRegOrLds_32)
135 DECODE_OPERAND_REG(VS_32)
136 DECODE_OPERAND_REG(VS_64)
137 DECODE_OPERAND_REG(VS_128)
138 
139 DECODE_OPERAND_REG(VReg_64)
140 DECODE_OPERAND_REG(VReg_96)
141 DECODE_OPERAND_REG(VReg_128)
142 
143 DECODE_OPERAND_REG(SReg_32)
144 DECODE_OPERAND_REG(SReg_32_XM0_XEXEC)
145 DECODE_OPERAND_REG(SReg_32_XEXEC_HI)
146 DECODE_OPERAND_REG(SRegOrLds_32)
147 DECODE_OPERAND_REG(SReg_64)
148 DECODE_OPERAND_REG(SReg_64_XEXEC)
149 DECODE_OPERAND_REG(SReg_128)
150 DECODE_OPERAND_REG(SReg_256)
151 DECODE_OPERAND_REG(SReg_512)
152 
153 DECODE_OPERAND_REG(AGPR_32)
154 DECODE_OPERAND_REG(AReg_128)
155 DECODE_OPERAND_REG(AReg_512)
156 DECODE_OPERAND_REG(AReg_1024)
157 DECODE_OPERAND_REG(AV_32)
158 DECODE_OPERAND_REG(AV_64)
159 
160 static DecodeStatus decodeOperand_VSrc16(MCInst &Inst,
161                                          unsigned Imm,
162                                          uint64_t Addr,
163                                          const void *Decoder) {
164   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
165   return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm));
166 }
167 
168 static DecodeStatus decodeOperand_VSrcV216(MCInst &Inst,
169                                          unsigned Imm,
170                                          uint64_t Addr,
171                                          const void *Decoder) {
172   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
173   return addOperand(Inst, DAsm->decodeOperand_VSrcV216(Imm));
174 }
175 
176 static DecodeStatus decodeOperand_VS_16(MCInst &Inst,
177                                         unsigned Imm,
178                                         uint64_t Addr,
179                                         const void *Decoder) {
180   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
181   return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm));
182 }
183 
184 static DecodeStatus decodeOperand_VS_32(MCInst &Inst,
185                                         unsigned Imm,
186                                         uint64_t Addr,
187                                         const void *Decoder) {
188   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
189   return addOperand(Inst, DAsm->decodeOperand_VS_32(Imm));
190 }
191 
192 static DecodeStatus decodeOperand_AReg_128(MCInst &Inst,
193                                            unsigned Imm,
194                                            uint64_t Addr,
195                                            const void *Decoder) {
196   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
197   return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm | 512));
198 }
199 
200 static DecodeStatus decodeOperand_AReg_512(MCInst &Inst,
201                                            unsigned Imm,
202                                            uint64_t Addr,
203                                            const void *Decoder) {
204   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
205   return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm | 512));
206 }
207 
208 static DecodeStatus decodeOperand_AReg_1024(MCInst &Inst,
209                                             unsigned Imm,
210                                             uint64_t Addr,
211                                             const void *Decoder) {
212   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
213   return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm | 512));
214 }
215 
216 static DecodeStatus decodeOperand_SReg_32(MCInst &Inst,
217                                           unsigned Imm,
218                                           uint64_t Addr,
219                                           const void *Decoder) {
220   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
221   return addOperand(Inst, DAsm->decodeOperand_SReg_32(Imm));
222 }
223 
224 static DecodeStatus decodeOperand_VGPR_32(MCInst &Inst,
225                                          unsigned Imm,
226                                          uint64_t Addr,
227                                          const void *Decoder) {
228   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
229   return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW32, Imm));
230 }
231 
232 #define DECODE_SDWA(DecName) \
233 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName)
234 
235 DECODE_SDWA(Src32)
236 DECODE_SDWA(Src16)
237 DECODE_SDWA(VopcDst)
238 
239 #include "AMDGPUGenDisassemblerTables.inc"
240 
241 //===----------------------------------------------------------------------===//
242 //
243 //===----------------------------------------------------------------------===//
244 
245 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) {
246   assert(Bytes.size() >= sizeof(T));
247   const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data());
248   Bytes = Bytes.slice(sizeof(T));
249   return Res;
250 }
251 
252 DecodeStatus AMDGPUDisassembler::tryDecodeInst(const uint8_t* Table,
253                                                MCInst &MI,
254                                                uint64_t Inst,
255                                                uint64_t Address) const {
256   assert(MI.getOpcode() == 0);
257   assert(MI.getNumOperands() == 0);
258   MCInst TmpInst;
259   HasLiteral = false;
260   const auto SavedBytes = Bytes;
261   if (decodeInstruction(Table, TmpInst, Inst, Address, this, STI)) {
262     MI = TmpInst;
263     return MCDisassembler::Success;
264   }
265   Bytes = SavedBytes;
266   return MCDisassembler::Fail;
267 }
268 
269 static bool isValidDPP8(const MCInst &MI) {
270   using namespace llvm::AMDGPU::DPP;
271   int FiIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::fi);
272   assert(FiIdx != -1);
273   if ((unsigned)FiIdx >= MI.getNumOperands())
274     return false;
275   unsigned Fi = MI.getOperand(FiIdx).getImm();
276   return Fi == DPP8_FI_0 || Fi == DPP8_FI_1;
277 }
278 
279 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
280                                                 ArrayRef<uint8_t> Bytes_,
281                                                 uint64_t Address,
282                                                 raw_ostream &CS) const {
283   CommentStream = &CS;
284   bool IsSDWA = false;
285 
286   unsigned MaxInstBytesNum = std::min((size_t)TargetMaxInstBytes, Bytes_.size());
287   Bytes = Bytes_.slice(0, MaxInstBytesNum);
288 
289   DecodeStatus Res = MCDisassembler::Fail;
290   do {
291     // ToDo: better to switch encoding length using some bit predicate
292     // but it is unknown yet, so try all we can
293 
294     // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2
295     // encodings
296     if (Bytes.size() >= 8) {
297       const uint64_t QW = eatBytes<uint64_t>(Bytes);
298 
299       Res = tryDecodeInst(DecoderTableDPP864, MI, QW, Address);
300       if (Res && convertDPP8Inst(MI) == MCDisassembler::Success)
301         break;
302 
303       MI = MCInst(); // clear
304 
305       Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address);
306       if (Res) break;
307 
308       Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address);
309       if (Res) { IsSDWA = true;  break; }
310 
311       Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address);
312       if (Res) { IsSDWA = true;  break; }
313 
314       Res = tryDecodeInst(DecoderTableSDWA1064, MI, QW, Address);
315       if (Res) { IsSDWA = true;  break; }
316 
317       if (STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem]) {
318         Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address);
319         if (Res)
320           break;
321       }
322 
323       // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and
324       // v_mad_mixhi_f16 for FMA variants. Try to decode using this special
325       // table first so we print the correct name.
326       if (STI.getFeatureBits()[AMDGPU::FeatureFmaMixInsts]) {
327         Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address);
328         if (Res)
329           break;
330       }
331     }
332 
333     // Reinitialize Bytes as DPP64 could have eaten too much
334     Bytes = Bytes_.slice(0, MaxInstBytesNum);
335 
336     // Try decode 32-bit instruction
337     if (Bytes.size() < 4) break;
338     const uint32_t DW = eatBytes<uint32_t>(Bytes);
339     Res = tryDecodeInst(DecoderTableGFX832, MI, DW, Address);
340     if (Res) break;
341 
342     Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address);
343     if (Res) break;
344 
345     Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address);
346     if (Res) break;
347 
348     Res = tryDecodeInst(DecoderTableGFX1032, MI, DW, Address);
349     if (Res) break;
350 
351     if (Bytes.size() < 4) break;
352     const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW;
353     Res = tryDecodeInst(DecoderTableGFX864, MI, QW, Address);
354     if (Res) break;
355 
356     Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address);
357     if (Res) break;
358 
359     Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address);
360     if (Res) break;
361 
362     Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address);
363   } while (false);
364 
365   if (Res && (MaxInstBytesNum - Bytes.size()) == 12 && (!HasLiteral ||
366         !(MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3))) {
367     MaxInstBytesNum = 8;
368     Bytes = Bytes_.slice(0, MaxInstBytesNum);
369     eatBytes<uint64_t>(Bytes);
370   }
371 
372   if (Res && (MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi ||
373               MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx6_gfx7 ||
374               MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx10 ||
375               MI.getOpcode() == AMDGPU::V_MAC_F16_e64_vi ||
376               MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_vi ||
377               MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_gfx10 ||
378               MI.getOpcode() == AMDGPU::V_FMAC_F16_e64_gfx10)) {
379     // Insert dummy unused src2_modifiers.
380     insertNamedMCOperand(MI, MCOperand::createImm(0),
381                          AMDGPU::OpName::src2_modifiers);
382   }
383 
384   if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) {
385     int VAddr0Idx =
386         AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0);
387     int RsrcIdx =
388         AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc);
389     unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1;
390     if (VAddr0Idx >= 0 && NSAArgs > 0) {
391       unsigned NSAWords = (NSAArgs + 3) / 4;
392       if (Bytes.size() < 4 * NSAWords) {
393         Res = MCDisassembler::Fail;
394       } else {
395         for (unsigned i = 0; i < NSAArgs; ++i) {
396           MI.insert(MI.begin() + VAddr0Idx + 1 + i,
397                     decodeOperand_VGPR_32(Bytes[i]));
398         }
399         Bytes = Bytes.slice(4 * NSAWords);
400       }
401     }
402 
403     if (Res)
404       Res = convertMIMGInst(MI);
405   }
406 
407   if (Res && IsSDWA)
408     Res = convertSDWAInst(MI);
409 
410   int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
411                                               AMDGPU::OpName::vdst_in);
412   if (VDstIn_Idx != -1) {
413     int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx,
414                            MCOI::OperandConstraint::TIED_TO);
415     if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx ||
416          !MI.getOperand(VDstIn_Idx).isReg() ||
417          MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) {
418       if (MI.getNumOperands() > (unsigned)VDstIn_Idx)
419         MI.erase(&MI.getOperand(VDstIn_Idx));
420       insertNamedMCOperand(MI,
421         MCOperand::createReg(MI.getOperand(Tied).getReg()),
422         AMDGPU::OpName::vdst_in);
423     }
424   }
425 
426   // if the opcode was not recognized we'll assume a Size of 4 bytes
427   // (unless there are fewer bytes left)
428   Size = Res ? (MaxInstBytesNum - Bytes.size())
429              : std::min((size_t)4, Bytes_.size());
430   return Res;
431 }
432 
433 DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const {
434   if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] ||
435       STI.getFeatureBits()[AMDGPU::FeatureGFX10]) {
436     if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst) != -1)
437       // VOPC - insert clamp
438       insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp);
439   } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) {
440     int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst);
441     if (SDst != -1) {
442       // VOPC - insert VCC register as sdst
443       insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC),
444                            AMDGPU::OpName::sdst);
445     } else {
446       // VOP1/2 - insert omod if present in instruction
447       insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod);
448     }
449   }
450   return MCDisassembler::Success;
451 }
452 
453 DecodeStatus AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const {
454   unsigned Opc = MI.getOpcode();
455   unsigned DescNumOps = MCII->get(Opc).getNumOperands();
456 
457   // Insert dummy unused src modifiers.
458   if (MI.getNumOperands() < DescNumOps &&
459       AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1)
460     insertNamedMCOperand(MI, MCOperand::createImm(0),
461                          AMDGPU::OpName::src0_modifiers);
462 
463   if (MI.getNumOperands() < DescNumOps &&
464       AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers) != -1)
465     insertNamedMCOperand(MI, MCOperand::createImm(0),
466                          AMDGPU::OpName::src1_modifiers);
467 
468   return isValidDPP8(MI) ? MCDisassembler::Success : MCDisassembler::SoftFail;
469 }
470 
471 // Note that before gfx10, the MIMG encoding provided no information about
472 // VADDR size. Consequently, decoded instructions always show address as if it
473 // has 1 dword, which could be not really so.
474 DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const {
475 
476   int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
477                                            AMDGPU::OpName::vdst);
478 
479   int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
480                                             AMDGPU::OpName::vdata);
481   int VAddr0Idx =
482       AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0);
483   int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
484                                             AMDGPU::OpName::dmask);
485 
486   int TFEIdx   = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
487                                             AMDGPU::OpName::tfe);
488   int D16Idx   = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
489                                             AMDGPU::OpName::d16);
490 
491   assert(VDataIdx != -1);
492   assert(DMaskIdx != -1);
493   assert(TFEIdx != -1);
494 
495   const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode());
496   bool IsAtomic = (VDstIdx != -1);
497   bool IsGather4 = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::Gather4;
498 
499   bool IsNSA = false;
500   unsigned AddrSize = Info->VAddrDwords;
501 
502   if (STI.getFeatureBits()[AMDGPU::FeatureGFX10]) {
503     unsigned DimIdx =
504         AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim);
505     const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode =
506         AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode);
507     const AMDGPU::MIMGDimInfo *Dim =
508         AMDGPU::getMIMGDimInfoByEncoding(MI.getOperand(DimIdx).getImm());
509 
510     AddrSize = BaseOpcode->NumExtraArgs +
511                (BaseOpcode->Gradients ? Dim->NumGradients : 0) +
512                (BaseOpcode->Coordinates ? Dim->NumCoords : 0) +
513                (BaseOpcode->LodOrClampOrMip ? 1 : 0);
514     IsNSA = Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA;
515     if (!IsNSA) {
516       if (AddrSize > 8)
517         AddrSize = 16;
518       else if (AddrSize > 4)
519         AddrSize = 8;
520     } else {
521       if (AddrSize > Info->VAddrDwords) {
522         // The NSA encoding does not contain enough operands for the combination
523         // of base opcode / dimension. Should this be an error?
524         return MCDisassembler::Success;
525       }
526     }
527   }
528 
529   unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf;
530   unsigned DstSize = IsGather4 ? 4 : std::max(countPopulation(DMask), 1u);
531 
532   bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm();
533   if (D16 && AMDGPU::hasPackedD16(STI)) {
534     DstSize = (DstSize + 1) / 2;
535   }
536 
537   // FIXME: Add tfe support
538   if (MI.getOperand(TFEIdx).getImm())
539     return MCDisassembler::Success;
540 
541   if (DstSize == Info->VDataDwords && AddrSize == Info->VAddrDwords)
542     return MCDisassembler::Success;
543 
544   int NewOpcode =
545       AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize);
546   if (NewOpcode == -1)
547     return MCDisassembler::Success;
548 
549   // Widen the register to the correct number of enabled channels.
550   unsigned NewVdata = AMDGPU::NoRegister;
551   if (DstSize != Info->VDataDwords) {
552     auto DataRCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass;
553 
554     // Get first subregister of VData
555     unsigned Vdata0 = MI.getOperand(VDataIdx).getReg();
556     unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0);
557     Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0;
558 
559     NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0,
560                                        &MRI.getRegClass(DataRCID));
561     if (NewVdata == AMDGPU::NoRegister) {
562       // It's possible to encode this such that the low register + enabled
563       // components exceeds the register count.
564       return MCDisassembler::Success;
565     }
566   }
567 
568   unsigned NewVAddr0 = AMDGPU::NoRegister;
569   if (STI.getFeatureBits()[AMDGPU::FeatureGFX10] && !IsNSA &&
570       AddrSize != Info->VAddrDwords) {
571     unsigned VAddr0 = MI.getOperand(VAddr0Idx).getReg();
572     unsigned VAddrSub0 = MRI.getSubReg(VAddr0, AMDGPU::sub0);
573     VAddr0 = (VAddrSub0 != 0) ? VAddrSub0 : VAddr0;
574 
575     auto AddrRCID = MCII->get(NewOpcode).OpInfo[VAddr0Idx].RegClass;
576     NewVAddr0 = MRI.getMatchingSuperReg(VAddr0, AMDGPU::sub0,
577                                         &MRI.getRegClass(AddrRCID));
578     if (NewVAddr0 == AMDGPU::NoRegister)
579       return MCDisassembler::Success;
580   }
581 
582   MI.setOpcode(NewOpcode);
583 
584   if (NewVdata != AMDGPU::NoRegister) {
585     MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata);
586 
587     if (IsAtomic) {
588       // Atomic operations have an additional operand (a copy of data)
589       MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata);
590     }
591   }
592 
593   if (NewVAddr0 != AMDGPU::NoRegister) {
594     MI.getOperand(VAddr0Idx) = MCOperand::createReg(NewVAddr0);
595   } else if (IsNSA) {
596     assert(AddrSize <= Info->VAddrDwords);
597     MI.erase(MI.begin() + VAddr0Idx + AddrSize,
598              MI.begin() + VAddr0Idx + Info->VAddrDwords);
599   }
600 
601   return MCDisassembler::Success;
602 }
603 
604 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const {
605   return getContext().getRegisterInfo()->
606     getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]);
607 }
608 
609 inline
610 MCOperand AMDGPUDisassembler::errOperand(unsigned V,
611                                          const Twine& ErrMsg) const {
612   *CommentStream << "Error: " + ErrMsg;
613 
614   // ToDo: add support for error operands to MCInst.h
615   // return MCOperand::createError(V);
616   return MCOperand();
617 }
618 
619 inline
620 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const {
621   return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI));
622 }
623 
624 inline
625 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID,
626                                                unsigned Val) const {
627   const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID];
628   if (Val >= RegCl.getNumRegs())
629     return errOperand(Val, Twine(getRegClassName(RegClassID)) +
630                            ": unknown register " + Twine(Val));
631   return createRegOperand(RegCl.getRegister(Val));
632 }
633 
634 inline
635 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID,
636                                                 unsigned Val) const {
637   // ToDo: SI/CI have 104 SGPRs, VI - 102
638   // Valery: here we accepting as much as we can, let assembler sort it out
639   int shift = 0;
640   switch (SRegClassID) {
641   case AMDGPU::SGPR_32RegClassID:
642   case AMDGPU::TTMP_32RegClassID:
643     break;
644   case AMDGPU::SGPR_64RegClassID:
645   case AMDGPU::TTMP_64RegClassID:
646     shift = 1;
647     break;
648   case AMDGPU::SGPR_128RegClassID:
649   case AMDGPU::TTMP_128RegClassID:
650   // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in
651   // this bundle?
652   case AMDGPU::SGPR_256RegClassID:
653   case AMDGPU::TTMP_256RegClassID:
654     // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in
655   // this bundle?
656   case AMDGPU::SGPR_512RegClassID:
657   case AMDGPU::TTMP_512RegClassID:
658     shift = 2;
659     break;
660   // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in
661   // this bundle?
662   default:
663     llvm_unreachable("unhandled register class");
664   }
665 
666   if (Val % (1 << shift)) {
667     *CommentStream << "Warning: " << getRegClassName(SRegClassID)
668                    << ": scalar reg isn't aligned " << Val;
669   }
670 
671   return createRegOperand(SRegClassID, Val >> shift);
672 }
673 
674 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const {
675   return decodeSrcOp(OPW32, Val);
676 }
677 
678 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const {
679   return decodeSrcOp(OPW64, Val);
680 }
681 
682 MCOperand AMDGPUDisassembler::decodeOperand_VS_128(unsigned Val) const {
683   return decodeSrcOp(OPW128, Val);
684 }
685 
686 MCOperand AMDGPUDisassembler::decodeOperand_VSrc16(unsigned Val) const {
687   return decodeSrcOp(OPW16, Val);
688 }
689 
690 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV216(unsigned Val) const {
691   return decodeSrcOp(OPWV216, Val);
692 }
693 
694 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const {
695   // Some instructions have operand restrictions beyond what the encoding
696   // allows. Some ordinarily VSrc_32 operands are VGPR_32, so clear the extra
697   // high bit.
698   Val &= 255;
699 
700   return createRegOperand(AMDGPU::VGPR_32RegClassID, Val);
701 }
702 
703 MCOperand AMDGPUDisassembler::decodeOperand_VRegOrLds_32(unsigned Val) const {
704   return decodeSrcOp(OPW32, Val);
705 }
706 
707 MCOperand AMDGPUDisassembler::decodeOperand_AGPR_32(unsigned Val) const {
708   return createRegOperand(AMDGPU::AGPR_32RegClassID, Val & 255);
709 }
710 
711 MCOperand AMDGPUDisassembler::decodeOperand_AReg_128(unsigned Val) const {
712   return createRegOperand(AMDGPU::AReg_128RegClassID, Val & 255);
713 }
714 
715 MCOperand AMDGPUDisassembler::decodeOperand_AReg_512(unsigned Val) const {
716   return createRegOperand(AMDGPU::AReg_512RegClassID, Val & 255);
717 }
718 
719 MCOperand AMDGPUDisassembler::decodeOperand_AReg_1024(unsigned Val) const {
720   return createRegOperand(AMDGPU::AReg_1024RegClassID, Val & 255);
721 }
722 
723 MCOperand AMDGPUDisassembler::decodeOperand_AV_32(unsigned Val) const {
724   return decodeSrcOp(OPW32, Val);
725 }
726 
727 MCOperand AMDGPUDisassembler::decodeOperand_AV_64(unsigned Val) const {
728   return decodeSrcOp(OPW64, Val);
729 }
730 
731 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const {
732   return createRegOperand(AMDGPU::VReg_64RegClassID, Val);
733 }
734 
735 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const {
736   return createRegOperand(AMDGPU::VReg_96RegClassID, Val);
737 }
738 
739 MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const {
740   return createRegOperand(AMDGPU::VReg_128RegClassID, Val);
741 }
742 
743 MCOperand AMDGPUDisassembler::decodeOperand_VReg_256(unsigned Val) const {
744   return createRegOperand(AMDGPU::VReg_256RegClassID, Val);
745 }
746 
747 MCOperand AMDGPUDisassembler::decodeOperand_VReg_512(unsigned Val) const {
748   return createRegOperand(AMDGPU::VReg_512RegClassID, Val);
749 }
750 
751 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const {
752   // table-gen generated disassembler doesn't care about operand types
753   // leaving only registry class so SSrc_32 operand turns into SReg_32
754   // and therefore we accept immediates and literals here as well
755   return decodeSrcOp(OPW32, Val);
756 }
757 
758 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0_XEXEC(
759   unsigned Val) const {
760   // SReg_32_XM0 is SReg_32 without M0 or EXEC_LO/EXEC_HI
761   return decodeOperand_SReg_32(Val);
762 }
763 
764 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XEXEC_HI(
765   unsigned Val) const {
766   // SReg_32_XM0 is SReg_32 without EXEC_HI
767   return decodeOperand_SReg_32(Val);
768 }
769 
770 MCOperand AMDGPUDisassembler::decodeOperand_SRegOrLds_32(unsigned Val) const {
771   // table-gen generated disassembler doesn't care about operand types
772   // leaving only registry class so SSrc_32 operand turns into SReg_32
773   // and therefore we accept immediates and literals here as well
774   return decodeSrcOp(OPW32, Val);
775 }
776 
777 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const {
778   return decodeSrcOp(OPW64, Val);
779 }
780 
781 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64_XEXEC(unsigned Val) const {
782   return decodeSrcOp(OPW64, Val);
783 }
784 
785 MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const {
786   return decodeSrcOp(OPW128, Val);
787 }
788 
789 MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const {
790   return decodeDstOp(OPW256, Val);
791 }
792 
793 MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const {
794   return decodeDstOp(OPW512, Val);
795 }
796 
797 MCOperand AMDGPUDisassembler::decodeLiteralConstant() const {
798   // For now all literal constants are supposed to be unsigned integer
799   // ToDo: deal with signed/unsigned 64-bit integer constants
800   // ToDo: deal with float/double constants
801   if (!HasLiteral) {
802     if (Bytes.size() < 4) {
803       return errOperand(0, "cannot read literal, inst bytes left " +
804                         Twine(Bytes.size()));
805     }
806     HasLiteral = true;
807     Literal = eatBytes<uint32_t>(Bytes);
808   }
809   return MCOperand::createImm(Literal);
810 }
811 
812 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) {
813   using namespace AMDGPU::EncValues;
814 
815   assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX);
816   return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ?
817     (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) :
818     (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm)));
819       // Cast prevents negative overflow.
820 }
821 
822 static int64_t getInlineImmVal32(unsigned Imm) {
823   switch (Imm) {
824   case 240:
825     return FloatToBits(0.5f);
826   case 241:
827     return FloatToBits(-0.5f);
828   case 242:
829     return FloatToBits(1.0f);
830   case 243:
831     return FloatToBits(-1.0f);
832   case 244:
833     return FloatToBits(2.0f);
834   case 245:
835     return FloatToBits(-2.0f);
836   case 246:
837     return FloatToBits(4.0f);
838   case 247:
839     return FloatToBits(-4.0f);
840   case 248: // 1 / (2 * PI)
841     return 0x3e22f983;
842   default:
843     llvm_unreachable("invalid fp inline imm");
844   }
845 }
846 
847 static int64_t getInlineImmVal64(unsigned Imm) {
848   switch (Imm) {
849   case 240:
850     return DoubleToBits(0.5);
851   case 241:
852     return DoubleToBits(-0.5);
853   case 242:
854     return DoubleToBits(1.0);
855   case 243:
856     return DoubleToBits(-1.0);
857   case 244:
858     return DoubleToBits(2.0);
859   case 245:
860     return DoubleToBits(-2.0);
861   case 246:
862     return DoubleToBits(4.0);
863   case 247:
864     return DoubleToBits(-4.0);
865   case 248: // 1 / (2 * PI)
866     return 0x3fc45f306dc9c882;
867   default:
868     llvm_unreachable("invalid fp inline imm");
869   }
870 }
871 
872 static int64_t getInlineImmVal16(unsigned Imm) {
873   switch (Imm) {
874   case 240:
875     return 0x3800;
876   case 241:
877     return 0xB800;
878   case 242:
879     return 0x3C00;
880   case 243:
881     return 0xBC00;
882   case 244:
883     return 0x4000;
884   case 245:
885     return 0xC000;
886   case 246:
887     return 0x4400;
888   case 247:
889     return 0xC400;
890   case 248: // 1 / (2 * PI)
891     return 0x3118;
892   default:
893     llvm_unreachable("invalid fp inline imm");
894   }
895 }
896 
897 MCOperand AMDGPUDisassembler::decodeFPImmed(OpWidthTy Width, unsigned Imm) {
898   assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN
899       && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX);
900 
901   // ToDo: case 248: 1/(2*PI) - is allowed only on VI
902   switch (Width) {
903   case OPW32:
904   case OPW128: // splat constants
905   case OPW512:
906   case OPW1024:
907     return MCOperand::createImm(getInlineImmVal32(Imm));
908   case OPW64:
909     return MCOperand::createImm(getInlineImmVal64(Imm));
910   case OPW16:
911   case OPWV216:
912     return MCOperand::createImm(getInlineImmVal16(Imm));
913   default:
914     llvm_unreachable("implement me");
915   }
916 }
917 
918 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const {
919   using namespace AMDGPU;
920 
921   assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
922   switch (Width) {
923   default: // fall
924   case OPW32:
925   case OPW16:
926   case OPWV216:
927     return VGPR_32RegClassID;
928   case OPW64: return VReg_64RegClassID;
929   case OPW128: return VReg_128RegClassID;
930   }
931 }
932 
933 unsigned AMDGPUDisassembler::getAgprClassId(const OpWidthTy Width) const {
934   using namespace AMDGPU;
935 
936   assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
937   switch (Width) {
938   default: // fall
939   case OPW32:
940   case OPW16:
941   case OPWV216:
942     return AGPR_32RegClassID;
943   case OPW64: return AReg_64RegClassID;
944   case OPW128: return AReg_128RegClassID;
945   case OPW256: return AReg_256RegClassID;
946   case OPW512: return AReg_512RegClassID;
947   case OPW1024: return AReg_1024RegClassID;
948   }
949 }
950 
951 
952 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const {
953   using namespace AMDGPU;
954 
955   assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
956   switch (Width) {
957   default: // fall
958   case OPW32:
959   case OPW16:
960   case OPWV216:
961     return SGPR_32RegClassID;
962   case OPW64: return SGPR_64RegClassID;
963   case OPW128: return SGPR_128RegClassID;
964   case OPW256: return SGPR_256RegClassID;
965   case OPW512: return SGPR_512RegClassID;
966   }
967 }
968 
969 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const {
970   using namespace AMDGPU;
971 
972   assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
973   switch (Width) {
974   default: // fall
975   case OPW32:
976   case OPW16:
977   case OPWV216:
978     return TTMP_32RegClassID;
979   case OPW64: return TTMP_64RegClassID;
980   case OPW128: return TTMP_128RegClassID;
981   case OPW256: return TTMP_256RegClassID;
982   case OPW512: return TTMP_512RegClassID;
983   }
984 }
985 
986 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const {
987   using namespace AMDGPU::EncValues;
988 
989   unsigned TTmpMin =
990       (isGFX9() || isGFX10()) ? TTMP_GFX9_GFX10_MIN : TTMP_VI_MIN;
991   unsigned TTmpMax =
992       (isGFX9() || isGFX10()) ? TTMP_GFX9_GFX10_MAX : TTMP_VI_MAX;
993 
994   return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1;
995 }
996 
997 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val) const {
998   using namespace AMDGPU::EncValues;
999 
1000   assert(Val < 1024); // enum10
1001 
1002   bool IsAGPR = Val & 512;
1003   Val &= 511;
1004 
1005   if (VGPR_MIN <= Val && Val <= VGPR_MAX) {
1006     return createRegOperand(IsAGPR ? getAgprClassId(Width)
1007                                    : getVgprClassId(Width), Val - VGPR_MIN);
1008   }
1009   if (Val <= SGPR_MAX) {
1010     assert(SGPR_MIN == 0); // "SGPR_MIN <= Val" is always true and causes compilation warning.
1011     return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN);
1012   }
1013 
1014   int TTmpIdx = getTTmpIdx(Val);
1015   if (TTmpIdx >= 0) {
1016     return createSRegOperand(getTtmpClassId(Width), TTmpIdx);
1017   }
1018 
1019   if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX)
1020     return decodeIntImmed(Val);
1021 
1022   if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX)
1023     return decodeFPImmed(Width, Val);
1024 
1025   if (Val == LITERAL_CONST)
1026     return decodeLiteralConstant();
1027 
1028   switch (Width) {
1029   case OPW32:
1030   case OPW16:
1031   case OPWV216:
1032     return decodeSpecialReg32(Val);
1033   case OPW64:
1034     return decodeSpecialReg64(Val);
1035   default:
1036     llvm_unreachable("unexpected immediate type");
1037   }
1038 }
1039 
1040 MCOperand AMDGPUDisassembler::decodeDstOp(const OpWidthTy Width, unsigned Val) const {
1041   using namespace AMDGPU::EncValues;
1042 
1043   assert(Val < 128);
1044   assert(Width == OPW256 || Width == OPW512);
1045 
1046   if (Val <= SGPR_MAX) {
1047     assert(SGPR_MIN == 0); // "SGPR_MIN <= Val" is always true and causes compilation warning.
1048     return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN);
1049   }
1050 
1051   int TTmpIdx = getTTmpIdx(Val);
1052   if (TTmpIdx >= 0) {
1053     return createSRegOperand(getTtmpClassId(Width), TTmpIdx);
1054   }
1055 
1056   llvm_unreachable("unknown dst register");
1057 }
1058 
1059 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const {
1060   using namespace AMDGPU;
1061 
1062   switch (Val) {
1063   case 102: return createRegOperand(FLAT_SCR_LO);
1064   case 103: return createRegOperand(FLAT_SCR_HI);
1065   case 104: return createRegOperand(XNACK_MASK_LO);
1066   case 105: return createRegOperand(XNACK_MASK_HI);
1067   case 106: return createRegOperand(VCC_LO);
1068   case 107: return createRegOperand(VCC_HI);
1069   case 108: return createRegOperand(TBA_LO);
1070   case 109: return createRegOperand(TBA_HI);
1071   case 110: return createRegOperand(TMA_LO);
1072   case 111: return createRegOperand(TMA_HI);
1073   case 124: return createRegOperand(M0);
1074   case 125: return createRegOperand(SGPR_NULL);
1075   case 126: return createRegOperand(EXEC_LO);
1076   case 127: return createRegOperand(EXEC_HI);
1077   case 235: return createRegOperand(SRC_SHARED_BASE);
1078   case 236: return createRegOperand(SRC_SHARED_LIMIT);
1079   case 237: return createRegOperand(SRC_PRIVATE_BASE);
1080   case 238: return createRegOperand(SRC_PRIVATE_LIMIT);
1081   case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID);
1082   case 251: return createRegOperand(SRC_VCCZ);
1083   case 252: return createRegOperand(SRC_EXECZ);
1084   case 253: return createRegOperand(SRC_SCC);
1085   case 254: return createRegOperand(LDS_DIRECT);
1086   default: break;
1087   }
1088   return errOperand(Val, "unknown operand encoding " + Twine(Val));
1089 }
1090 
1091 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const {
1092   using namespace AMDGPU;
1093 
1094   switch (Val) {
1095   case 102: return createRegOperand(FLAT_SCR);
1096   case 104: return createRegOperand(XNACK_MASK);
1097   case 106: return createRegOperand(VCC);
1098   case 108: return createRegOperand(TBA);
1099   case 110: return createRegOperand(TMA);
1100   case 125: return createRegOperand(SGPR_NULL);
1101   case 126: return createRegOperand(EXEC);
1102   case 235: return createRegOperand(SRC_SHARED_BASE);
1103   case 236: return createRegOperand(SRC_SHARED_LIMIT);
1104   case 237: return createRegOperand(SRC_PRIVATE_BASE);
1105   case 238: return createRegOperand(SRC_PRIVATE_LIMIT);
1106   case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID);
1107   case 251: return createRegOperand(SRC_VCCZ);
1108   case 252: return createRegOperand(SRC_EXECZ);
1109   case 253: return createRegOperand(SRC_SCC);
1110   default: break;
1111   }
1112   return errOperand(Val, "unknown operand encoding " + Twine(Val));
1113 }
1114 
1115 MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width,
1116                                             const unsigned Val) const {
1117   using namespace AMDGPU::SDWA;
1118   using namespace AMDGPU::EncValues;
1119 
1120   if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] ||
1121       STI.getFeatureBits()[AMDGPU::FeatureGFX10]) {
1122     // XXX: cast to int is needed to avoid stupid warning:
1123     // compare with unsigned is always true
1124     if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) &&
1125         Val <= SDWA9EncValues::SRC_VGPR_MAX) {
1126       return createRegOperand(getVgprClassId(Width),
1127                               Val - SDWA9EncValues::SRC_VGPR_MIN);
1128     }
1129     if (SDWA9EncValues::SRC_SGPR_MIN <= Val &&
1130         Val <= (isGFX10() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10
1131                           : SDWA9EncValues::SRC_SGPR_MAX_SI)) {
1132       return createSRegOperand(getSgprClassId(Width),
1133                                Val - SDWA9EncValues::SRC_SGPR_MIN);
1134     }
1135     if (SDWA9EncValues::SRC_TTMP_MIN <= Val &&
1136         Val <= SDWA9EncValues::SRC_TTMP_MAX) {
1137       return createSRegOperand(getTtmpClassId(Width),
1138                                Val - SDWA9EncValues::SRC_TTMP_MIN);
1139     }
1140 
1141     const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN;
1142 
1143     if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX)
1144       return decodeIntImmed(SVal);
1145 
1146     if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX)
1147       return decodeFPImmed(Width, SVal);
1148 
1149     return decodeSpecialReg32(SVal);
1150   } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) {
1151     return createRegOperand(getVgprClassId(Width), Val);
1152   }
1153   llvm_unreachable("unsupported target");
1154 }
1155 
1156 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const {
1157   return decodeSDWASrc(OPW16, Val);
1158 }
1159 
1160 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const {
1161   return decodeSDWASrc(OPW32, Val);
1162 }
1163 
1164 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const {
1165   using namespace AMDGPU::SDWA;
1166 
1167   assert((STI.getFeatureBits()[AMDGPU::FeatureGFX9] ||
1168           STI.getFeatureBits()[AMDGPU::FeatureGFX10]) &&
1169          "SDWAVopcDst should be present only on GFX9+");
1170 
1171   bool IsWave64 = STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64];
1172 
1173   if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) {
1174     Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK;
1175 
1176     int TTmpIdx = getTTmpIdx(Val);
1177     if (TTmpIdx >= 0) {
1178       auto TTmpClsId = getTtmpClassId(IsWave64 ? OPW64 : OPW32);
1179       return createSRegOperand(TTmpClsId, TTmpIdx);
1180     } else if (Val > SGPR_MAX) {
1181       return IsWave64 ? decodeSpecialReg64(Val)
1182                       : decodeSpecialReg32(Val);
1183     } else {
1184       return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val);
1185     }
1186   } else {
1187     return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO);
1188   }
1189 }
1190 
1191 MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const {
1192   return STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ?
1193     decodeOperand_SReg_64(Val) : decodeOperand_SReg_32(Val);
1194 }
1195 
1196 bool AMDGPUDisassembler::isVI() const {
1197   return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands];
1198 }
1199 
1200 bool AMDGPUDisassembler::isGFX9() const {
1201   return STI.getFeatureBits()[AMDGPU::FeatureGFX9];
1202 }
1203 
1204 bool AMDGPUDisassembler::isGFX10() const {
1205   return STI.getFeatureBits()[AMDGPU::FeatureGFX10];
1206 }
1207 
1208 //===----------------------------------------------------------------------===//
1209 // AMDGPUSymbolizer
1210 //===----------------------------------------------------------------------===//
1211 
1212 // Try to find symbol name for specified label
1213 bool AMDGPUSymbolizer::tryAddingSymbolicOperand(MCInst &Inst,
1214                                 raw_ostream &/*cStream*/, int64_t Value,
1215                                 uint64_t /*Address*/, bool IsBranch,
1216                                 uint64_t /*Offset*/, uint64_t /*InstSize*/) {
1217 
1218   if (!IsBranch) {
1219     return false;
1220   }
1221 
1222   auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo);
1223   if (!Symbols)
1224     return false;
1225 
1226   auto Result = std::find_if(Symbols->begin(), Symbols->end(),
1227                              [Value](const SymbolInfoTy& Val) {
1228                                 return Val.Addr == static_cast<uint64_t>(Value)
1229                                     && Val.Type == ELF::STT_NOTYPE;
1230                              });
1231   if (Result != Symbols->end()) {
1232     auto *Sym = Ctx.getOrCreateSymbol(Result->Name);
1233     const auto *Add = MCSymbolRefExpr::create(Sym, Ctx);
1234     Inst.addOperand(MCOperand::createExpr(Add));
1235     return true;
1236   }
1237   return false;
1238 }
1239 
1240 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream,
1241                                                        int64_t Value,
1242                                                        uint64_t Address) {
1243   llvm_unreachable("unimplemented");
1244 }
1245 
1246 //===----------------------------------------------------------------------===//
1247 // Initialization
1248 //===----------------------------------------------------------------------===//
1249 
1250 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/,
1251                               LLVMOpInfoCallback /*GetOpInfo*/,
1252                               LLVMSymbolLookupCallback /*SymbolLookUp*/,
1253                               void *DisInfo,
1254                               MCContext *Ctx,
1255                               std::unique_ptr<MCRelocationInfo> &&RelInfo) {
1256   return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo);
1257 }
1258 
1259 static MCDisassembler *createAMDGPUDisassembler(const Target &T,
1260                                                 const MCSubtargetInfo &STI,
1261                                                 MCContext &Ctx) {
1262   return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo());
1263 }
1264 
1265 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler() {
1266   TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(),
1267                                          createAMDGPUDisassembler);
1268   TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(),
1269                                        createAMDGPUSymbolizer);
1270 }
1271