1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 //===----------------------------------------------------------------------===//
11 //
12 /// \file
13 ///
14 /// This file contains definition for AMDGPU ISA disassembler
15 //
16 //===----------------------------------------------------------------------===//
17 
18 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)?
19 
20 #include "Disassembler/AMDGPUDisassembler.h"
21 #include "AMDGPU.h"
22 #include "AMDGPURegisterInfo.h"
23 #include "SIDefines.h"
24 #include "Utils/AMDGPUBaseInfo.h"
25 #include "llvm-c/Disassembler.h"
26 #include "llvm/ADT/APInt.h"
27 #include "llvm/ADT/ArrayRef.h"
28 #include "llvm/ADT/Twine.h"
29 #include "llvm/BinaryFormat/ELF.h"
30 #include "llvm/MC/MCContext.h"
31 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
32 #include "llvm/MC/MCExpr.h"
33 #include "llvm/MC/MCFixedLenDisassembler.h"
34 #include "llvm/MC/MCInst.h"
35 #include "llvm/MC/MCSubtargetInfo.h"
36 #include "llvm/Support/Endian.h"
37 #include "llvm/Support/ErrorHandling.h"
38 #include "llvm/Support/MathExtras.h"
39 #include "llvm/Support/TargetRegistry.h"
40 #include "llvm/Support/raw_ostream.h"
41 #include <algorithm>
42 #include <cassert>
43 #include <cstddef>
44 #include <cstdint>
45 #include <iterator>
46 #include <tuple>
47 #include <vector>
48 
49 using namespace llvm;
50 
51 #define DEBUG_TYPE "amdgpu-disassembler"
52 
53 using DecodeStatus = llvm::MCDisassembler::DecodeStatus;
54 
55 inline static MCDisassembler::DecodeStatus
56 addOperand(MCInst &Inst, const MCOperand& Opnd) {
57   Inst.addOperand(Opnd);
58   return Opnd.isValid() ?
59     MCDisassembler::Success :
60     MCDisassembler::SoftFail;
61 }
62 
63 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op,
64                                 uint16_t NameIdx) {
65   int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx);
66   if (OpIdx != -1) {
67     auto I = MI.begin();
68     std::advance(I, OpIdx);
69     MI.insert(I, Op);
70   }
71   return OpIdx;
72 }
73 
74 static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm,
75                                        uint64_t Addr, const void *Decoder) {
76   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
77 
78   APInt SignedOffset(18, Imm * 4, true);
79   int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue();
80 
81   if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2))
82     return MCDisassembler::Success;
83   return addOperand(Inst, MCOperand::createImm(Imm));
84 }
85 
86 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \
87 static DecodeStatus StaticDecoderName(MCInst &Inst, \
88                                        unsigned Imm, \
89                                        uint64_t /*Addr*/, \
90                                        const void *Decoder) { \
91   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); \
92   return addOperand(Inst, DAsm->DecoderName(Imm)); \
93 }
94 
95 #define DECODE_OPERAND_REG(RegClass) \
96 DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass)
97 
98 DECODE_OPERAND_REG(VGPR_32)
99 DECODE_OPERAND_REG(VS_32)
100 DECODE_OPERAND_REG(VS_64)
101 DECODE_OPERAND_REG(VS_128)
102 
103 DECODE_OPERAND_REG(VReg_64)
104 DECODE_OPERAND_REG(VReg_96)
105 DECODE_OPERAND_REG(VReg_128)
106 
107 DECODE_OPERAND_REG(SReg_32)
108 DECODE_OPERAND_REG(SReg_32_XM0_XEXEC)
109 DECODE_OPERAND_REG(SReg_32_XEXEC_HI)
110 DECODE_OPERAND_REG(SReg_64)
111 DECODE_OPERAND_REG(SReg_64_XEXEC)
112 DECODE_OPERAND_REG(SReg_128)
113 DECODE_OPERAND_REG(SReg_256)
114 DECODE_OPERAND_REG(SReg_512)
115 
116 static DecodeStatus decodeOperand_VSrc16(MCInst &Inst,
117                                          unsigned Imm,
118                                          uint64_t Addr,
119                                          const void *Decoder) {
120   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
121   return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm));
122 }
123 
124 static DecodeStatus decodeOperand_VSrcV216(MCInst &Inst,
125                                          unsigned Imm,
126                                          uint64_t Addr,
127                                          const void *Decoder) {
128   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
129   return addOperand(Inst, DAsm->decodeOperand_VSrcV216(Imm));
130 }
131 
132 #define DECODE_SDWA(DecName) \
133 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName)
134 
135 DECODE_SDWA(Src32)
136 DECODE_SDWA(Src16)
137 DECODE_SDWA(VopcDst)
138 
139 #include "AMDGPUGenDisassemblerTables.inc"
140 
141 //===----------------------------------------------------------------------===//
142 //
143 //===----------------------------------------------------------------------===//
144 
145 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) {
146   assert(Bytes.size() >= sizeof(T));
147   const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data());
148   Bytes = Bytes.slice(sizeof(T));
149   return Res;
150 }
151 
152 DecodeStatus AMDGPUDisassembler::tryDecodeInst(const uint8_t* Table,
153                                                MCInst &MI,
154                                                uint64_t Inst,
155                                                uint64_t Address) const {
156   assert(MI.getOpcode() == 0);
157   assert(MI.getNumOperands() == 0);
158   MCInst TmpInst;
159   HasLiteral = false;
160   const auto SavedBytes = Bytes;
161   if (decodeInstruction(Table, TmpInst, Inst, Address, this, STI)) {
162     MI = TmpInst;
163     return MCDisassembler::Success;
164   }
165   Bytes = SavedBytes;
166   return MCDisassembler::Fail;
167 }
168 
169 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
170                                                 ArrayRef<uint8_t> Bytes_,
171                                                 uint64_t Address,
172                                                 raw_ostream &WS,
173                                                 raw_ostream &CS) const {
174   CommentStream = &CS;
175   bool IsSDWA = false;
176 
177   // ToDo: AMDGPUDisassembler supports only VI ISA.
178   if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding])
179     report_fatal_error("Disassembly not yet supported for subtarget");
180 
181   const unsigned MaxInstBytesNum = (std::min)((size_t)8, Bytes_.size());
182   Bytes = Bytes_.slice(0, MaxInstBytesNum);
183 
184   DecodeStatus Res = MCDisassembler::Fail;
185   do {
186     // ToDo: better to switch encoding length using some bit predicate
187     // but it is unknown yet, so try all we can
188 
189     // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2
190     // encodings
191     if (Bytes.size() >= 8) {
192       const uint64_t QW = eatBytes<uint64_t>(Bytes);
193       Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address);
194       if (Res) break;
195 
196       Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address);
197       if (Res) { IsSDWA = true;  break; }
198 
199       Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address);
200       if (Res) { IsSDWA = true;  break; }
201 
202       if (STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem]) {
203         Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address);
204         if (Res) break;
205       }
206     }
207 
208     // Reinitialize Bytes as DPP64 could have eaten too much
209     Bytes = Bytes_.slice(0, MaxInstBytesNum);
210 
211     // Try decode 32-bit instruction
212     if (Bytes.size() < 4) break;
213     const uint32_t DW = eatBytes<uint32_t>(Bytes);
214     Res = tryDecodeInst(DecoderTableVI32, MI, DW, Address);
215     if (Res) break;
216 
217     Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address);
218     if (Res) break;
219 
220     Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address);
221     if (Res) break;
222 
223     if (Bytes.size() < 4) break;
224     const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW;
225     Res = tryDecodeInst(DecoderTableVI64, MI, QW, Address);
226     if (Res) break;
227 
228     Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address);
229     if (Res) break;
230 
231     Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address);
232   } while (false);
233 
234   if (Res && (MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi ||
235               MI.getOpcode() == AMDGPU::V_MAC_F32_e64_si ||
236               MI.getOpcode() == AMDGPU::V_MAC_F16_e64_vi)) {
237     // Insert dummy unused src2_modifiers.
238     insertNamedMCOperand(MI, MCOperand::createImm(0),
239                          AMDGPU::OpName::src2_modifiers);
240   }
241 
242   if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) {
243     Res = convertMIMGInst(MI);
244   }
245 
246   if (Res && IsSDWA)
247     Res = convertSDWAInst(MI);
248 
249   Size = Res ? (MaxInstBytesNum - Bytes.size()) : 0;
250   return Res;
251 }
252 
253 DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const {
254   if (STI.getFeatureBits()[AMDGPU::FeatureGFX9]) {
255     if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst) != -1)
256       // VOPC - insert clamp
257       insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp);
258   } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) {
259     int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst);
260     if (SDst != -1) {
261       // VOPC - insert VCC register as sdst
262       insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC),
263                            AMDGPU::OpName::sdst);
264     } else {
265       // VOP1/2 - insert omod if present in instruction
266       insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod);
267     }
268   }
269   return MCDisassembler::Success;
270 }
271 
272 // Note that MIMG format provides no information about VADDR size.
273 // Consequently, decoded instructions always show address
274 // as if it has 1 dword, which could be not really so.
275 DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const {
276   int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
277                                            AMDGPU::OpName::vdst);
278 
279   int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
280                                             AMDGPU::OpName::vdata);
281 
282   int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
283                                             AMDGPU::OpName::dmask);
284 
285   int TFEIdx   = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
286                                             AMDGPU::OpName::tfe);
287 
288   assert(VDataIdx != -1);
289   assert(DMaskIdx != -1);
290   assert(TFEIdx != -1);
291 
292   bool isAtomic = (VDstIdx != -1);
293 
294   unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf;
295   if (DMask == 0)
296     return MCDisassembler::Success;
297 
298   unsigned DstSize = countPopulation(DMask);
299   if (DstSize == 1)
300     return MCDisassembler::Success;
301 
302   bool D16 = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::D16;
303   if (D16 && AMDGPU::hasPackedD16(STI)) {
304     DstSize = (DstSize + 1) / 2;
305   }
306 
307   // FIXME: Add tfe support
308   if (MI.getOperand(TFEIdx).getImm())
309     return MCDisassembler::Success;
310 
311   int NewOpcode = -1;
312 
313   if (isAtomic) {
314     if (DMask == 0x1 || DMask == 0x3 || DMask == 0xF) {
315       NewOpcode = AMDGPU::getMaskedMIMGAtomicOp(*MCII, MI.getOpcode(), DstSize);
316     }
317     if (NewOpcode == -1) return MCDisassembler::Success;
318   } else {
319     NewOpcode = AMDGPU::getMaskedMIMGOp(*MCII, MI.getOpcode(), DstSize);
320     assert(NewOpcode != -1 && "could not find matching mimg channel instruction");
321   }
322 
323   auto RCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass;
324 
325   // Get first subregister of VData
326   unsigned Vdata0 = MI.getOperand(VDataIdx).getReg();
327   unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0);
328   Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0;
329 
330   // Widen the register to the correct number of enabled channels.
331   auto NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0,
332                                           &MRI.getRegClass(RCID));
333   if (NewVdata == AMDGPU::NoRegister) {
334     // It's possible to encode this such that the low register + enabled
335     // components exceeds the register count.
336     return MCDisassembler::Success;
337   }
338 
339   MI.setOpcode(NewOpcode);
340   // vaddr will be always appear as a single VGPR. This will look different than
341   // how it is usually emitted because the number of register components is not
342   // in the instruction encoding.
343   MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata);
344 
345   if (isAtomic) {
346     // Atomic operations have an additional operand (a copy of data)
347     MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata);
348   }
349 
350   return MCDisassembler::Success;
351 }
352 
353 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const {
354   return getContext().getRegisterInfo()->
355     getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]);
356 }
357 
358 inline
359 MCOperand AMDGPUDisassembler::errOperand(unsigned V,
360                                          const Twine& ErrMsg) const {
361   *CommentStream << "Error: " + ErrMsg;
362 
363   // ToDo: add support for error operands to MCInst.h
364   // return MCOperand::createError(V);
365   return MCOperand();
366 }
367 
368 inline
369 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const {
370   return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI));
371 }
372 
373 inline
374 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID,
375                                                unsigned Val) const {
376   const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID];
377   if (Val >= RegCl.getNumRegs())
378     return errOperand(Val, Twine(getRegClassName(RegClassID)) +
379                            ": unknown register " + Twine(Val));
380   return createRegOperand(RegCl.getRegister(Val));
381 }
382 
383 inline
384 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID,
385                                                 unsigned Val) const {
386   // ToDo: SI/CI have 104 SGPRs, VI - 102
387   // Valery: here we accepting as much as we can, let assembler sort it out
388   int shift = 0;
389   switch (SRegClassID) {
390   case AMDGPU::SGPR_32RegClassID:
391   case AMDGPU::TTMP_32RegClassID:
392     break;
393   case AMDGPU::SGPR_64RegClassID:
394   case AMDGPU::TTMP_64RegClassID:
395     shift = 1;
396     break;
397   case AMDGPU::SGPR_128RegClassID:
398   case AMDGPU::TTMP_128RegClassID:
399   // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in
400   // this bundle?
401   case AMDGPU::SGPR_256RegClassID:
402   case AMDGPU::TTMP_256RegClassID:
403     // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in
404   // this bundle?
405   case AMDGPU::SGPR_512RegClassID:
406   case AMDGPU::TTMP_512RegClassID:
407     shift = 2;
408     break;
409   // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in
410   // this bundle?
411   default:
412     llvm_unreachable("unhandled register class");
413   }
414 
415   if (Val % (1 << shift)) {
416     *CommentStream << "Warning: " << getRegClassName(SRegClassID)
417                    << ": scalar reg isn't aligned " << Val;
418   }
419 
420   return createRegOperand(SRegClassID, Val >> shift);
421 }
422 
423 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const {
424   return decodeSrcOp(OPW32, Val);
425 }
426 
427 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const {
428   return decodeSrcOp(OPW64, Val);
429 }
430 
431 MCOperand AMDGPUDisassembler::decodeOperand_VS_128(unsigned Val) const {
432   return decodeSrcOp(OPW128, Val);
433 }
434 
435 MCOperand AMDGPUDisassembler::decodeOperand_VSrc16(unsigned Val) const {
436   return decodeSrcOp(OPW16, Val);
437 }
438 
439 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV216(unsigned Val) const {
440   return decodeSrcOp(OPWV216, Val);
441 }
442 
443 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const {
444   // Some instructions have operand restrictions beyond what the encoding
445   // allows. Some ordinarily VSrc_32 operands are VGPR_32, so clear the extra
446   // high bit.
447   Val &= 255;
448 
449   return createRegOperand(AMDGPU::VGPR_32RegClassID, Val);
450 }
451 
452 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const {
453   return createRegOperand(AMDGPU::VReg_64RegClassID, Val);
454 }
455 
456 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const {
457   return createRegOperand(AMDGPU::VReg_96RegClassID, Val);
458 }
459 
460 MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const {
461   return createRegOperand(AMDGPU::VReg_128RegClassID, Val);
462 }
463 
464 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const {
465   // table-gen generated disassembler doesn't care about operand types
466   // leaving only registry class so SSrc_32 operand turns into SReg_32
467   // and therefore we accept immediates and literals here as well
468   return decodeSrcOp(OPW32, Val);
469 }
470 
471 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0_XEXEC(
472   unsigned Val) const {
473   // SReg_32_XM0 is SReg_32 without M0 or EXEC_LO/EXEC_HI
474   return decodeOperand_SReg_32(Val);
475 }
476 
477 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XEXEC_HI(
478   unsigned Val) const {
479   // SReg_32_XM0 is SReg_32 without EXEC_HI
480   return decodeOperand_SReg_32(Val);
481 }
482 
483 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const {
484   return decodeSrcOp(OPW64, Val);
485 }
486 
487 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64_XEXEC(unsigned Val) const {
488   return decodeSrcOp(OPW64, Val);
489 }
490 
491 MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const {
492   return decodeSrcOp(OPW128, Val);
493 }
494 
495 MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const {
496   return decodeDstOp(OPW256, Val);
497 }
498 
499 MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const {
500   return decodeDstOp(OPW512, Val);
501 }
502 
503 MCOperand AMDGPUDisassembler::decodeLiteralConstant() const {
504   // For now all literal constants are supposed to be unsigned integer
505   // ToDo: deal with signed/unsigned 64-bit integer constants
506   // ToDo: deal with float/double constants
507   if (!HasLiteral) {
508     if (Bytes.size() < 4) {
509       return errOperand(0, "cannot read literal, inst bytes left " +
510                         Twine(Bytes.size()));
511     }
512     HasLiteral = true;
513     Literal = eatBytes<uint32_t>(Bytes);
514   }
515   return MCOperand::createImm(Literal);
516 }
517 
518 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) {
519   using namespace AMDGPU::EncValues;
520 
521   assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX);
522   return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ?
523     (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) :
524     (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm)));
525       // Cast prevents negative overflow.
526 }
527 
528 static int64_t getInlineImmVal32(unsigned Imm) {
529   switch (Imm) {
530   case 240:
531     return FloatToBits(0.5f);
532   case 241:
533     return FloatToBits(-0.5f);
534   case 242:
535     return FloatToBits(1.0f);
536   case 243:
537     return FloatToBits(-1.0f);
538   case 244:
539     return FloatToBits(2.0f);
540   case 245:
541     return FloatToBits(-2.0f);
542   case 246:
543     return FloatToBits(4.0f);
544   case 247:
545     return FloatToBits(-4.0f);
546   case 248: // 1 / (2 * PI)
547     return 0x3e22f983;
548   default:
549     llvm_unreachable("invalid fp inline imm");
550   }
551 }
552 
553 static int64_t getInlineImmVal64(unsigned Imm) {
554   switch (Imm) {
555   case 240:
556     return DoubleToBits(0.5);
557   case 241:
558     return DoubleToBits(-0.5);
559   case 242:
560     return DoubleToBits(1.0);
561   case 243:
562     return DoubleToBits(-1.0);
563   case 244:
564     return DoubleToBits(2.0);
565   case 245:
566     return DoubleToBits(-2.0);
567   case 246:
568     return DoubleToBits(4.0);
569   case 247:
570     return DoubleToBits(-4.0);
571   case 248: // 1 / (2 * PI)
572     return 0x3fc45f306dc9c882;
573   default:
574     llvm_unreachable("invalid fp inline imm");
575   }
576 }
577 
578 static int64_t getInlineImmVal16(unsigned Imm) {
579   switch (Imm) {
580   case 240:
581     return 0x3800;
582   case 241:
583     return 0xB800;
584   case 242:
585     return 0x3C00;
586   case 243:
587     return 0xBC00;
588   case 244:
589     return 0x4000;
590   case 245:
591     return 0xC000;
592   case 246:
593     return 0x4400;
594   case 247:
595     return 0xC400;
596   case 248: // 1 / (2 * PI)
597     return 0x3118;
598   default:
599     llvm_unreachable("invalid fp inline imm");
600   }
601 }
602 
603 MCOperand AMDGPUDisassembler::decodeFPImmed(OpWidthTy Width, unsigned Imm) {
604   assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN
605       && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX);
606 
607   // ToDo: case 248: 1/(2*PI) - is allowed only on VI
608   switch (Width) {
609   case OPW32:
610     return MCOperand::createImm(getInlineImmVal32(Imm));
611   case OPW64:
612     return MCOperand::createImm(getInlineImmVal64(Imm));
613   case OPW16:
614   case OPWV216:
615     return MCOperand::createImm(getInlineImmVal16(Imm));
616   default:
617     llvm_unreachable("implement me");
618   }
619 }
620 
621 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const {
622   using namespace AMDGPU;
623 
624   assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
625   switch (Width) {
626   default: // fall
627   case OPW32:
628   case OPW16:
629   case OPWV216:
630     return VGPR_32RegClassID;
631   case OPW64: return VReg_64RegClassID;
632   case OPW128: return VReg_128RegClassID;
633   }
634 }
635 
636 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const {
637   using namespace AMDGPU;
638 
639   assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
640   switch (Width) {
641   default: // fall
642   case OPW32:
643   case OPW16:
644   case OPWV216:
645     return SGPR_32RegClassID;
646   case OPW64: return SGPR_64RegClassID;
647   case OPW128: return SGPR_128RegClassID;
648   case OPW256: return SGPR_256RegClassID;
649   case OPW512: return SGPR_512RegClassID;
650   }
651 }
652 
653 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const {
654   using namespace AMDGPU;
655 
656   assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
657   switch (Width) {
658   default: // fall
659   case OPW32:
660   case OPW16:
661   case OPWV216:
662     return TTMP_32RegClassID;
663   case OPW64: return TTMP_64RegClassID;
664   case OPW128: return TTMP_128RegClassID;
665   case OPW256: return TTMP_256RegClassID;
666   case OPW512: return TTMP_512RegClassID;
667   }
668 }
669 
670 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const {
671   using namespace AMDGPU::EncValues;
672 
673   unsigned TTmpMin = isGFX9() ? TTMP_GFX9_MIN : TTMP_VI_MIN;
674   unsigned TTmpMax = isGFX9() ? TTMP_GFX9_MAX : TTMP_VI_MAX;
675 
676   return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1;
677 }
678 
679 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val) const {
680   using namespace AMDGPU::EncValues;
681 
682   assert(Val < 512); // enum9
683 
684   if (VGPR_MIN <= Val && Val <= VGPR_MAX) {
685     return createRegOperand(getVgprClassId(Width), Val - VGPR_MIN);
686   }
687   if (Val <= SGPR_MAX) {
688     assert(SGPR_MIN == 0); // "SGPR_MIN <= Val" is always true and causes compilation warning.
689     return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN);
690   }
691 
692   int TTmpIdx = getTTmpIdx(Val);
693   if (TTmpIdx >= 0) {
694     return createSRegOperand(getTtmpClassId(Width), TTmpIdx);
695   }
696 
697   if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX)
698     return decodeIntImmed(Val);
699 
700   if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX)
701     return decodeFPImmed(Width, Val);
702 
703   if (Val == LITERAL_CONST)
704     return decodeLiteralConstant();
705 
706   switch (Width) {
707   case OPW32:
708   case OPW16:
709   case OPWV216:
710     return decodeSpecialReg32(Val);
711   case OPW64:
712     return decodeSpecialReg64(Val);
713   default:
714     llvm_unreachable("unexpected immediate type");
715   }
716 }
717 
718 MCOperand AMDGPUDisassembler::decodeDstOp(const OpWidthTy Width, unsigned Val) const {
719   using namespace AMDGPU::EncValues;
720 
721   assert(Val < 128);
722   assert(Width == OPW256 || Width == OPW512);
723 
724   if (Val <= SGPR_MAX) {
725     assert(SGPR_MIN == 0); // "SGPR_MIN <= Val" is always true and causes compilation warning.
726     return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN);
727   }
728 
729   int TTmpIdx = getTTmpIdx(Val);
730   if (TTmpIdx >= 0) {
731     return createSRegOperand(getTtmpClassId(Width), TTmpIdx);
732   }
733 
734   llvm_unreachable("unknown dst register");
735 }
736 
737 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const {
738   using namespace AMDGPU;
739 
740   switch (Val) {
741   case 102: return createRegOperand(FLAT_SCR_LO);
742   case 103: return createRegOperand(FLAT_SCR_HI);
743   case 104: return createRegOperand(XNACK_MASK_LO);
744   case 105: return createRegOperand(XNACK_MASK_HI);
745   case 106: return createRegOperand(VCC_LO);
746   case 107: return createRegOperand(VCC_HI);
747   case 108: assert(!isGFX9()); return createRegOperand(TBA_LO);
748   case 109: assert(!isGFX9()); return createRegOperand(TBA_HI);
749   case 110: assert(!isGFX9()); return createRegOperand(TMA_LO);
750   case 111: assert(!isGFX9()); return createRegOperand(TMA_HI);
751   case 124: return createRegOperand(M0);
752   case 126: return createRegOperand(EXEC_LO);
753   case 127: return createRegOperand(EXEC_HI);
754   case 235: return createRegOperand(SRC_SHARED_BASE);
755   case 236: return createRegOperand(SRC_SHARED_LIMIT);
756   case 237: return createRegOperand(SRC_PRIVATE_BASE);
757   case 238: return createRegOperand(SRC_PRIVATE_LIMIT);
758     // TODO: SRC_POPS_EXITING_WAVE_ID
759     // ToDo: no support for vccz register
760   case 251: break;
761     // ToDo: no support for execz register
762   case 252: break;
763   case 253: return createRegOperand(SCC);
764   default: break;
765   }
766   return errOperand(Val, "unknown operand encoding " + Twine(Val));
767 }
768 
769 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const {
770   using namespace AMDGPU;
771 
772   switch (Val) {
773   case 102: return createRegOperand(FLAT_SCR);
774   case 104: return createRegOperand(XNACK_MASK);
775   case 106: return createRegOperand(VCC);
776   case 108: assert(!isGFX9()); return createRegOperand(TBA);
777   case 110: assert(!isGFX9()); return createRegOperand(TMA);
778   case 126: return createRegOperand(EXEC);
779   default: break;
780   }
781   return errOperand(Val, "unknown operand encoding " + Twine(Val));
782 }
783 
784 MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width,
785                                             const unsigned Val) const {
786   using namespace AMDGPU::SDWA;
787   using namespace AMDGPU::EncValues;
788 
789   if (STI.getFeatureBits()[AMDGPU::FeatureGFX9]) {
790     // XXX: static_cast<int> is needed to avoid stupid warning:
791     // compare with unsigned is always true
792     if (SDWA9EncValues::SRC_VGPR_MIN <= static_cast<int>(Val) &&
793         Val <= SDWA9EncValues::SRC_VGPR_MAX) {
794       return createRegOperand(getVgprClassId(Width),
795                               Val - SDWA9EncValues::SRC_VGPR_MIN);
796     }
797     if (SDWA9EncValues::SRC_SGPR_MIN <= Val &&
798         Val <= SDWA9EncValues::SRC_SGPR_MAX) {
799       return createSRegOperand(getSgprClassId(Width),
800                                Val - SDWA9EncValues::SRC_SGPR_MIN);
801     }
802     if (SDWA9EncValues::SRC_TTMP_MIN <= Val &&
803         Val <= SDWA9EncValues::SRC_TTMP_MAX) {
804       return createSRegOperand(getTtmpClassId(Width),
805                                Val - SDWA9EncValues::SRC_TTMP_MIN);
806     }
807 
808     const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN;
809 
810     if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX)
811       return decodeIntImmed(SVal);
812 
813     if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX)
814       return decodeFPImmed(Width, SVal);
815 
816     return decodeSpecialReg32(SVal);
817   } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) {
818     return createRegOperand(getVgprClassId(Width), Val);
819   }
820   llvm_unreachable("unsupported target");
821 }
822 
823 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const {
824   return decodeSDWASrc(OPW16, Val);
825 }
826 
827 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const {
828   return decodeSDWASrc(OPW32, Val);
829 }
830 
831 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const {
832   using namespace AMDGPU::SDWA;
833 
834   assert(STI.getFeatureBits()[AMDGPU::FeatureGFX9] &&
835          "SDWAVopcDst should be present only on GFX9");
836   if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) {
837     Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK;
838 
839     int TTmpIdx = getTTmpIdx(Val);
840     if (TTmpIdx >= 0) {
841       return createSRegOperand(getTtmpClassId(OPW64), TTmpIdx);
842     } else if (Val > AMDGPU::EncValues::SGPR_MAX) {
843       return decodeSpecialReg64(Val);
844     } else {
845       return createSRegOperand(getSgprClassId(OPW64), Val);
846     }
847   } else {
848     return createRegOperand(AMDGPU::VCC);
849   }
850 }
851 
852 bool AMDGPUDisassembler::isVI() const {
853   return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands];
854 }
855 
856 bool AMDGPUDisassembler::isGFX9() const {
857   return STI.getFeatureBits()[AMDGPU::FeatureGFX9];
858 }
859 
860 //===----------------------------------------------------------------------===//
861 // AMDGPUSymbolizer
862 //===----------------------------------------------------------------------===//
863 
864 // Try to find symbol name for specified label
865 bool AMDGPUSymbolizer::tryAddingSymbolicOperand(MCInst &Inst,
866                                 raw_ostream &/*cStream*/, int64_t Value,
867                                 uint64_t /*Address*/, bool IsBranch,
868                                 uint64_t /*Offset*/, uint64_t /*InstSize*/) {
869   using SymbolInfoTy = std::tuple<uint64_t, StringRef, uint8_t>;
870   using SectionSymbolsTy = std::vector<SymbolInfoTy>;
871 
872   if (!IsBranch) {
873     return false;
874   }
875 
876   auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo);
877   auto Result = std::find_if(Symbols->begin(), Symbols->end(),
878                              [Value](const SymbolInfoTy& Val) {
879                                 return std::get<0>(Val) == static_cast<uint64_t>(Value)
880                                     && std::get<2>(Val) == ELF::STT_NOTYPE;
881                              });
882   if (Result != Symbols->end()) {
883     auto *Sym = Ctx.getOrCreateSymbol(std::get<1>(*Result));
884     const auto *Add = MCSymbolRefExpr::create(Sym, Ctx);
885     Inst.addOperand(MCOperand::createExpr(Add));
886     return true;
887   }
888   return false;
889 }
890 
891 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream,
892                                                        int64_t Value,
893                                                        uint64_t Address) {
894   llvm_unreachable("unimplemented");
895 }
896 
897 //===----------------------------------------------------------------------===//
898 // Initialization
899 //===----------------------------------------------------------------------===//
900 
901 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/,
902                               LLVMOpInfoCallback /*GetOpInfo*/,
903                               LLVMSymbolLookupCallback /*SymbolLookUp*/,
904                               void *DisInfo,
905                               MCContext *Ctx,
906                               std::unique_ptr<MCRelocationInfo> &&RelInfo) {
907   return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo);
908 }
909 
910 static MCDisassembler *createAMDGPUDisassembler(const Target &T,
911                                                 const MCSubtargetInfo &STI,
912                                                 MCContext &Ctx) {
913   return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo());
914 }
915 
916 extern "C" void LLVMInitializeAMDGPUDisassembler() {
917   TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(),
918                                          createAMDGPUDisassembler);
919   TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(),
920                                        createAMDGPUSymbolizer);
921 }
922