1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 //===----------------------------------------------------------------------===//
11 //
12 /// \file
13 ///
14 /// This file contains definition for AMDGPU ISA disassembler
15 //
16 //===----------------------------------------------------------------------===//
17 
18 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)?
19 
20 #include "Disassembler/AMDGPUDisassembler.h"
21 #include "AMDGPU.h"
22 #include "AMDGPURegisterInfo.h"
23 #include "SIDefines.h"
24 #include "Utils/AMDGPUBaseInfo.h"
25 #include "llvm-c/Disassembler.h"
26 #include "llvm/ADT/APInt.h"
27 #include "llvm/ADT/ArrayRef.h"
28 #include "llvm/ADT/Twine.h"
29 #include "llvm/BinaryFormat/ELF.h"
30 #include "llvm/MC/MCContext.h"
31 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
32 #include "llvm/MC/MCExpr.h"
33 #include "llvm/MC/MCFixedLenDisassembler.h"
34 #include "llvm/MC/MCInst.h"
35 #include "llvm/MC/MCSubtargetInfo.h"
36 #include "llvm/Support/Endian.h"
37 #include "llvm/Support/ErrorHandling.h"
38 #include "llvm/Support/MathExtras.h"
39 #include "llvm/Support/TargetRegistry.h"
40 #include "llvm/Support/raw_ostream.h"
41 #include <algorithm>
42 #include <cassert>
43 #include <cstddef>
44 #include <cstdint>
45 #include <iterator>
46 #include <tuple>
47 #include <vector>
48 
49 using namespace llvm;
50 
51 #define DEBUG_TYPE "amdgpu-disassembler"
52 
53 using DecodeStatus = llvm::MCDisassembler::DecodeStatus;
54 
55 inline static MCDisassembler::DecodeStatus
56 addOperand(MCInst &Inst, const MCOperand& Opnd) {
57   Inst.addOperand(Opnd);
58   return Opnd.isValid() ?
59     MCDisassembler::Success :
60     MCDisassembler::SoftFail;
61 }
62 
63 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op,
64                                 uint16_t NameIdx) {
65   int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx);
66   if (OpIdx != -1) {
67     auto I = MI.begin();
68     std::advance(I, OpIdx);
69     MI.insert(I, Op);
70   }
71   return OpIdx;
72 }
73 
74 static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm,
75                                        uint64_t Addr, const void *Decoder) {
76   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
77 
78   APInt SignedOffset(18, Imm * 4, true);
79   int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue();
80 
81   if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2))
82     return MCDisassembler::Success;
83   return addOperand(Inst, MCOperand::createImm(Imm));
84 }
85 
86 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \
87 static DecodeStatus StaticDecoderName(MCInst &Inst, \
88                                        unsigned Imm, \
89                                        uint64_t /*Addr*/, \
90                                        const void *Decoder) { \
91   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); \
92   return addOperand(Inst, DAsm->DecoderName(Imm)); \
93 }
94 
95 #define DECODE_OPERAND_REG(RegClass) \
96 DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass)
97 
98 DECODE_OPERAND_REG(VGPR_32)
99 DECODE_OPERAND_REG(VS_32)
100 DECODE_OPERAND_REG(VS_64)
101 DECODE_OPERAND_REG(VS_128)
102 
103 DECODE_OPERAND_REG(VReg_64)
104 DECODE_OPERAND_REG(VReg_96)
105 DECODE_OPERAND_REG(VReg_128)
106 
107 DECODE_OPERAND_REG(SReg_32)
108 DECODE_OPERAND_REG(SReg_32_XM0_XEXEC)
109 DECODE_OPERAND_REG(SReg_32_XEXEC_HI)
110 DECODE_OPERAND_REG(SReg_64)
111 DECODE_OPERAND_REG(SReg_64_XEXEC)
112 DECODE_OPERAND_REG(SReg_128)
113 DECODE_OPERAND_REG(SReg_256)
114 DECODE_OPERAND_REG(SReg_512)
115 
116 static DecodeStatus decodeOperand_VSrc16(MCInst &Inst,
117                                          unsigned Imm,
118                                          uint64_t Addr,
119                                          const void *Decoder) {
120   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
121   return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm));
122 }
123 
124 static DecodeStatus decodeOperand_VSrcV216(MCInst &Inst,
125                                          unsigned Imm,
126                                          uint64_t Addr,
127                                          const void *Decoder) {
128   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
129   return addOperand(Inst, DAsm->decodeOperand_VSrcV216(Imm));
130 }
131 
132 #define DECODE_SDWA(DecName) \
133 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName)
134 
135 DECODE_SDWA(Src32)
136 DECODE_SDWA(Src16)
137 DECODE_SDWA(VopcDst)
138 
139 #include "AMDGPUGenDisassemblerTables.inc"
140 
141 //===----------------------------------------------------------------------===//
142 //
143 //===----------------------------------------------------------------------===//
144 
145 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) {
146   assert(Bytes.size() >= sizeof(T));
147   const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data());
148   Bytes = Bytes.slice(sizeof(T));
149   return Res;
150 }
151 
152 DecodeStatus AMDGPUDisassembler::tryDecodeInst(const uint8_t* Table,
153                                                MCInst &MI,
154                                                uint64_t Inst,
155                                                uint64_t Address) const {
156   assert(MI.getOpcode() == 0);
157   assert(MI.getNumOperands() == 0);
158   MCInst TmpInst;
159   HasLiteral = false;
160   const auto SavedBytes = Bytes;
161   if (decodeInstruction(Table, TmpInst, Inst, Address, this, STI)) {
162     MI = TmpInst;
163     return MCDisassembler::Success;
164   }
165   Bytes = SavedBytes;
166   return MCDisassembler::Fail;
167 }
168 
169 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
170                                                 ArrayRef<uint8_t> Bytes_,
171                                                 uint64_t Address,
172                                                 raw_ostream &WS,
173                                                 raw_ostream &CS) const {
174   CommentStream = &CS;
175   bool IsSDWA = false;
176 
177   // ToDo: AMDGPUDisassembler supports only VI ISA.
178   if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding])
179     report_fatal_error("Disassembly not yet supported for subtarget");
180 
181   const unsigned MaxInstBytesNum = (std::min)((size_t)8, Bytes_.size());
182   Bytes = Bytes_.slice(0, MaxInstBytesNum);
183 
184   DecodeStatus Res = MCDisassembler::Fail;
185   do {
186     // ToDo: better to switch encoding length using some bit predicate
187     // but it is unknown yet, so try all we can
188 
189     // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2
190     // encodings
191     if (Bytes.size() >= 8) {
192       const uint64_t QW = eatBytes<uint64_t>(Bytes);
193       Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address);
194       if (Res) break;
195 
196       Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address);
197       if (Res) { IsSDWA = true;  break; }
198 
199       Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address);
200       if (Res) { IsSDWA = true;  break; }
201     }
202 
203     // Reinitialize Bytes as DPP64 could have eaten too much
204     Bytes = Bytes_.slice(0, MaxInstBytesNum);
205 
206     // Try decode 32-bit instruction
207     if (Bytes.size() < 4) break;
208     const uint32_t DW = eatBytes<uint32_t>(Bytes);
209     Res = tryDecodeInst(DecoderTableVI32, MI, DW, Address);
210     if (Res) break;
211 
212     Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address);
213     if (Res) break;
214 
215     Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address);
216     if (Res) break;
217 
218     if (Bytes.size() < 4) break;
219     const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW;
220     Res = tryDecodeInst(DecoderTableVI64, MI, QW, Address);
221     if (Res) break;
222 
223     Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address);
224     if (Res) break;
225 
226     Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address);
227   } while (false);
228 
229   if (Res && (MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi ||
230               MI.getOpcode() == AMDGPU::V_MAC_F32_e64_si ||
231               MI.getOpcode() == AMDGPU::V_MAC_F16_e64_vi)) {
232     // Insert dummy unused src2_modifiers.
233     insertNamedMCOperand(MI, MCOperand::createImm(0),
234                          AMDGPU::OpName::src2_modifiers);
235   }
236 
237   if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) {
238     Res = convertMIMGInst(MI);
239   }
240 
241   if (Res && IsSDWA)
242     Res = convertSDWAInst(MI);
243 
244   Size = Res ? (MaxInstBytesNum - Bytes.size()) : 0;
245   return Res;
246 }
247 
248 DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const {
249   if (STI.getFeatureBits()[AMDGPU::FeatureGFX9]) {
250     if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst) != -1)
251       // VOPC - insert clamp
252       insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp);
253   } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) {
254     int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst);
255     if (SDst != -1) {
256       // VOPC - insert VCC register as sdst
257       insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC),
258                            AMDGPU::OpName::sdst);
259     } else {
260       // VOP1/2 - insert omod if present in instruction
261       insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod);
262     }
263   }
264   return MCDisassembler::Success;
265 }
266 
267 DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const {
268   int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
269                                             AMDGPU::OpName::vdata);
270 
271   int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
272                                             AMDGPU::OpName::dmask);
273   unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf;
274   if (DMask == 0)
275     return MCDisassembler::Success;
276 
277   unsigned ChannelCount = countPopulation(DMask);
278   if (ChannelCount == 1)
279     return MCDisassembler::Success;
280 
281   int NewOpcode = AMDGPU::getMaskedMIMGOp(*MCII, MI.getOpcode(), ChannelCount);
282   assert(NewOpcode != -1 && "could not find matching mimg channel instruction");
283   auto RCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass;
284 
285   // Widen the register to the correct number of enabled channels.
286   unsigned Vdata0 = MI.getOperand(VDataIdx).getReg();
287   auto NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0,
288                                           &MRI.getRegClass(RCID));
289   if (NewVdata == AMDGPU::NoRegister) {
290     // It's possible to encode this such that the low register + enabled
291     // components exceeds the register count.
292     return MCDisassembler::Success;
293   }
294 
295   MI.setOpcode(NewOpcode);
296   // vaddr will be always appear as a single VGPR. This will look different than
297   // how it is usually emitted because the number of register components is not
298   // in the instruction encoding.
299   MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata);
300   return MCDisassembler::Success;
301 }
302 
303 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const {
304   return getContext().getRegisterInfo()->
305     getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]);
306 }
307 
308 inline
309 MCOperand AMDGPUDisassembler::errOperand(unsigned V,
310                                          const Twine& ErrMsg) const {
311   *CommentStream << "Error: " + ErrMsg;
312 
313   // ToDo: add support for error operands to MCInst.h
314   // return MCOperand::createError(V);
315   return MCOperand();
316 }
317 
318 inline
319 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const {
320   return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI));
321 }
322 
323 inline
324 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID,
325                                                unsigned Val) const {
326   const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID];
327   if (Val >= RegCl.getNumRegs())
328     return errOperand(Val, Twine(getRegClassName(RegClassID)) +
329                            ": unknown register " + Twine(Val));
330   return createRegOperand(RegCl.getRegister(Val));
331 }
332 
333 inline
334 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID,
335                                                 unsigned Val) const {
336   // ToDo: SI/CI have 104 SGPRs, VI - 102
337   // Valery: here we accepting as much as we can, let assembler sort it out
338   int shift = 0;
339   switch (SRegClassID) {
340   case AMDGPU::SGPR_32RegClassID:
341   case AMDGPU::TTMP_32RegClassID:
342     break;
343   case AMDGPU::SGPR_64RegClassID:
344   case AMDGPU::TTMP_64RegClassID:
345     shift = 1;
346     break;
347   case AMDGPU::SGPR_128RegClassID:
348   case AMDGPU::TTMP_128RegClassID:
349   // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in
350   // this bundle?
351   case AMDGPU::SReg_256RegClassID:
352   // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in
353   // this bundle?
354   case AMDGPU::SReg_512RegClassID:
355     shift = 2;
356     break;
357   // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in
358   // this bundle?
359   default:
360     llvm_unreachable("unhandled register class");
361   }
362 
363   if (Val % (1 << shift)) {
364     *CommentStream << "Warning: " << getRegClassName(SRegClassID)
365                    << ": scalar reg isn't aligned " << Val;
366   }
367 
368   return createRegOperand(SRegClassID, Val >> shift);
369 }
370 
371 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const {
372   return decodeSrcOp(OPW32, Val);
373 }
374 
375 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const {
376   return decodeSrcOp(OPW64, Val);
377 }
378 
379 MCOperand AMDGPUDisassembler::decodeOperand_VS_128(unsigned Val) const {
380   return decodeSrcOp(OPW128, Val);
381 }
382 
383 MCOperand AMDGPUDisassembler::decodeOperand_VSrc16(unsigned Val) const {
384   return decodeSrcOp(OPW16, Val);
385 }
386 
387 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV216(unsigned Val) const {
388   return decodeSrcOp(OPWV216, Val);
389 }
390 
391 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const {
392   // Some instructions have operand restrictions beyond what the encoding
393   // allows. Some ordinarily VSrc_32 operands are VGPR_32, so clear the extra
394   // high bit.
395   Val &= 255;
396 
397   return createRegOperand(AMDGPU::VGPR_32RegClassID, Val);
398 }
399 
400 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const {
401   return createRegOperand(AMDGPU::VReg_64RegClassID, Val);
402 }
403 
404 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const {
405   return createRegOperand(AMDGPU::VReg_96RegClassID, Val);
406 }
407 
408 MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const {
409   return createRegOperand(AMDGPU::VReg_128RegClassID, Val);
410 }
411 
412 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const {
413   // table-gen generated disassembler doesn't care about operand types
414   // leaving only registry class so SSrc_32 operand turns into SReg_32
415   // and therefore we accept immediates and literals here as well
416   return decodeSrcOp(OPW32, Val);
417 }
418 
419 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0_XEXEC(
420   unsigned Val) const {
421   // SReg_32_XM0 is SReg_32 without M0 or EXEC_LO/EXEC_HI
422   return decodeOperand_SReg_32(Val);
423 }
424 
425 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XEXEC_HI(
426   unsigned Val) const {
427   // SReg_32_XM0 is SReg_32 without EXEC_HI
428   return decodeOperand_SReg_32(Val);
429 }
430 
431 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const {
432   return decodeSrcOp(OPW64, Val);
433 }
434 
435 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64_XEXEC(unsigned Val) const {
436   return decodeSrcOp(OPW64, Val);
437 }
438 
439 MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const {
440   return decodeSrcOp(OPW128, Val);
441 }
442 
443 MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const {
444   return createSRegOperand(AMDGPU::SReg_256RegClassID, Val);
445 }
446 
447 MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const {
448   return createSRegOperand(AMDGPU::SReg_512RegClassID, Val);
449 }
450 
451 MCOperand AMDGPUDisassembler::decodeLiteralConstant() const {
452   // For now all literal constants are supposed to be unsigned integer
453   // ToDo: deal with signed/unsigned 64-bit integer constants
454   // ToDo: deal with float/double constants
455   if (!HasLiteral) {
456     if (Bytes.size() < 4) {
457       return errOperand(0, "cannot read literal, inst bytes left " +
458                         Twine(Bytes.size()));
459     }
460     HasLiteral = true;
461     Literal = eatBytes<uint32_t>(Bytes);
462   }
463   return MCOperand::createImm(Literal);
464 }
465 
466 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) {
467   using namespace AMDGPU::EncValues;
468 
469   assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX);
470   return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ?
471     (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) :
472     (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm)));
473       // Cast prevents negative overflow.
474 }
475 
476 static int64_t getInlineImmVal32(unsigned Imm) {
477   switch (Imm) {
478   case 240:
479     return FloatToBits(0.5f);
480   case 241:
481     return FloatToBits(-0.5f);
482   case 242:
483     return FloatToBits(1.0f);
484   case 243:
485     return FloatToBits(-1.0f);
486   case 244:
487     return FloatToBits(2.0f);
488   case 245:
489     return FloatToBits(-2.0f);
490   case 246:
491     return FloatToBits(4.0f);
492   case 247:
493     return FloatToBits(-4.0f);
494   case 248: // 1 / (2 * PI)
495     return 0x3e22f983;
496   default:
497     llvm_unreachable("invalid fp inline imm");
498   }
499 }
500 
501 static int64_t getInlineImmVal64(unsigned Imm) {
502   switch (Imm) {
503   case 240:
504     return DoubleToBits(0.5);
505   case 241:
506     return DoubleToBits(-0.5);
507   case 242:
508     return DoubleToBits(1.0);
509   case 243:
510     return DoubleToBits(-1.0);
511   case 244:
512     return DoubleToBits(2.0);
513   case 245:
514     return DoubleToBits(-2.0);
515   case 246:
516     return DoubleToBits(4.0);
517   case 247:
518     return DoubleToBits(-4.0);
519   case 248: // 1 / (2 * PI)
520     return 0x3fc45f306dc9c882;
521   default:
522     llvm_unreachable("invalid fp inline imm");
523   }
524 }
525 
526 static int64_t getInlineImmVal16(unsigned Imm) {
527   switch (Imm) {
528   case 240:
529     return 0x3800;
530   case 241:
531     return 0xB800;
532   case 242:
533     return 0x3C00;
534   case 243:
535     return 0xBC00;
536   case 244:
537     return 0x4000;
538   case 245:
539     return 0xC000;
540   case 246:
541     return 0x4400;
542   case 247:
543     return 0xC400;
544   case 248: // 1 / (2 * PI)
545     return 0x3118;
546   default:
547     llvm_unreachable("invalid fp inline imm");
548   }
549 }
550 
551 MCOperand AMDGPUDisassembler::decodeFPImmed(OpWidthTy Width, unsigned Imm) {
552   assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN
553       && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX);
554 
555   // ToDo: case 248: 1/(2*PI) - is allowed only on VI
556   switch (Width) {
557   case OPW32:
558     return MCOperand::createImm(getInlineImmVal32(Imm));
559   case OPW64:
560     return MCOperand::createImm(getInlineImmVal64(Imm));
561   case OPW16:
562   case OPWV216:
563     return MCOperand::createImm(getInlineImmVal16(Imm));
564   default:
565     llvm_unreachable("implement me");
566   }
567 }
568 
569 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const {
570   using namespace AMDGPU;
571 
572   assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
573   switch (Width) {
574   default: // fall
575   case OPW32:
576   case OPW16:
577   case OPWV216:
578     return VGPR_32RegClassID;
579   case OPW64: return VReg_64RegClassID;
580   case OPW128: return VReg_128RegClassID;
581   }
582 }
583 
584 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const {
585   using namespace AMDGPU;
586 
587   assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
588   switch (Width) {
589   default: // fall
590   case OPW32:
591   case OPW16:
592   case OPWV216:
593     return SGPR_32RegClassID;
594   case OPW64: return SGPR_64RegClassID;
595   case OPW128: return SGPR_128RegClassID;
596   }
597 }
598 
599 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const {
600   using namespace AMDGPU;
601 
602   assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
603   switch (Width) {
604   default: // fall
605   case OPW32:
606   case OPW16:
607   case OPWV216:
608     return TTMP_32RegClassID;
609   case OPW64: return TTMP_64RegClassID;
610   case OPW128: return TTMP_128RegClassID;
611   }
612 }
613 
614 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const {
615   using namespace AMDGPU::EncValues;
616 
617   unsigned TTmpMin = isGFX9() ? TTMP_GFX9_MIN : TTMP_VI_MIN;
618   unsigned TTmpMax = isGFX9() ? TTMP_GFX9_MAX : TTMP_VI_MAX;
619 
620   return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1;
621 }
622 
623 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val) const {
624   using namespace AMDGPU::EncValues;
625 
626   assert(Val < 512); // enum9
627 
628   if (VGPR_MIN <= Val && Val <= VGPR_MAX) {
629     return createRegOperand(getVgprClassId(Width), Val - VGPR_MIN);
630   }
631   if (Val <= SGPR_MAX) {
632     assert(SGPR_MIN == 0); // "SGPR_MIN <= Val" is always true and causes compilation warning.
633     return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN);
634   }
635 
636   int TTmpIdx = getTTmpIdx(Val);
637   if (TTmpIdx >= 0) {
638     return createSRegOperand(getTtmpClassId(Width), TTmpIdx);
639   }
640 
641   if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX)
642     return decodeIntImmed(Val);
643 
644   if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX)
645     return decodeFPImmed(Width, Val);
646 
647   if (Val == LITERAL_CONST)
648     return decodeLiteralConstant();
649 
650   switch (Width) {
651   case OPW32:
652   case OPW16:
653   case OPWV216:
654     return decodeSpecialReg32(Val);
655   case OPW64:
656     return decodeSpecialReg64(Val);
657   default:
658     llvm_unreachable("unexpected immediate type");
659   }
660 }
661 
662 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const {
663   using namespace AMDGPU;
664 
665   switch (Val) {
666   case 102: return createRegOperand(FLAT_SCR_LO);
667   case 103: return createRegOperand(FLAT_SCR_HI);
668     // ToDo: no support for xnack_mask_lo/_hi register
669   case 104:
670   case 105: break;
671   case 106: return createRegOperand(VCC_LO);
672   case 107: return createRegOperand(VCC_HI);
673   case 108: assert(!isGFX9()); return createRegOperand(TBA_LO);
674   case 109: assert(!isGFX9()); return createRegOperand(TBA_HI);
675   case 110: assert(!isGFX9()); return createRegOperand(TMA_LO);
676   case 111: assert(!isGFX9()); return createRegOperand(TMA_HI);
677   case 124: return createRegOperand(M0);
678   case 126: return createRegOperand(EXEC_LO);
679   case 127: return createRegOperand(EXEC_HI);
680   case 235: return createRegOperand(SRC_SHARED_BASE);
681   case 236: return createRegOperand(SRC_SHARED_LIMIT);
682   case 237: return createRegOperand(SRC_PRIVATE_BASE);
683   case 238: return createRegOperand(SRC_PRIVATE_LIMIT);
684     // TODO: SRC_POPS_EXITING_WAVE_ID
685     // ToDo: no support for vccz register
686   case 251: break;
687     // ToDo: no support for execz register
688   case 252: break;
689   case 253: return createRegOperand(SCC);
690   default: break;
691   }
692   return errOperand(Val, "unknown operand encoding " + Twine(Val));
693 }
694 
695 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const {
696   using namespace AMDGPU;
697 
698   switch (Val) {
699   case 102: return createRegOperand(FLAT_SCR);
700   case 106: return createRegOperand(VCC);
701   case 108: assert(!isGFX9()); return createRegOperand(TBA);
702   case 110: assert(!isGFX9()); return createRegOperand(TMA);
703   case 126: return createRegOperand(EXEC);
704   default: break;
705   }
706   return errOperand(Val, "unknown operand encoding " + Twine(Val));
707 }
708 
709 MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width,
710                                             unsigned Val) const {
711   using namespace AMDGPU::SDWA;
712 
713   if (STI.getFeatureBits()[AMDGPU::FeatureGFX9]) {
714     // XXX: static_cast<int> is needed to avoid stupid warning:
715     // compare with unsigned is always true
716     if (SDWA9EncValues::SRC_VGPR_MIN <= static_cast<int>(Val) &&
717         Val <= SDWA9EncValues::SRC_VGPR_MAX) {
718       return createRegOperand(getVgprClassId(Width),
719                               Val - SDWA9EncValues::SRC_VGPR_MIN);
720     }
721     if (SDWA9EncValues::SRC_SGPR_MIN <= Val &&
722         Val <= SDWA9EncValues::SRC_SGPR_MAX) {
723       return createSRegOperand(getSgprClassId(Width),
724                                Val - SDWA9EncValues::SRC_SGPR_MIN);
725     }
726     if (SDWA9EncValues::SRC_TTMP_MIN <= Val &&
727         Val <= SDWA9EncValues::SRC_TTMP_MAX) {
728       return createSRegOperand(getTtmpClassId(Width),
729                                Val - SDWA9EncValues::SRC_TTMP_MIN);
730     }
731 
732     return decodeSpecialReg32(Val - SDWA9EncValues::SRC_SGPR_MIN);
733   } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) {
734     return createRegOperand(getVgprClassId(Width), Val);
735   }
736   llvm_unreachable("unsupported target");
737 }
738 
739 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const {
740   return decodeSDWASrc(OPW16, Val);
741 }
742 
743 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const {
744   return decodeSDWASrc(OPW32, Val);
745 }
746 
747 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const {
748   using namespace AMDGPU::SDWA;
749 
750   assert(STI.getFeatureBits()[AMDGPU::FeatureGFX9] &&
751          "SDWAVopcDst should be present only on GFX9");
752   if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) {
753     Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK;
754 
755     int TTmpIdx = getTTmpIdx(Val);
756     if (TTmpIdx >= 0) {
757       return createSRegOperand(getTtmpClassId(OPW64), TTmpIdx);
758     } else if (Val > AMDGPU::EncValues::SGPR_MAX) {
759       return decodeSpecialReg64(Val);
760     } else {
761       return createSRegOperand(getSgprClassId(OPW64), Val);
762     }
763   } else {
764     return createRegOperand(AMDGPU::VCC);
765   }
766 }
767 
768 bool AMDGPUDisassembler::isVI() const {
769   return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands];
770 }
771 
772 bool AMDGPUDisassembler::isGFX9() const {
773   return STI.getFeatureBits()[AMDGPU::FeatureGFX9];
774 }
775 
776 //===----------------------------------------------------------------------===//
777 // AMDGPUSymbolizer
778 //===----------------------------------------------------------------------===//
779 
780 // Try to find symbol name for specified label
781 bool AMDGPUSymbolizer::tryAddingSymbolicOperand(MCInst &Inst,
782                                 raw_ostream &/*cStream*/, int64_t Value,
783                                 uint64_t /*Address*/, bool IsBranch,
784                                 uint64_t /*Offset*/, uint64_t /*InstSize*/) {
785   using SymbolInfoTy = std::tuple<uint64_t, StringRef, uint8_t>;
786   using SectionSymbolsTy = std::vector<SymbolInfoTy>;
787 
788   if (!IsBranch) {
789     return false;
790   }
791 
792   auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo);
793   auto Result = std::find_if(Symbols->begin(), Symbols->end(),
794                              [Value](const SymbolInfoTy& Val) {
795                                 return std::get<0>(Val) == static_cast<uint64_t>(Value)
796                                     && std::get<2>(Val) == ELF::STT_NOTYPE;
797                              });
798   if (Result != Symbols->end()) {
799     auto *Sym = Ctx.getOrCreateSymbol(std::get<1>(*Result));
800     const auto *Add = MCSymbolRefExpr::create(Sym, Ctx);
801     Inst.addOperand(MCOperand::createExpr(Add));
802     return true;
803   }
804   return false;
805 }
806 
807 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream,
808                                                        int64_t Value,
809                                                        uint64_t Address) {
810   llvm_unreachable("unimplemented");
811 }
812 
813 //===----------------------------------------------------------------------===//
814 // Initialization
815 //===----------------------------------------------------------------------===//
816 
817 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/,
818                               LLVMOpInfoCallback /*GetOpInfo*/,
819                               LLVMSymbolLookupCallback /*SymbolLookUp*/,
820                               void *DisInfo,
821                               MCContext *Ctx,
822                               std::unique_ptr<MCRelocationInfo> &&RelInfo) {
823   return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo);
824 }
825 
826 static MCDisassembler *createAMDGPUDisassembler(const Target &T,
827                                                 const MCSubtargetInfo &STI,
828                                                 MCContext &Ctx) {
829   return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo());
830 }
831 
832 extern "C" void LLVMInitializeAMDGPUDisassembler() {
833   TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(),
834                                          createAMDGPUDisassembler);
835   TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(),
836                                        createAMDGPUSymbolizer);
837 }
838