1 //===-- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA --------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 //===----------------------------------------------------------------------===//
11 //
12 /// \file
13 ///
14 /// This file contains definition for AMDGPU ISA disassembler
15 //
16 //===----------------------------------------------------------------------===//
17 
18 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)?
19 
20 #include "AMDGPUDisassembler.h"
21 #include "AMDGPU.h"
22 #include "AMDGPURegisterInfo.h"
23 #include "Utils/AMDGPUBaseInfo.h"
24 
25 #include "llvm/MC/MCContext.h"
26 #include "llvm/MC/MCFixedLenDisassembler.h"
27 #include "llvm/MC/MCInst.h"
28 #include "llvm/MC/MCInstrDesc.h"
29 #include "llvm/MC/MCSubtargetInfo.h"
30 #include "llvm/Support/Endian.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/TargetRegistry.h"
33 
34 
35 using namespace llvm;
36 
37 #define DEBUG_TYPE "amdgpu-disassembler"
38 
39 typedef llvm::MCDisassembler::DecodeStatus DecodeStatus;
40 
41 
42 inline static MCDisassembler::DecodeStatus
43 addOperand(MCInst &Inst, const MCOperand& Opnd) {
44   Inst.addOperand(Opnd);
45   return Opnd.isValid() ?
46     MCDisassembler::Success :
47     MCDisassembler::SoftFail;
48 }
49 
50 #define DECODE_OPERAND2(RegClass, DecName) \
51 static DecodeStatus Decode##RegClass##RegisterClass(MCInst &Inst, \
52                                                     unsigned Imm, \
53                                                     uint64_t /*Addr*/, \
54                                                     const void *Decoder) { \
55   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); \
56   return addOperand(Inst, DAsm->decodeOperand_##DecName(Imm)); \
57 }
58 
59 #define DECODE_OPERAND(RegClass) DECODE_OPERAND2(RegClass, RegClass)
60 
61 DECODE_OPERAND(VGPR_32)
62 DECODE_OPERAND(VS_32)
63 DECODE_OPERAND(VS_64)
64 
65 DECODE_OPERAND(VReg_64)
66 DECODE_OPERAND(VReg_96)
67 DECODE_OPERAND(VReg_128)
68 
69 DECODE_OPERAND(SGPR_32)
70 DECODE_OPERAND(SReg_32)
71 DECODE_OPERAND(SReg_64)
72 DECODE_OPERAND(SReg_128)
73 DECODE_OPERAND(SReg_256)
74 DECODE_OPERAND(SReg_512)
75 
76 #define GET_SUBTARGETINFO_ENUM
77 #include "AMDGPUGenSubtargetInfo.inc"
78 #undef GET_SUBTARGETINFO_ENUM
79 
80 #include "AMDGPUGenDisassemblerTables.inc"
81 
82 //===----------------------------------------------------------------------===//
83 //
84 //===----------------------------------------------------------------------===//
85 
86 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) {
87   assert(Bytes.size() >= sizeof(T));
88   const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data());
89   Bytes = Bytes.slice(sizeof(T));
90   return Res;
91 }
92 
93 DecodeStatus AMDGPUDisassembler::tryDecodeInst(const uint8_t* Table,
94                                                MCInst &MI,
95                                                uint64_t Inst,
96                                                uint64_t Address) const {
97   assert(MI.getOpcode() == 0);
98   assert(MI.getNumOperands() == 0);
99   MCInst TmpInst;
100   const auto SavedBytes = Bytes;
101   if (decodeInstruction(Table, TmpInst, Inst, Address, this, STI)) {
102     MI = TmpInst;
103     return MCDisassembler::Success;
104   }
105   Bytes = SavedBytes;
106   return MCDisassembler::Fail;
107 }
108 
109 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
110                                                 ArrayRef<uint8_t> Bytes_,
111                                                 uint64_t Address,
112                                                 raw_ostream &WS,
113                                                 raw_ostream &CS) const {
114   CommentStream = &CS;
115 
116   // ToDo: AMDGPUDisassembler supports only VI ISA.
117   assert(AMDGPU::isVI(STI) && "Can disassemble only VI ISA.");
118 
119   const unsigned MaxInstBytesNum = (std::min)((size_t)8, Bytes_.size());
120   Bytes = Bytes_.slice(0, MaxInstBytesNum);
121 
122   DecodeStatus Res = MCDisassembler::Fail;
123   do {
124     // ToDo: better to switch encoding length using some bit predicate
125     // but it is unknown yet, so try all we can
126 
127     // Try to decode DPP first to solve conflict with VOP1 and VOP2 encodings
128     if (Bytes.size() >= 8) {
129       const uint64_t QW = eatBytes<uint64_t>(Bytes);
130       Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address);
131       if (Res) break;
132     }
133 
134     // Reinitialize Bytes as DPP64 could have eaten too much
135     Bytes = Bytes_.slice(0, MaxInstBytesNum);
136 
137     // Try decode 32-bit instruction
138     if (Bytes.size() < 4) break;
139     const uint32_t DW = eatBytes<uint32_t>(Bytes);
140     Res = tryDecodeInst(DecoderTableVI32, MI, DW, Address);
141     if (Res) break;
142 
143     Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address);
144     if (Res) break;
145 
146     if (Bytes.size() < 4) break;
147     const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW;
148     Res = tryDecodeInst(DecoderTableVI64, MI, QW, Address);
149     if (Res) break;
150 
151     Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address);
152   } while (false);
153 
154   Size = Res ? (MaxInstBytesNum - Bytes.size()) : 0;
155   return Res;
156 }
157 
158 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const {
159   return getContext().getRegisterInfo()->
160     getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]);
161 }
162 
163 inline
164 MCOperand AMDGPUDisassembler::errOperand(unsigned V,
165                                          const Twine& ErrMsg) const {
166   *CommentStream << "Error: " + ErrMsg;
167 
168   // ToDo: add support for error operands to MCInst.h
169   // return MCOperand::createError(V);
170   return MCOperand();
171 }
172 
173 inline
174 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const {
175   return MCOperand::createReg(RegId);
176 }
177 
178 inline
179 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID,
180                                                unsigned Val) const {
181   const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID];
182   if (Val >= RegCl.getNumRegs())
183     return errOperand(Val, Twine(getRegClassName(RegClassID)) +
184                            ": unknown register " + Twine(Val));
185   return createRegOperand(RegCl.getRegister(Val));
186 }
187 
188 inline
189 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID,
190                                                 unsigned Val) const {
191   // ToDo: SI/CI have 104 SGPRs, VI - 102
192   // Valery: here we accepting as much as we can, let assembler sort it out
193   int shift = 0;
194   switch (SRegClassID) {
195   case AMDGPU::SGPR_32RegClassID:
196   case AMDGPU::SReg_32RegClassID: break;
197   case AMDGPU::SGPR_64RegClassID:
198   case AMDGPU::SReg_64RegClassID:  shift = 1; break;
199   case AMDGPU::SReg_128RegClassID:
200   // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in
201   // this bundle?
202   case AMDGPU::SReg_256RegClassID:
203   // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in
204   // this bundle?
205   case AMDGPU::SReg_512RegClassID: shift = 2; break;
206   // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in
207   // this bundle?
208   default: assert(false); break;
209   }
210   if (Val % (1 << shift))
211     *CommentStream << "Warning: " << getRegClassName(SRegClassID)
212                    << ": scalar reg isn't aligned " << Val;
213   return createRegOperand(SRegClassID, Val >> shift);
214 }
215 
216 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const {
217   return decodeSrcOp(OP32, Val);
218 }
219 
220 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const {
221   return decodeSrcOp(OP64, Val);
222 }
223 
224 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const {
225   return createRegOperand(AMDGPU::VGPR_32RegClassID, Val);
226 }
227 
228 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const {
229   return createRegOperand(AMDGPU::VReg_64RegClassID, Val);
230 }
231 
232 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const {
233   return createRegOperand(AMDGPU::VReg_96RegClassID, Val);
234 }
235 
236 MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const {
237   return createRegOperand(AMDGPU::VReg_128RegClassID, Val);
238 }
239 
240 MCOperand AMDGPUDisassembler::decodeOperand_SGPR_32(unsigned Val) const {
241   return createSRegOperand(AMDGPU::SGPR_32RegClassID, Val);
242 }
243 
244 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const {
245   // table-gen generated disassembler doesn't care about operand types
246   // leaving only registry class so SSrc_32 operand turns into SReg_32
247   // and therefore we accept immediates and literals here as well
248   return decodeSrcOp(OP32, Val);
249 }
250 
251 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const {
252   // see decodeOperand_SReg_32 comment
253   return decodeSrcOp(OP64, Val);
254 }
255 
256 MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const {
257   return createSRegOperand(AMDGPU::SReg_128RegClassID, Val);
258 }
259 
260 MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const {
261   return createSRegOperand(AMDGPU::SReg_256RegClassID, Val);
262 }
263 
264 MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const {
265   return createSRegOperand(AMDGPU::SReg_512RegClassID, Val);
266 }
267 
268 
269 MCOperand AMDGPUDisassembler::decodeLiteralConstant() const {
270   // For now all literal constants are supposed to be unsigned integer
271   // ToDo: deal with signed/unsigned 64-bit integer constants
272   // ToDo: deal with float/double constants
273   if (Bytes.size() < 4)
274     return errOperand(0, "cannot read literal, inst bytes left " +
275                          Twine(Bytes.size()));
276   return MCOperand::createImm(eatBytes<uint32_t>(Bytes));
277 }
278 
279 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) {
280   assert(Imm >= 128 && Imm <= 208);
281   return MCOperand::createImm((Imm <= 192) ? (Imm - 128) : (192 - Imm));
282 }
283 
284 MCOperand AMDGPUDisassembler::decodeFPImmed(bool Is32, unsigned Imm) {
285   assert(Imm >= 240 && Imm <= 248);
286   // ToDo: case 248: 1/(2*PI) - is allowed only on VI
287   // ToDo: AMDGPUInstPrinter does not support 1/(2*PI). It consider 1/(2*PI) as
288   // literal constant.
289   float V = 0.0f;
290   switch (Imm) {
291   case 240: V =  0.5f; break;
292   case 241: V = -0.5f; break;
293   case 242: V =  1.0f; break;
294   case 243: V = -1.0f; break;
295   case 244: V =  2.0f; break;
296   case 245: V = -2.0f; break;
297   case 246: V =  4.0f; break;
298   case 247: V = -4.0f; break;
299   case 248: return MCOperand::createImm(Is32 ?         // 1/(2*PI)
300                                           0x3e22f983 :
301                                           0x3fc45f306dc9c882);
302   default: break;
303   }
304   return MCOperand::createImm(Is32? FloatToBits(V) : DoubleToBits(V));
305 }
306 
307 MCOperand AMDGPUDisassembler::decodeSrcOp(bool Is32, unsigned Val) const {
308   using namespace AMDGPU;
309   assert(Val < 512); // enum9
310 
311   if (Val >= 256)
312     return createRegOperand(Is32 ? VGPR_32RegClassID : VReg_64RegClassID,
313                             Val - 256);
314   if (Val <= 101)
315     return createSRegOperand(Is32 ? SGPR_32RegClassID : SGPR_64RegClassID,
316                              Val);
317 
318   if (Val >= 128 && Val <= 208)
319     return decodeIntImmed(Val);
320 
321   if (Val >= 240 && Val <= 248)
322     return decodeFPImmed(Is32, Val);
323 
324   if (Val == 255)
325     return decodeLiteralConstant();
326 
327   return Is32 ? decodeSpecialReg32(Val) : decodeSpecialReg64(Val);
328 }
329 
330 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const {
331   using namespace AMDGPU;
332   switch (Val) {
333   case 102: return createRegOperand(getMCReg(FLAT_SCR_LO, STI));
334   case 103: return createRegOperand(getMCReg(FLAT_SCR_HI, STI));
335     // ToDo: no support for xnack_mask_lo/_hi register
336   case 104:
337   case 105: break;
338   case 106: return createRegOperand(VCC_LO);
339   case 107: return createRegOperand(VCC_HI);
340     // ToDo: no support for tba_lo/_hi register
341   case 108:
342   case 109: break;
343     // ToDo: no support for tma_lo/_hi register
344   case 110:
345   case 111: break;
346     // ToDo: no support for ttmp[0:11] register
347   case 112:
348   case 113:
349   case 114:
350   case 115:
351   case 116:
352   case 117:
353   case 118:
354   case 119:
355   case 120:
356   case 121:
357   case 122:
358   case 123: break;
359   case 124: return createRegOperand(M0);
360   case 126: return createRegOperand(EXEC_LO);
361   case 127: return createRegOperand(EXEC_HI);
362     // ToDo: no support for vccz register
363   case 251: break;
364     // ToDo: no support for execz register
365   case 252: break;
366   case 253: return createRegOperand(SCC);
367   default: break;
368   }
369   return errOperand(Val, "unknown operand encoding " + Twine(Val));
370 }
371 
372 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const {
373   using namespace AMDGPU;
374   switch (Val) {
375   case 102: return createRegOperand(getMCReg(FLAT_SCR, STI));
376   case 106: return createRegOperand(VCC);
377   case 126: return createRegOperand(EXEC);
378   default: break;
379   }
380   return errOperand(Val, "unknown operand encoding " + Twine(Val));
381 }
382 
383 static MCDisassembler *createAMDGPUDisassembler(const Target &T,
384                                                 const MCSubtargetInfo &STI,
385                                                 MCContext &Ctx) {
386   return new AMDGPUDisassembler(STI, Ctx);
387 }
388 
389 extern "C" void LLVMInitializeAMDGPUDisassembler() {
390   TargetRegistry::RegisterMCDisassembler(TheGCNTarget, createAMDGPUDisassembler);
391 }
392