1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 //===----------------------------------------------------------------------===// 10 // 11 /// \file 12 /// 13 /// This file contains definition for AMDGPU ISA disassembler 14 // 15 //===----------------------------------------------------------------------===// 16 17 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)? 18 19 #include "Disassembler/AMDGPUDisassembler.h" 20 #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 21 #include "TargetInfo/AMDGPUTargetInfo.h" 22 #include "Utils/AMDGPUBaseInfo.h" 23 #include "llvm-c/DisassemblerTypes.h" 24 #include "llvm/MC/MCAsmInfo.h" 25 #include "llvm/MC/MCContext.h" 26 #include "llvm/MC/MCExpr.h" 27 #include "llvm/MC/MCFixedLenDisassembler.h" 28 #include "llvm/Support/AMDHSAKernelDescriptor.h" 29 #include "llvm/Support/TargetRegistry.h" 30 31 using namespace llvm; 32 33 #define DEBUG_TYPE "amdgpu-disassembler" 34 35 #define SGPR_MAX \ 36 (isGFX10Plus() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \ 37 : AMDGPU::EncValues::SGPR_MAX_SI) 38 39 using DecodeStatus = llvm::MCDisassembler::DecodeStatus; 40 41 AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI, 42 MCContext &Ctx, 43 MCInstrInfo const *MCII) : 44 MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()), 45 TargetMaxInstBytes(Ctx.getAsmInfo()->getMaxInstLength(&STI)) { 46 47 // ToDo: AMDGPUDisassembler supports only VI ISA. 48 if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding] && !isGFX10Plus()) 49 report_fatal_error("Disassembly not yet supported for subtarget"); 50 } 51 52 inline static MCDisassembler::DecodeStatus 53 addOperand(MCInst &Inst, const MCOperand& Opnd) { 54 Inst.addOperand(Opnd); 55 return Opnd.isValid() ? 56 MCDisassembler::Success : 57 MCDisassembler::Fail; 58 } 59 60 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, 61 uint16_t NameIdx) { 62 int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx); 63 if (OpIdx != -1) { 64 auto I = MI.begin(); 65 std::advance(I, OpIdx); 66 MI.insert(I, Op); 67 } 68 return OpIdx; 69 } 70 71 static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm, 72 uint64_t Addr, const void *Decoder) { 73 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 74 75 // Our branches take a simm16, but we need two extra bits to account for the 76 // factor of 4. 77 APInt SignedOffset(18, Imm * 4, true); 78 int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue(); 79 80 if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2)) 81 return MCDisassembler::Success; 82 return addOperand(Inst, MCOperand::createImm(Imm)); 83 } 84 85 static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, 86 uint64_t Addr, const void *Decoder) { 87 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 88 int64_t Offset; 89 if (DAsm->isVI()) { // VI supports 20-bit unsigned offsets. 90 Offset = Imm & 0xFFFFF; 91 } else { // GFX9+ supports 21-bit signed offsets. 92 Offset = SignExtend64<21>(Imm); 93 } 94 return addOperand(Inst, MCOperand::createImm(Offset)); 95 } 96 97 static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, 98 uint64_t Addr, const void *Decoder) { 99 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 100 return addOperand(Inst, DAsm->decodeBoolReg(Val)); 101 } 102 103 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \ 104 static DecodeStatus StaticDecoderName(MCInst &Inst, \ 105 unsigned Imm, \ 106 uint64_t /*Addr*/, \ 107 const void *Decoder) { \ 108 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); \ 109 return addOperand(Inst, DAsm->DecoderName(Imm)); \ 110 } 111 112 #define DECODE_OPERAND_REG(RegClass) \ 113 DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass) 114 115 DECODE_OPERAND_REG(VGPR_32) 116 DECODE_OPERAND_REG(VRegOrLds_32) 117 DECODE_OPERAND_REG(VS_32) 118 DECODE_OPERAND_REG(VS_64) 119 DECODE_OPERAND_REG(VS_128) 120 121 DECODE_OPERAND_REG(VReg_64) 122 DECODE_OPERAND_REG(VReg_96) 123 DECODE_OPERAND_REG(VReg_128) 124 DECODE_OPERAND_REG(VReg_256) 125 DECODE_OPERAND_REG(VReg_512) 126 127 DECODE_OPERAND_REG(SReg_32) 128 DECODE_OPERAND_REG(SReg_32_XM0_XEXEC) 129 DECODE_OPERAND_REG(SReg_32_XEXEC_HI) 130 DECODE_OPERAND_REG(SRegOrLds_32) 131 DECODE_OPERAND_REG(SReg_64) 132 DECODE_OPERAND_REG(SReg_64_XEXEC) 133 DECODE_OPERAND_REG(SReg_128) 134 DECODE_OPERAND_REG(SReg_256) 135 DECODE_OPERAND_REG(SReg_512) 136 137 DECODE_OPERAND_REG(AGPR_32) 138 DECODE_OPERAND_REG(AReg_128) 139 DECODE_OPERAND_REG(AReg_512) 140 DECODE_OPERAND_REG(AReg_1024) 141 DECODE_OPERAND_REG(AV_32) 142 DECODE_OPERAND_REG(AV_64) 143 144 static DecodeStatus decodeOperand_VSrc16(MCInst &Inst, 145 unsigned Imm, 146 uint64_t Addr, 147 const void *Decoder) { 148 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 149 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); 150 } 151 152 static DecodeStatus decodeOperand_VSrcV216(MCInst &Inst, 153 unsigned Imm, 154 uint64_t Addr, 155 const void *Decoder) { 156 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 157 return addOperand(Inst, DAsm->decodeOperand_VSrcV216(Imm)); 158 } 159 160 static DecodeStatus decodeOperand_VS_16(MCInst &Inst, 161 unsigned Imm, 162 uint64_t Addr, 163 const void *Decoder) { 164 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 165 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); 166 } 167 168 static DecodeStatus decodeOperand_VS_32(MCInst &Inst, 169 unsigned Imm, 170 uint64_t Addr, 171 const void *Decoder) { 172 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 173 return addOperand(Inst, DAsm->decodeOperand_VS_32(Imm)); 174 } 175 176 static DecodeStatus decodeOperand_AReg_128(MCInst &Inst, 177 unsigned Imm, 178 uint64_t Addr, 179 const void *Decoder) { 180 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 181 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm | 512)); 182 } 183 184 static DecodeStatus decodeOperand_AReg_512(MCInst &Inst, 185 unsigned Imm, 186 uint64_t Addr, 187 const void *Decoder) { 188 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 189 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm | 512)); 190 } 191 192 static DecodeStatus decodeOperand_AReg_1024(MCInst &Inst, 193 unsigned Imm, 194 uint64_t Addr, 195 const void *Decoder) { 196 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 197 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm | 512)); 198 } 199 200 static DecodeStatus decodeOperand_SReg_32(MCInst &Inst, 201 unsigned Imm, 202 uint64_t Addr, 203 const void *Decoder) { 204 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 205 return addOperand(Inst, DAsm->decodeOperand_SReg_32(Imm)); 206 } 207 208 static DecodeStatus decodeOperand_VGPR_32(MCInst &Inst, 209 unsigned Imm, 210 uint64_t Addr, 211 const void *Decoder) { 212 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 213 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW32, Imm)); 214 } 215 216 #define DECODE_SDWA(DecName) \ 217 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName) 218 219 DECODE_SDWA(Src32) 220 DECODE_SDWA(Src16) 221 DECODE_SDWA(VopcDst) 222 223 #include "AMDGPUGenDisassemblerTables.inc" 224 225 //===----------------------------------------------------------------------===// 226 // 227 //===----------------------------------------------------------------------===// 228 229 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) { 230 assert(Bytes.size() >= sizeof(T)); 231 const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data()); 232 Bytes = Bytes.slice(sizeof(T)); 233 return Res; 234 } 235 236 DecodeStatus AMDGPUDisassembler::tryDecodeInst(const uint8_t* Table, 237 MCInst &MI, 238 uint64_t Inst, 239 uint64_t Address) const { 240 assert(MI.getOpcode() == 0); 241 assert(MI.getNumOperands() == 0); 242 MCInst TmpInst; 243 HasLiteral = false; 244 const auto SavedBytes = Bytes; 245 if (decodeInstruction(Table, TmpInst, Inst, Address, this, STI)) { 246 MI = TmpInst; 247 return MCDisassembler::Success; 248 } 249 Bytes = SavedBytes; 250 return MCDisassembler::Fail; 251 } 252 253 static bool isValidDPP8(const MCInst &MI) { 254 using namespace llvm::AMDGPU::DPP; 255 int FiIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::fi); 256 assert(FiIdx != -1); 257 if ((unsigned)FiIdx >= MI.getNumOperands()) 258 return false; 259 unsigned Fi = MI.getOperand(FiIdx).getImm(); 260 return Fi == DPP8_FI_0 || Fi == DPP8_FI_1; 261 } 262 263 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 264 ArrayRef<uint8_t> Bytes_, 265 uint64_t Address, 266 raw_ostream &CS) const { 267 CommentStream = &CS; 268 bool IsSDWA = false; 269 270 unsigned MaxInstBytesNum = std::min((size_t)TargetMaxInstBytes, Bytes_.size()); 271 Bytes = Bytes_.slice(0, MaxInstBytesNum); 272 273 DecodeStatus Res = MCDisassembler::Fail; 274 do { 275 // ToDo: better to switch encoding length using some bit predicate 276 // but it is unknown yet, so try all we can 277 278 // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2 279 // encodings 280 if (Bytes.size() >= 8) { 281 const uint64_t QW = eatBytes<uint64_t>(Bytes); 282 283 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) { 284 Res = tryDecodeInst(DecoderTableGFX10_B64, MI, QW, Address); 285 if (Res) { 286 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dpp8) 287 == -1) 288 break; 289 if (convertDPP8Inst(MI) == MCDisassembler::Success) 290 break; 291 MI = MCInst(); // clear 292 } 293 } 294 295 Res = tryDecodeInst(DecoderTableDPP864, MI, QW, Address); 296 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 297 break; 298 299 MI = MCInst(); // clear 300 301 Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address); 302 if (Res) break; 303 304 Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address); 305 if (Res) { IsSDWA = true; break; } 306 307 Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address); 308 if (Res) { IsSDWA = true; break; } 309 310 Res = tryDecodeInst(DecoderTableSDWA1064, MI, QW, Address); 311 if (Res) { IsSDWA = true; break; } 312 313 if (STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem]) { 314 Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address); 315 if (Res) 316 break; 317 } 318 319 // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and 320 // v_mad_mixhi_f16 for FMA variants. Try to decode using this special 321 // table first so we print the correct name. 322 if (STI.getFeatureBits()[AMDGPU::FeatureFmaMixInsts]) { 323 Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address); 324 if (Res) 325 break; 326 } 327 } 328 329 // Reinitialize Bytes as DPP64 could have eaten too much 330 Bytes = Bytes_.slice(0, MaxInstBytesNum); 331 332 // Try decode 32-bit instruction 333 if (Bytes.size() < 4) break; 334 const uint32_t DW = eatBytes<uint32_t>(Bytes); 335 Res = tryDecodeInst(DecoderTableGFX832, MI, DW, Address); 336 if (Res) break; 337 338 Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address); 339 if (Res) break; 340 341 Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address); 342 if (Res) break; 343 344 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) { 345 Res = tryDecodeInst(DecoderTableGFX10_B32, MI, DW, Address); 346 if (Res) break; 347 } 348 349 Res = tryDecodeInst(DecoderTableGFX1032, MI, DW, Address); 350 if (Res) break; 351 352 if (Bytes.size() < 4) break; 353 const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW; 354 Res = tryDecodeInst(DecoderTableGFX864, MI, QW, Address); 355 if (Res) break; 356 357 Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address); 358 if (Res) break; 359 360 Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address); 361 if (Res) break; 362 363 Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address); 364 } while (false); 365 366 if (Res && (MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi || 367 MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx6_gfx7 || 368 MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx10 || 369 MI.getOpcode() == AMDGPU::V_MAC_LEGACY_F32_e64_gfx6_gfx7 || 370 MI.getOpcode() == AMDGPU::V_MAC_LEGACY_F32_e64_gfx10 || 371 MI.getOpcode() == AMDGPU::V_MAC_F16_e64_vi || 372 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_vi || 373 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_gfx10 || 374 MI.getOpcode() == AMDGPU::V_FMAC_LEGACY_F32_e64_gfx10 || 375 MI.getOpcode() == AMDGPU::V_FMAC_F16_e64_gfx10)) { 376 // Insert dummy unused src2_modifiers. 377 insertNamedMCOperand(MI, MCOperand::createImm(0), 378 AMDGPU::OpName::src2_modifiers); 379 } 380 381 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 382 (SIInstrFlags::MUBUF | SIInstrFlags::FLAT)) && 383 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::glc1) != -1) { 384 insertNamedMCOperand(MI, MCOperand::createImm(1), AMDGPU::OpName::glc1); 385 } 386 387 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) { 388 int VAddr0Idx = 389 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 390 int RsrcIdx = 391 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc); 392 unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1; 393 if (VAddr0Idx >= 0 && NSAArgs > 0) { 394 unsigned NSAWords = (NSAArgs + 3) / 4; 395 if (Bytes.size() < 4 * NSAWords) { 396 Res = MCDisassembler::Fail; 397 } else { 398 for (unsigned i = 0; i < NSAArgs; ++i) { 399 MI.insert(MI.begin() + VAddr0Idx + 1 + i, 400 decodeOperand_VGPR_32(Bytes[i])); 401 } 402 Bytes = Bytes.slice(4 * NSAWords); 403 } 404 } 405 406 if (Res) 407 Res = convertMIMGInst(MI); 408 } 409 410 if (Res && IsSDWA) 411 Res = convertSDWAInst(MI); 412 413 int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 414 AMDGPU::OpName::vdst_in); 415 if (VDstIn_Idx != -1) { 416 int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx, 417 MCOI::OperandConstraint::TIED_TO); 418 if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx || 419 !MI.getOperand(VDstIn_Idx).isReg() || 420 MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) { 421 if (MI.getNumOperands() > (unsigned)VDstIn_Idx) 422 MI.erase(&MI.getOperand(VDstIn_Idx)); 423 insertNamedMCOperand(MI, 424 MCOperand::createReg(MI.getOperand(Tied).getReg()), 425 AMDGPU::OpName::vdst_in); 426 } 427 } 428 429 // if the opcode was not recognized we'll assume a Size of 4 bytes 430 // (unless there are fewer bytes left) 431 Size = Res ? (MaxInstBytesNum - Bytes.size()) 432 : std::min((size_t)4, Bytes_.size()); 433 return Res; 434 } 435 436 DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const { 437 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 438 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 439 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst) != -1) 440 // VOPC - insert clamp 441 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp); 442 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 443 int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst); 444 if (SDst != -1) { 445 // VOPC - insert VCC register as sdst 446 insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC), 447 AMDGPU::OpName::sdst); 448 } else { 449 // VOP1/2 - insert omod if present in instruction 450 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod); 451 } 452 } 453 return MCDisassembler::Success; 454 } 455 456 DecodeStatus AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const { 457 unsigned Opc = MI.getOpcode(); 458 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 459 460 // Insert dummy unused src modifiers. 461 if (MI.getNumOperands() < DescNumOps && 462 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1) 463 insertNamedMCOperand(MI, MCOperand::createImm(0), 464 AMDGPU::OpName::src0_modifiers); 465 466 if (MI.getNumOperands() < DescNumOps && 467 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers) != -1) 468 insertNamedMCOperand(MI, MCOperand::createImm(0), 469 AMDGPU::OpName::src1_modifiers); 470 471 return isValidDPP8(MI) ? MCDisassembler::Success : MCDisassembler::SoftFail; 472 } 473 474 // Note that before gfx10, the MIMG encoding provided no information about 475 // VADDR size. Consequently, decoded instructions always show address as if it 476 // has 1 dword, which could be not really so. 477 DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const { 478 479 int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 480 AMDGPU::OpName::vdst); 481 482 int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 483 AMDGPU::OpName::vdata); 484 int VAddr0Idx = 485 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 486 int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 487 AMDGPU::OpName::dmask); 488 489 int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 490 AMDGPU::OpName::tfe); 491 int D16Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 492 AMDGPU::OpName::d16); 493 494 assert(VDataIdx != -1); 495 if (DMaskIdx == -1 || TFEIdx == -1) {// intersect_ray 496 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16) > -1) { 497 assert(MI.getOpcode() == AMDGPU::IMAGE_BVH_INTERSECT_RAY_a16_sa || 498 MI.getOpcode() == AMDGPU::IMAGE_BVH_INTERSECT_RAY_a16_nsa || 499 MI.getOpcode() == AMDGPU::IMAGE_BVH64_INTERSECT_RAY_a16_sa || 500 MI.getOpcode() == AMDGPU::IMAGE_BVH64_INTERSECT_RAY_a16_nsa); 501 addOperand(MI, MCOperand::createImm(1)); 502 } 503 return MCDisassembler::Success; 504 } 505 506 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode()); 507 bool IsAtomic = (VDstIdx != -1); 508 bool IsGather4 = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::Gather4; 509 510 bool IsNSA = false; 511 unsigned AddrSize = Info->VAddrDwords; 512 513 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 514 unsigned DimIdx = 515 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim); 516 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = 517 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); 518 const AMDGPU::MIMGDimInfo *Dim = 519 AMDGPU::getMIMGDimInfoByEncoding(MI.getOperand(DimIdx).getImm()); 520 521 AddrSize = BaseOpcode->NumExtraArgs + 522 (BaseOpcode->Gradients ? Dim->NumGradients : 0) + 523 (BaseOpcode->Coordinates ? Dim->NumCoords : 0) + 524 (BaseOpcode->LodOrClampOrMip ? 1 : 0); 525 IsNSA = Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA; 526 if (!IsNSA) { 527 if (AddrSize > 8) 528 AddrSize = 16; 529 else if (AddrSize > 4) 530 AddrSize = 8; 531 } else { 532 if (AddrSize > Info->VAddrDwords) { 533 // The NSA encoding does not contain enough operands for the combination 534 // of base opcode / dimension. Should this be an error? 535 return MCDisassembler::Success; 536 } 537 } 538 } 539 540 unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf; 541 unsigned DstSize = IsGather4 ? 4 : std::max(countPopulation(DMask), 1u); 542 543 bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm(); 544 if (D16 && AMDGPU::hasPackedD16(STI)) { 545 DstSize = (DstSize + 1) / 2; 546 } 547 548 if (MI.getOperand(TFEIdx).getImm()) 549 DstSize += 1; 550 551 if (DstSize == Info->VDataDwords && AddrSize == Info->VAddrDwords) 552 return MCDisassembler::Success; 553 554 int NewOpcode = 555 AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize); 556 if (NewOpcode == -1) 557 return MCDisassembler::Success; 558 559 // Widen the register to the correct number of enabled channels. 560 unsigned NewVdata = AMDGPU::NoRegister; 561 if (DstSize != Info->VDataDwords) { 562 auto DataRCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass; 563 564 // Get first subregister of VData 565 unsigned Vdata0 = MI.getOperand(VDataIdx).getReg(); 566 unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0); 567 Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0; 568 569 NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0, 570 &MRI.getRegClass(DataRCID)); 571 if (NewVdata == AMDGPU::NoRegister) { 572 // It's possible to encode this such that the low register + enabled 573 // components exceeds the register count. 574 return MCDisassembler::Success; 575 } 576 } 577 578 unsigned NewVAddr0 = AMDGPU::NoRegister; 579 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10] && !IsNSA && 580 AddrSize != Info->VAddrDwords) { 581 unsigned VAddr0 = MI.getOperand(VAddr0Idx).getReg(); 582 unsigned VAddrSub0 = MRI.getSubReg(VAddr0, AMDGPU::sub0); 583 VAddr0 = (VAddrSub0 != 0) ? VAddrSub0 : VAddr0; 584 585 auto AddrRCID = MCII->get(NewOpcode).OpInfo[VAddr0Idx].RegClass; 586 NewVAddr0 = MRI.getMatchingSuperReg(VAddr0, AMDGPU::sub0, 587 &MRI.getRegClass(AddrRCID)); 588 if (NewVAddr0 == AMDGPU::NoRegister) 589 return MCDisassembler::Success; 590 } 591 592 MI.setOpcode(NewOpcode); 593 594 if (NewVdata != AMDGPU::NoRegister) { 595 MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata); 596 597 if (IsAtomic) { 598 // Atomic operations have an additional operand (a copy of data) 599 MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata); 600 } 601 } 602 603 if (NewVAddr0 != AMDGPU::NoRegister) { 604 MI.getOperand(VAddr0Idx) = MCOperand::createReg(NewVAddr0); 605 } else if (IsNSA) { 606 assert(AddrSize <= Info->VAddrDwords); 607 MI.erase(MI.begin() + VAddr0Idx + AddrSize, 608 MI.begin() + VAddr0Idx + Info->VAddrDwords); 609 } 610 611 return MCDisassembler::Success; 612 } 613 614 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { 615 return getContext().getRegisterInfo()-> 616 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); 617 } 618 619 inline 620 MCOperand AMDGPUDisassembler::errOperand(unsigned V, 621 const Twine& ErrMsg) const { 622 *CommentStream << "Error: " + ErrMsg; 623 624 // ToDo: add support for error operands to MCInst.h 625 // return MCOperand::createError(V); 626 return MCOperand(); 627 } 628 629 inline 630 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const { 631 return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI)); 632 } 633 634 inline 635 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, 636 unsigned Val) const { 637 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; 638 if (Val >= RegCl.getNumRegs()) 639 return errOperand(Val, Twine(getRegClassName(RegClassID)) + 640 ": unknown register " + Twine(Val)); 641 return createRegOperand(RegCl.getRegister(Val)); 642 } 643 644 inline 645 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID, 646 unsigned Val) const { 647 // ToDo: SI/CI have 104 SGPRs, VI - 102 648 // Valery: here we accepting as much as we can, let assembler sort it out 649 int shift = 0; 650 switch (SRegClassID) { 651 case AMDGPU::SGPR_32RegClassID: 652 case AMDGPU::TTMP_32RegClassID: 653 break; 654 case AMDGPU::SGPR_64RegClassID: 655 case AMDGPU::TTMP_64RegClassID: 656 shift = 1; 657 break; 658 case AMDGPU::SGPR_128RegClassID: 659 case AMDGPU::TTMP_128RegClassID: 660 // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in 661 // this bundle? 662 case AMDGPU::SGPR_256RegClassID: 663 case AMDGPU::TTMP_256RegClassID: 664 // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in 665 // this bundle? 666 case AMDGPU::SGPR_512RegClassID: 667 case AMDGPU::TTMP_512RegClassID: 668 shift = 2; 669 break; 670 // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in 671 // this bundle? 672 default: 673 llvm_unreachable("unhandled register class"); 674 } 675 676 if (Val % (1 << shift)) { 677 *CommentStream << "Warning: " << getRegClassName(SRegClassID) 678 << ": scalar reg isn't aligned " << Val; 679 } 680 681 return createRegOperand(SRegClassID, Val >> shift); 682 } 683 684 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const { 685 return decodeSrcOp(OPW32, Val); 686 } 687 688 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const { 689 return decodeSrcOp(OPW64, Val); 690 } 691 692 MCOperand AMDGPUDisassembler::decodeOperand_VS_128(unsigned Val) const { 693 return decodeSrcOp(OPW128, Val); 694 } 695 696 MCOperand AMDGPUDisassembler::decodeOperand_VSrc16(unsigned Val) const { 697 return decodeSrcOp(OPW16, Val); 698 } 699 700 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV216(unsigned Val) const { 701 return decodeSrcOp(OPWV216, Val); 702 } 703 704 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const { 705 // Some instructions have operand restrictions beyond what the encoding 706 // allows. Some ordinarily VSrc_32 operands are VGPR_32, so clear the extra 707 // high bit. 708 Val &= 255; 709 710 return createRegOperand(AMDGPU::VGPR_32RegClassID, Val); 711 } 712 713 MCOperand AMDGPUDisassembler::decodeOperand_VRegOrLds_32(unsigned Val) const { 714 return decodeSrcOp(OPW32, Val); 715 } 716 717 MCOperand AMDGPUDisassembler::decodeOperand_AGPR_32(unsigned Val) const { 718 return createRegOperand(AMDGPU::AGPR_32RegClassID, Val & 255); 719 } 720 721 MCOperand AMDGPUDisassembler::decodeOperand_AReg_128(unsigned Val) const { 722 return createRegOperand(AMDGPU::AReg_128RegClassID, Val & 255); 723 } 724 725 MCOperand AMDGPUDisassembler::decodeOperand_AReg_512(unsigned Val) const { 726 return createRegOperand(AMDGPU::AReg_512RegClassID, Val & 255); 727 } 728 729 MCOperand AMDGPUDisassembler::decodeOperand_AReg_1024(unsigned Val) const { 730 return createRegOperand(AMDGPU::AReg_1024RegClassID, Val & 255); 731 } 732 733 MCOperand AMDGPUDisassembler::decodeOperand_AV_32(unsigned Val) const { 734 return decodeSrcOp(OPW32, Val); 735 } 736 737 MCOperand AMDGPUDisassembler::decodeOperand_AV_64(unsigned Val) const { 738 return decodeSrcOp(OPW64, Val); 739 } 740 741 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const { 742 return createRegOperand(AMDGPU::VReg_64RegClassID, Val); 743 } 744 745 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const { 746 return createRegOperand(AMDGPU::VReg_96RegClassID, Val); 747 } 748 749 MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const { 750 return createRegOperand(AMDGPU::VReg_128RegClassID, Val); 751 } 752 753 MCOperand AMDGPUDisassembler::decodeOperand_VReg_256(unsigned Val) const { 754 return createRegOperand(AMDGPU::VReg_256RegClassID, Val); 755 } 756 757 MCOperand AMDGPUDisassembler::decodeOperand_VReg_512(unsigned Val) const { 758 return createRegOperand(AMDGPU::VReg_512RegClassID, Val); 759 } 760 761 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const { 762 // table-gen generated disassembler doesn't care about operand types 763 // leaving only registry class so SSrc_32 operand turns into SReg_32 764 // and therefore we accept immediates and literals here as well 765 return decodeSrcOp(OPW32, Val); 766 } 767 768 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0_XEXEC( 769 unsigned Val) const { 770 // SReg_32_XM0 is SReg_32 without M0 or EXEC_LO/EXEC_HI 771 return decodeOperand_SReg_32(Val); 772 } 773 774 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XEXEC_HI( 775 unsigned Val) const { 776 // SReg_32_XM0 is SReg_32 without EXEC_HI 777 return decodeOperand_SReg_32(Val); 778 } 779 780 MCOperand AMDGPUDisassembler::decodeOperand_SRegOrLds_32(unsigned Val) const { 781 // table-gen generated disassembler doesn't care about operand types 782 // leaving only registry class so SSrc_32 operand turns into SReg_32 783 // and therefore we accept immediates and literals here as well 784 return decodeSrcOp(OPW32, Val); 785 } 786 787 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const { 788 return decodeSrcOp(OPW64, Val); 789 } 790 791 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64_XEXEC(unsigned Val) const { 792 return decodeSrcOp(OPW64, Val); 793 } 794 795 MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const { 796 return decodeSrcOp(OPW128, Val); 797 } 798 799 MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const { 800 return decodeDstOp(OPW256, Val); 801 } 802 803 MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const { 804 return decodeDstOp(OPW512, Val); 805 } 806 807 MCOperand AMDGPUDisassembler::decodeLiteralConstant() const { 808 // For now all literal constants are supposed to be unsigned integer 809 // ToDo: deal with signed/unsigned 64-bit integer constants 810 // ToDo: deal with float/double constants 811 if (!HasLiteral) { 812 if (Bytes.size() < 4) { 813 return errOperand(0, "cannot read literal, inst bytes left " + 814 Twine(Bytes.size())); 815 } 816 HasLiteral = true; 817 Literal = eatBytes<uint32_t>(Bytes); 818 } 819 return MCOperand::createImm(Literal); 820 } 821 822 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) { 823 using namespace AMDGPU::EncValues; 824 825 assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX); 826 return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ? 827 (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) : 828 (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm))); 829 // Cast prevents negative overflow. 830 } 831 832 static int64_t getInlineImmVal32(unsigned Imm) { 833 switch (Imm) { 834 case 240: 835 return FloatToBits(0.5f); 836 case 241: 837 return FloatToBits(-0.5f); 838 case 242: 839 return FloatToBits(1.0f); 840 case 243: 841 return FloatToBits(-1.0f); 842 case 244: 843 return FloatToBits(2.0f); 844 case 245: 845 return FloatToBits(-2.0f); 846 case 246: 847 return FloatToBits(4.0f); 848 case 247: 849 return FloatToBits(-4.0f); 850 case 248: // 1 / (2 * PI) 851 return 0x3e22f983; 852 default: 853 llvm_unreachable("invalid fp inline imm"); 854 } 855 } 856 857 static int64_t getInlineImmVal64(unsigned Imm) { 858 switch (Imm) { 859 case 240: 860 return DoubleToBits(0.5); 861 case 241: 862 return DoubleToBits(-0.5); 863 case 242: 864 return DoubleToBits(1.0); 865 case 243: 866 return DoubleToBits(-1.0); 867 case 244: 868 return DoubleToBits(2.0); 869 case 245: 870 return DoubleToBits(-2.0); 871 case 246: 872 return DoubleToBits(4.0); 873 case 247: 874 return DoubleToBits(-4.0); 875 case 248: // 1 / (2 * PI) 876 return 0x3fc45f306dc9c882; 877 default: 878 llvm_unreachable("invalid fp inline imm"); 879 } 880 } 881 882 static int64_t getInlineImmVal16(unsigned Imm) { 883 switch (Imm) { 884 case 240: 885 return 0x3800; 886 case 241: 887 return 0xB800; 888 case 242: 889 return 0x3C00; 890 case 243: 891 return 0xBC00; 892 case 244: 893 return 0x4000; 894 case 245: 895 return 0xC000; 896 case 246: 897 return 0x4400; 898 case 247: 899 return 0xC400; 900 case 248: // 1 / (2 * PI) 901 return 0x3118; 902 default: 903 llvm_unreachable("invalid fp inline imm"); 904 } 905 } 906 907 MCOperand AMDGPUDisassembler::decodeFPImmed(OpWidthTy Width, unsigned Imm) { 908 assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN 909 && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX); 910 911 // ToDo: case 248: 1/(2*PI) - is allowed only on VI 912 switch (Width) { 913 case OPW32: 914 case OPW128: // splat constants 915 case OPW512: 916 case OPW1024: 917 return MCOperand::createImm(getInlineImmVal32(Imm)); 918 case OPW64: 919 return MCOperand::createImm(getInlineImmVal64(Imm)); 920 case OPW16: 921 case OPWV216: 922 return MCOperand::createImm(getInlineImmVal16(Imm)); 923 default: 924 llvm_unreachable("implement me"); 925 } 926 } 927 928 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const { 929 using namespace AMDGPU; 930 931 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 932 switch (Width) { 933 default: // fall 934 case OPW32: 935 case OPW16: 936 case OPWV216: 937 return VGPR_32RegClassID; 938 case OPW64: return VReg_64RegClassID; 939 case OPW128: return VReg_128RegClassID; 940 } 941 } 942 943 unsigned AMDGPUDisassembler::getAgprClassId(const OpWidthTy Width) const { 944 using namespace AMDGPU; 945 946 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 947 switch (Width) { 948 default: // fall 949 case OPW32: 950 case OPW16: 951 case OPWV216: 952 return AGPR_32RegClassID; 953 case OPW64: return AReg_64RegClassID; 954 case OPW128: return AReg_128RegClassID; 955 case OPW256: return AReg_256RegClassID; 956 case OPW512: return AReg_512RegClassID; 957 case OPW1024: return AReg_1024RegClassID; 958 } 959 } 960 961 962 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const { 963 using namespace AMDGPU; 964 965 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 966 switch (Width) { 967 default: // fall 968 case OPW32: 969 case OPW16: 970 case OPWV216: 971 return SGPR_32RegClassID; 972 case OPW64: return SGPR_64RegClassID; 973 case OPW128: return SGPR_128RegClassID; 974 case OPW256: return SGPR_256RegClassID; 975 case OPW512: return SGPR_512RegClassID; 976 } 977 } 978 979 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const { 980 using namespace AMDGPU; 981 982 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 983 switch (Width) { 984 default: // fall 985 case OPW32: 986 case OPW16: 987 case OPWV216: 988 return TTMP_32RegClassID; 989 case OPW64: return TTMP_64RegClassID; 990 case OPW128: return TTMP_128RegClassID; 991 case OPW256: return TTMP_256RegClassID; 992 case OPW512: return TTMP_512RegClassID; 993 } 994 } 995 996 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const { 997 using namespace AMDGPU::EncValues; 998 999 unsigned TTmpMin = isGFX9Plus() ? TTMP_GFX9PLUS_MIN : TTMP_VI_MIN; 1000 unsigned TTmpMax = isGFX9Plus() ? TTMP_GFX9PLUS_MAX : TTMP_VI_MAX; 1001 1002 return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1; 1003 } 1004 1005 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val) const { 1006 using namespace AMDGPU::EncValues; 1007 1008 assert(Val < 1024); // enum10 1009 1010 bool IsAGPR = Val & 512; 1011 Val &= 511; 1012 1013 if (VGPR_MIN <= Val && Val <= VGPR_MAX) { 1014 return createRegOperand(IsAGPR ? getAgprClassId(Width) 1015 : getVgprClassId(Width), Val - VGPR_MIN); 1016 } 1017 if (Val <= SGPR_MAX) { 1018 assert(SGPR_MIN == 0); // "SGPR_MIN <= Val" is always true and causes compilation warning. 1019 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1020 } 1021 1022 int TTmpIdx = getTTmpIdx(Val); 1023 if (TTmpIdx >= 0) { 1024 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1025 } 1026 1027 if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX) 1028 return decodeIntImmed(Val); 1029 1030 if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX) 1031 return decodeFPImmed(Width, Val); 1032 1033 if (Val == LITERAL_CONST) 1034 return decodeLiteralConstant(); 1035 1036 switch (Width) { 1037 case OPW32: 1038 case OPW16: 1039 case OPWV216: 1040 return decodeSpecialReg32(Val); 1041 case OPW64: 1042 return decodeSpecialReg64(Val); 1043 default: 1044 llvm_unreachable("unexpected immediate type"); 1045 } 1046 } 1047 1048 MCOperand AMDGPUDisassembler::decodeDstOp(const OpWidthTy Width, unsigned Val) const { 1049 using namespace AMDGPU::EncValues; 1050 1051 assert(Val < 128); 1052 assert(Width == OPW256 || Width == OPW512); 1053 1054 if (Val <= SGPR_MAX) { 1055 assert(SGPR_MIN == 0); // "SGPR_MIN <= Val" is always true and causes compilation warning. 1056 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1057 } 1058 1059 int TTmpIdx = getTTmpIdx(Val); 1060 if (TTmpIdx >= 0) { 1061 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1062 } 1063 1064 llvm_unreachable("unknown dst register"); 1065 } 1066 1067 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { 1068 using namespace AMDGPU; 1069 1070 switch (Val) { 1071 case 102: return createRegOperand(FLAT_SCR_LO); 1072 case 103: return createRegOperand(FLAT_SCR_HI); 1073 case 104: return createRegOperand(XNACK_MASK_LO); 1074 case 105: return createRegOperand(XNACK_MASK_HI); 1075 case 106: return createRegOperand(VCC_LO); 1076 case 107: return createRegOperand(VCC_HI); 1077 case 108: return createRegOperand(TBA_LO); 1078 case 109: return createRegOperand(TBA_HI); 1079 case 110: return createRegOperand(TMA_LO); 1080 case 111: return createRegOperand(TMA_HI); 1081 case 124: return createRegOperand(M0); 1082 case 125: return createRegOperand(SGPR_NULL); 1083 case 126: return createRegOperand(EXEC_LO); 1084 case 127: return createRegOperand(EXEC_HI); 1085 case 235: return createRegOperand(SRC_SHARED_BASE); 1086 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1087 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1088 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1089 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1090 case 251: return createRegOperand(SRC_VCCZ); 1091 case 252: return createRegOperand(SRC_EXECZ); 1092 case 253: return createRegOperand(SRC_SCC); 1093 case 254: return createRegOperand(LDS_DIRECT); 1094 default: break; 1095 } 1096 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1097 } 1098 1099 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { 1100 using namespace AMDGPU; 1101 1102 switch (Val) { 1103 case 102: return createRegOperand(FLAT_SCR); 1104 case 104: return createRegOperand(XNACK_MASK); 1105 case 106: return createRegOperand(VCC); 1106 case 108: return createRegOperand(TBA); 1107 case 110: return createRegOperand(TMA); 1108 case 125: return createRegOperand(SGPR_NULL); 1109 case 126: return createRegOperand(EXEC); 1110 case 235: return createRegOperand(SRC_SHARED_BASE); 1111 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1112 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1113 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1114 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1115 case 251: return createRegOperand(SRC_VCCZ); 1116 case 252: return createRegOperand(SRC_EXECZ); 1117 case 253: return createRegOperand(SRC_SCC); 1118 default: break; 1119 } 1120 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1121 } 1122 1123 MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width, 1124 const unsigned Val) const { 1125 using namespace AMDGPU::SDWA; 1126 using namespace AMDGPU::EncValues; 1127 1128 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 1129 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 1130 // XXX: cast to int is needed to avoid stupid warning: 1131 // compare with unsigned is always true 1132 if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) && 1133 Val <= SDWA9EncValues::SRC_VGPR_MAX) { 1134 return createRegOperand(getVgprClassId(Width), 1135 Val - SDWA9EncValues::SRC_VGPR_MIN); 1136 } 1137 if (SDWA9EncValues::SRC_SGPR_MIN <= Val && 1138 Val <= (isGFX10Plus() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10 1139 : SDWA9EncValues::SRC_SGPR_MAX_SI)) { 1140 return createSRegOperand(getSgprClassId(Width), 1141 Val - SDWA9EncValues::SRC_SGPR_MIN); 1142 } 1143 if (SDWA9EncValues::SRC_TTMP_MIN <= Val && 1144 Val <= SDWA9EncValues::SRC_TTMP_MAX) { 1145 return createSRegOperand(getTtmpClassId(Width), 1146 Val - SDWA9EncValues::SRC_TTMP_MIN); 1147 } 1148 1149 const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN; 1150 1151 if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX) 1152 return decodeIntImmed(SVal); 1153 1154 if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX) 1155 return decodeFPImmed(Width, SVal); 1156 1157 return decodeSpecialReg32(SVal); 1158 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 1159 return createRegOperand(getVgprClassId(Width), Val); 1160 } 1161 llvm_unreachable("unsupported target"); 1162 } 1163 1164 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const { 1165 return decodeSDWASrc(OPW16, Val); 1166 } 1167 1168 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const { 1169 return decodeSDWASrc(OPW32, Val); 1170 } 1171 1172 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const { 1173 using namespace AMDGPU::SDWA; 1174 1175 assert((STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 1176 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) && 1177 "SDWAVopcDst should be present only on GFX9+"); 1178 1179 bool IsWave64 = STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64]; 1180 1181 if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) { 1182 Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK; 1183 1184 int TTmpIdx = getTTmpIdx(Val); 1185 if (TTmpIdx >= 0) { 1186 auto TTmpClsId = getTtmpClassId(IsWave64 ? OPW64 : OPW32); 1187 return createSRegOperand(TTmpClsId, TTmpIdx); 1188 } else if (Val > SGPR_MAX) { 1189 return IsWave64 ? decodeSpecialReg64(Val) 1190 : decodeSpecialReg32(Val); 1191 } else { 1192 return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val); 1193 } 1194 } else { 1195 return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO); 1196 } 1197 } 1198 1199 MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const { 1200 return STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ? 1201 decodeOperand_SReg_64(Val) : decodeOperand_SReg_32(Val); 1202 } 1203 1204 bool AMDGPUDisassembler::isVI() const { 1205 return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]; 1206 } 1207 1208 bool AMDGPUDisassembler::isGFX9() const { return AMDGPU::isGFX9(STI); } 1209 1210 bool AMDGPUDisassembler::isGFX9Plus() const { return AMDGPU::isGFX9Plus(STI); } 1211 1212 bool AMDGPUDisassembler::isGFX10() const { return AMDGPU::isGFX10(STI); } 1213 1214 bool AMDGPUDisassembler::isGFX10Plus() const { 1215 return AMDGPU::isGFX10Plus(STI); 1216 } 1217 1218 //===----------------------------------------------------------------------===// 1219 // AMDGPU specific symbol handling 1220 //===----------------------------------------------------------------------===// 1221 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1222 do { \ 1223 KdStream << Indent << DIRECTIVE " " \ 1224 << ((FourByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 1225 } while (0) 1226 1227 // NOLINTNEXTLINE(readability-identifier-naming) 1228 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1( 1229 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1230 using namespace amdhsa; 1231 StringRef Indent = "\t"; 1232 1233 // We cannot accurately backward compute #VGPRs used from 1234 // GRANULATED_WORKITEM_VGPR_COUNT. But we are concerned with getting the same 1235 // value of GRANULATED_WORKITEM_VGPR_COUNT in the reassembled binary. So we 1236 // simply calculate the inverse of what the assembler does. 1237 1238 uint32_t GranulatedWorkitemVGPRCount = 1239 (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT) >> 1240 COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT_SHIFT; 1241 1242 uint32_t NextFreeVGPR = (GranulatedWorkitemVGPRCount + 1) * 1243 AMDGPU::IsaInfo::getVGPREncodingGranule(&STI); 1244 1245 KdStream << Indent << ".amdhsa_next_free_vgpr " << NextFreeVGPR << '\n'; 1246 1247 // We cannot backward compute values used to calculate 1248 // GRANULATED_WAVEFRONT_SGPR_COUNT. Hence the original values for following 1249 // directives can't be computed: 1250 // .amdhsa_reserve_vcc 1251 // .amdhsa_reserve_flat_scratch 1252 // .amdhsa_reserve_xnack_mask 1253 // They take their respective default values if not specified in the assembly. 1254 // 1255 // GRANULATED_WAVEFRONT_SGPR_COUNT 1256 // = f(NEXT_FREE_SGPR + VCC + FLAT_SCRATCH + XNACK_MASK) 1257 // 1258 // We compute the inverse as though all directives apart from NEXT_FREE_SGPR 1259 // are set to 0. So while disassembling we consider that: 1260 // 1261 // GRANULATED_WAVEFRONT_SGPR_COUNT 1262 // = f(NEXT_FREE_SGPR + 0 + 0 + 0) 1263 // 1264 // The disassembler cannot recover the original values of those 3 directives. 1265 1266 uint32_t GranulatedWavefrontSGPRCount = 1267 (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT) >> 1268 COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT_SHIFT; 1269 1270 if (isGFX10Plus() && GranulatedWavefrontSGPRCount) 1271 return MCDisassembler::Fail; 1272 1273 uint32_t NextFreeSGPR = (GranulatedWavefrontSGPRCount + 1) * 1274 AMDGPU::IsaInfo::getSGPREncodingGranule(&STI); 1275 1276 KdStream << Indent << ".amdhsa_reserve_vcc " << 0 << '\n'; 1277 KdStream << Indent << ".amdhsa_reserve_flat_scratch " << 0 << '\n'; 1278 KdStream << Indent << ".amdhsa_reserve_xnack_mask " << 0 << '\n'; 1279 KdStream << Indent << ".amdhsa_next_free_sgpr " << NextFreeSGPR << "\n"; 1280 1281 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIORITY) 1282 return MCDisassembler::Fail; 1283 1284 PRINT_DIRECTIVE(".amdhsa_float_round_mode_32", 1285 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); 1286 PRINT_DIRECTIVE(".amdhsa_float_round_mode_16_64", 1287 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); 1288 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_32", 1289 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); 1290 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_16_64", 1291 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); 1292 1293 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIV) 1294 return MCDisassembler::Fail; 1295 1296 PRINT_DIRECTIVE(".amdhsa_dx10_clamp", COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP); 1297 1298 if (FourByteBuffer & COMPUTE_PGM_RSRC1_DEBUG_MODE) 1299 return MCDisassembler::Fail; 1300 1301 PRINT_DIRECTIVE(".amdhsa_ieee_mode", COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE); 1302 1303 if (FourByteBuffer & COMPUTE_PGM_RSRC1_BULKY) 1304 return MCDisassembler::Fail; 1305 1306 if (FourByteBuffer & COMPUTE_PGM_RSRC1_CDBG_USER) 1307 return MCDisassembler::Fail; 1308 1309 PRINT_DIRECTIVE(".amdhsa_fp16_overflow", COMPUTE_PGM_RSRC1_FP16_OVFL); 1310 1311 if (FourByteBuffer & COMPUTE_PGM_RSRC1_RESERVED0) 1312 return MCDisassembler::Fail; 1313 1314 if (isGFX10Plus()) { 1315 PRINT_DIRECTIVE(".amdhsa_workgroup_processor_mode", 1316 COMPUTE_PGM_RSRC1_WGP_MODE); 1317 PRINT_DIRECTIVE(".amdhsa_memory_ordered", COMPUTE_PGM_RSRC1_MEM_ORDERED); 1318 PRINT_DIRECTIVE(".amdhsa_forward_progress", COMPUTE_PGM_RSRC1_FWD_PROGRESS); 1319 } 1320 return MCDisassembler::Success; 1321 } 1322 1323 // NOLINTNEXTLINE(readability-identifier-naming) 1324 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2( 1325 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1326 using namespace amdhsa; 1327 StringRef Indent = "\t"; 1328 PRINT_DIRECTIVE( 1329 ".amdhsa_system_sgpr_private_segment_wavefront_offset", 1330 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1331 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_x", 1332 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); 1333 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_y", 1334 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); 1335 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_z", 1336 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); 1337 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_info", 1338 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); 1339 PRINT_DIRECTIVE(".amdhsa_system_vgpr_workitem_id", 1340 COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); 1341 1342 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_ADDRESS_WATCH) 1343 return MCDisassembler::Fail; 1344 1345 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_MEMORY) 1346 return MCDisassembler::Fail; 1347 1348 if (FourByteBuffer & COMPUTE_PGM_RSRC2_GRANULATED_LDS_SIZE) 1349 return MCDisassembler::Fail; 1350 1351 PRINT_DIRECTIVE( 1352 ".amdhsa_exception_fp_ieee_invalid_op", 1353 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); 1354 PRINT_DIRECTIVE(".amdhsa_exception_fp_denorm_src", 1355 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); 1356 PRINT_DIRECTIVE( 1357 ".amdhsa_exception_fp_ieee_div_zero", 1358 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); 1359 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_overflow", 1360 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); 1361 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_underflow", 1362 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); 1363 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_inexact", 1364 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); 1365 PRINT_DIRECTIVE(".amdhsa_exception_int_div_zero", 1366 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); 1367 1368 if (FourByteBuffer & COMPUTE_PGM_RSRC2_RESERVED0) 1369 return MCDisassembler::Fail; 1370 1371 return MCDisassembler::Success; 1372 } 1373 1374 #undef PRINT_DIRECTIVE 1375 1376 MCDisassembler::DecodeStatus 1377 AMDGPUDisassembler::decodeKernelDescriptorDirective( 1378 DataExtractor::Cursor &Cursor, ArrayRef<uint8_t> Bytes, 1379 raw_string_ostream &KdStream) const { 1380 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1381 do { \ 1382 KdStream << Indent << DIRECTIVE " " \ 1383 << ((TwoByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 1384 } while (0) 1385 1386 uint16_t TwoByteBuffer = 0; 1387 uint32_t FourByteBuffer = 0; 1388 uint64_t EightByteBuffer = 0; 1389 1390 StringRef ReservedBytes; 1391 StringRef Indent = "\t"; 1392 1393 assert(Bytes.size() == 64); 1394 DataExtractor DE(Bytes, /*IsLittleEndian=*/true, /*AddressSize=*/8); 1395 1396 switch (Cursor.tell()) { 1397 case amdhsa::GROUP_SEGMENT_FIXED_SIZE_OFFSET: 1398 FourByteBuffer = DE.getU32(Cursor); 1399 KdStream << Indent << ".amdhsa_group_segment_fixed_size " << FourByteBuffer 1400 << '\n'; 1401 return MCDisassembler::Success; 1402 1403 case amdhsa::PRIVATE_SEGMENT_FIXED_SIZE_OFFSET: 1404 FourByteBuffer = DE.getU32(Cursor); 1405 KdStream << Indent << ".amdhsa_private_segment_fixed_size " 1406 << FourByteBuffer << '\n'; 1407 return MCDisassembler::Success; 1408 1409 case amdhsa::RESERVED0_OFFSET: 1410 // 8 reserved bytes, must be 0. 1411 EightByteBuffer = DE.getU64(Cursor); 1412 if (EightByteBuffer) { 1413 return MCDisassembler::Fail; 1414 } 1415 return MCDisassembler::Success; 1416 1417 case amdhsa::KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET: 1418 // KERNEL_CODE_ENTRY_BYTE_OFFSET 1419 // So far no directive controls this for Code Object V3, so simply skip for 1420 // disassembly. 1421 DE.skip(Cursor, 8); 1422 return MCDisassembler::Success; 1423 1424 case amdhsa::RESERVED1_OFFSET: 1425 // 20 reserved bytes, must be 0. 1426 ReservedBytes = DE.getBytes(Cursor, 20); 1427 for (int I = 0; I < 20; ++I) { 1428 if (ReservedBytes[I] != 0) { 1429 return MCDisassembler::Fail; 1430 } 1431 } 1432 return MCDisassembler::Success; 1433 1434 case amdhsa::COMPUTE_PGM_RSRC3_OFFSET: 1435 // COMPUTE_PGM_RSRC3 1436 // - Only set for GFX10, GFX6-9 have this to be 0. 1437 // - Currently no directives directly control this. 1438 FourByteBuffer = DE.getU32(Cursor); 1439 if (!isGFX10Plus() && FourByteBuffer) { 1440 return MCDisassembler::Fail; 1441 } 1442 return MCDisassembler::Success; 1443 1444 case amdhsa::COMPUTE_PGM_RSRC1_OFFSET: 1445 FourByteBuffer = DE.getU32(Cursor); 1446 if (decodeCOMPUTE_PGM_RSRC1(FourByteBuffer, KdStream) == 1447 MCDisassembler::Fail) { 1448 return MCDisassembler::Fail; 1449 } 1450 return MCDisassembler::Success; 1451 1452 case amdhsa::COMPUTE_PGM_RSRC2_OFFSET: 1453 FourByteBuffer = DE.getU32(Cursor); 1454 if (decodeCOMPUTE_PGM_RSRC2(FourByteBuffer, KdStream) == 1455 MCDisassembler::Fail) { 1456 return MCDisassembler::Fail; 1457 } 1458 return MCDisassembler::Success; 1459 1460 case amdhsa::KERNEL_CODE_PROPERTIES_OFFSET: 1461 using namespace amdhsa; 1462 TwoByteBuffer = DE.getU16(Cursor); 1463 1464 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_buffer", 1465 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); 1466 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_ptr", 1467 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); 1468 PRINT_DIRECTIVE(".amdhsa_user_sgpr_queue_ptr", 1469 KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); 1470 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_segment_ptr", 1471 KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); 1472 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_id", 1473 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); 1474 PRINT_DIRECTIVE(".amdhsa_user_sgpr_flat_scratch_init", 1475 KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); 1476 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_size", 1477 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); 1478 1479 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED0) 1480 return MCDisassembler::Fail; 1481 1482 // Reserved for GFX9 1483 if (isGFX9() && 1484 (TwoByteBuffer & KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32)) { 1485 return MCDisassembler::Fail; 1486 } else if (isGFX10Plus()) { 1487 PRINT_DIRECTIVE(".amdhsa_wavefront_size32", 1488 KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 1489 } 1490 1491 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED1) 1492 return MCDisassembler::Fail; 1493 1494 return MCDisassembler::Success; 1495 1496 case amdhsa::RESERVED2_OFFSET: 1497 // 6 bytes from here are reserved, must be 0. 1498 ReservedBytes = DE.getBytes(Cursor, 6); 1499 for (int I = 0; I < 6; ++I) { 1500 if (ReservedBytes[I] != 0) 1501 return MCDisassembler::Fail; 1502 } 1503 return MCDisassembler::Success; 1504 1505 default: 1506 llvm_unreachable("Unhandled index. Case statements cover everything."); 1507 return MCDisassembler::Fail; 1508 } 1509 #undef PRINT_DIRECTIVE 1510 } 1511 1512 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeKernelDescriptor( 1513 StringRef KdName, ArrayRef<uint8_t> Bytes, uint64_t KdAddress) const { 1514 // CP microcode requires the kernel descriptor to be 64 aligned. 1515 if (Bytes.size() != 64 || KdAddress % 64 != 0) 1516 return MCDisassembler::Fail; 1517 1518 std::string Kd; 1519 raw_string_ostream KdStream(Kd); 1520 KdStream << ".amdhsa_kernel " << KdName << '\n'; 1521 1522 DataExtractor::Cursor C(0); 1523 while (C && C.tell() < Bytes.size()) { 1524 MCDisassembler::DecodeStatus Status = 1525 decodeKernelDescriptorDirective(C, Bytes, KdStream); 1526 1527 cantFail(C.takeError()); 1528 1529 if (Status == MCDisassembler::Fail) 1530 return MCDisassembler::Fail; 1531 } 1532 KdStream << ".end_amdhsa_kernel\n"; 1533 outs() << KdStream.str(); 1534 return MCDisassembler::Success; 1535 } 1536 1537 Optional<MCDisassembler::DecodeStatus> 1538 AMDGPUDisassembler::onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, 1539 ArrayRef<uint8_t> Bytes, uint64_t Address, 1540 raw_ostream &CStream) const { 1541 // Right now only kernel descriptor needs to be handled. 1542 // We ignore all other symbols for target specific handling. 1543 // TODO: 1544 // Fix the spurious symbol issue for AMDGPU kernels. Exists for both Code 1545 // Object V2 and V3 when symbols are marked protected. 1546 1547 // amd_kernel_code_t for Code Object V2. 1548 if (Symbol.Type == ELF::STT_AMDGPU_HSA_KERNEL) { 1549 Size = 256; 1550 return MCDisassembler::Fail; 1551 } 1552 1553 // Code Object V3 kernel descriptors. 1554 StringRef Name = Symbol.Name; 1555 if (Symbol.Type == ELF::STT_OBJECT && Name.endswith(StringRef(".kd"))) { 1556 Size = 64; // Size = 64 regardless of success or failure. 1557 return decodeKernelDescriptor(Name.drop_back(3), Bytes, Address); 1558 } 1559 return None; 1560 } 1561 1562 //===----------------------------------------------------------------------===// 1563 // AMDGPUSymbolizer 1564 //===----------------------------------------------------------------------===// 1565 1566 // Try to find symbol name for specified label 1567 bool AMDGPUSymbolizer::tryAddingSymbolicOperand(MCInst &Inst, 1568 raw_ostream &/*cStream*/, int64_t Value, 1569 uint64_t /*Address*/, bool IsBranch, 1570 uint64_t /*Offset*/, uint64_t /*InstSize*/) { 1571 1572 if (!IsBranch) { 1573 return false; 1574 } 1575 1576 auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo); 1577 if (!Symbols) 1578 return false; 1579 1580 auto Result = llvm::find_if(*Symbols, [Value](const SymbolInfoTy &Val) { 1581 return Val.Addr == static_cast<uint64_t>(Value) && 1582 Val.Type == ELF::STT_NOTYPE; 1583 }); 1584 if (Result != Symbols->end()) { 1585 auto *Sym = Ctx.getOrCreateSymbol(Result->Name); 1586 const auto *Add = MCSymbolRefExpr::create(Sym, Ctx); 1587 Inst.addOperand(MCOperand::createExpr(Add)); 1588 return true; 1589 } 1590 return false; 1591 } 1592 1593 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream, 1594 int64_t Value, 1595 uint64_t Address) { 1596 llvm_unreachable("unimplemented"); 1597 } 1598 1599 //===----------------------------------------------------------------------===// 1600 // Initialization 1601 //===----------------------------------------------------------------------===// 1602 1603 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/, 1604 LLVMOpInfoCallback /*GetOpInfo*/, 1605 LLVMSymbolLookupCallback /*SymbolLookUp*/, 1606 void *DisInfo, 1607 MCContext *Ctx, 1608 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 1609 return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo); 1610 } 1611 1612 static MCDisassembler *createAMDGPUDisassembler(const Target &T, 1613 const MCSubtargetInfo &STI, 1614 MCContext &Ctx) { 1615 return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo()); 1616 } 1617 1618 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler() { 1619 TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(), 1620 createAMDGPUDisassembler); 1621 TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(), 1622 createAMDGPUSymbolizer); 1623 } 1624