1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 //===----------------------------------------------------------------------===// 11 // 12 /// \file 13 /// 14 /// This file contains definition for AMDGPU ISA disassembler 15 // 16 //===----------------------------------------------------------------------===// 17 18 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)? 19 20 #include "Disassembler/AMDGPUDisassembler.h" 21 #include "AMDGPU.h" 22 #include "AMDGPURegisterInfo.h" 23 #include "SIDefines.h" 24 #include "Utils/AMDGPUBaseInfo.h" 25 #include "llvm-c/Disassembler.h" 26 #include "llvm/ADT/APInt.h" 27 #include "llvm/ADT/ArrayRef.h" 28 #include "llvm/ADT/Twine.h" 29 #include "llvm/BinaryFormat/ELF.h" 30 #include "llvm/MC/MCContext.h" 31 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 32 #include "llvm/MC/MCExpr.h" 33 #include "llvm/MC/MCFixedLenDisassembler.h" 34 #include "llvm/MC/MCInst.h" 35 #include "llvm/MC/MCSubtargetInfo.h" 36 #include "llvm/Support/Endian.h" 37 #include "llvm/Support/ErrorHandling.h" 38 #include "llvm/Support/MathExtras.h" 39 #include "llvm/Support/TargetRegistry.h" 40 #include "llvm/Support/raw_ostream.h" 41 #include <algorithm> 42 #include <cassert> 43 #include <cstddef> 44 #include <cstdint> 45 #include <iterator> 46 #include <tuple> 47 #include <vector> 48 49 using namespace llvm; 50 51 #define DEBUG_TYPE "amdgpu-disassembler" 52 53 using DecodeStatus = llvm::MCDisassembler::DecodeStatus; 54 55 inline static MCDisassembler::DecodeStatus 56 addOperand(MCInst &Inst, const MCOperand& Opnd) { 57 Inst.addOperand(Opnd); 58 return Opnd.isValid() ? 59 MCDisassembler::Success : 60 MCDisassembler::SoftFail; 61 } 62 63 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, 64 uint16_t NameIdx) { 65 int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx); 66 if (OpIdx != -1) { 67 auto I = MI.begin(); 68 std::advance(I, OpIdx); 69 MI.insert(I, Op); 70 } 71 return OpIdx; 72 } 73 74 static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm, 75 uint64_t Addr, const void *Decoder) { 76 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 77 78 APInt SignedOffset(18, Imm * 4, true); 79 int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue(); 80 81 if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2)) 82 return MCDisassembler::Success; 83 return addOperand(Inst, MCOperand::createImm(Imm)); 84 } 85 86 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \ 87 static DecodeStatus StaticDecoderName(MCInst &Inst, \ 88 unsigned Imm, \ 89 uint64_t /*Addr*/, \ 90 const void *Decoder) { \ 91 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); \ 92 return addOperand(Inst, DAsm->DecoderName(Imm)); \ 93 } 94 95 #define DECODE_OPERAND_REG(RegClass) \ 96 DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass) 97 98 DECODE_OPERAND_REG(VGPR_32) 99 DECODE_OPERAND_REG(VS_32) 100 DECODE_OPERAND_REG(VS_64) 101 DECODE_OPERAND_REG(VS_128) 102 103 DECODE_OPERAND_REG(VReg_64) 104 DECODE_OPERAND_REG(VReg_96) 105 DECODE_OPERAND_REG(VReg_128) 106 107 DECODE_OPERAND_REG(SReg_32) 108 DECODE_OPERAND_REG(SReg_32_XM0_XEXEC) 109 DECODE_OPERAND_REG(SReg_32_XEXEC_HI) 110 DECODE_OPERAND_REG(SReg_64) 111 DECODE_OPERAND_REG(SReg_64_XEXEC) 112 DECODE_OPERAND_REG(SReg_128) 113 DECODE_OPERAND_REG(SReg_256) 114 DECODE_OPERAND_REG(SReg_512) 115 116 static DecodeStatus decodeOperand_VSrc16(MCInst &Inst, 117 unsigned Imm, 118 uint64_t Addr, 119 const void *Decoder) { 120 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 121 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); 122 } 123 124 static DecodeStatus decodeOperand_VSrcV216(MCInst &Inst, 125 unsigned Imm, 126 uint64_t Addr, 127 const void *Decoder) { 128 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 129 return addOperand(Inst, DAsm->decodeOperand_VSrcV216(Imm)); 130 } 131 132 #define DECODE_SDWA(DecName) \ 133 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName) 134 135 DECODE_SDWA(Src32) 136 DECODE_SDWA(Src16) 137 DECODE_SDWA(VopcDst) 138 139 #include "AMDGPUGenDisassemblerTables.inc" 140 141 //===----------------------------------------------------------------------===// 142 // 143 //===----------------------------------------------------------------------===// 144 145 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) { 146 assert(Bytes.size() >= sizeof(T)); 147 const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data()); 148 Bytes = Bytes.slice(sizeof(T)); 149 return Res; 150 } 151 152 DecodeStatus AMDGPUDisassembler::tryDecodeInst(const uint8_t* Table, 153 MCInst &MI, 154 uint64_t Inst, 155 uint64_t Address) const { 156 assert(MI.getOpcode() == 0); 157 assert(MI.getNumOperands() == 0); 158 MCInst TmpInst; 159 HasLiteral = false; 160 const auto SavedBytes = Bytes; 161 if (decodeInstruction(Table, TmpInst, Inst, Address, this, STI)) { 162 MI = TmpInst; 163 return MCDisassembler::Success; 164 } 165 Bytes = SavedBytes; 166 return MCDisassembler::Fail; 167 } 168 169 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 170 ArrayRef<uint8_t> Bytes_, 171 uint64_t Address, 172 raw_ostream &WS, 173 raw_ostream &CS) const { 174 CommentStream = &CS; 175 bool IsSDWA = false; 176 177 // ToDo: AMDGPUDisassembler supports only VI ISA. 178 if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding]) 179 report_fatal_error("Disassembly not yet supported for subtarget"); 180 181 const unsigned MaxInstBytesNum = (std::min)((size_t)8, Bytes_.size()); 182 Bytes = Bytes_.slice(0, MaxInstBytesNum); 183 184 DecodeStatus Res = MCDisassembler::Fail; 185 do { 186 // ToDo: better to switch encoding length using some bit predicate 187 // but it is unknown yet, so try all we can 188 189 // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2 190 // encodings 191 if (Bytes.size() >= 8) { 192 const uint64_t QW = eatBytes<uint64_t>(Bytes); 193 Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address); 194 if (Res) break; 195 196 Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address); 197 if (Res) { IsSDWA = true; break; } 198 199 Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address); 200 if (Res) { IsSDWA = true; break; } 201 202 if (STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem]) { 203 Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address); 204 if (Res) break; 205 } 206 } 207 208 // Reinitialize Bytes as DPP64 could have eaten too much 209 Bytes = Bytes_.slice(0, MaxInstBytesNum); 210 211 // Try decode 32-bit instruction 212 if (Bytes.size() < 4) break; 213 const uint32_t DW = eatBytes<uint32_t>(Bytes); 214 Res = tryDecodeInst(DecoderTableVI32, MI, DW, Address); 215 if (Res) break; 216 217 Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address); 218 if (Res) break; 219 220 Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address); 221 if (Res) break; 222 223 if (Bytes.size() < 4) break; 224 const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW; 225 Res = tryDecodeInst(DecoderTableVI64, MI, QW, Address); 226 if (Res) break; 227 228 Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address); 229 if (Res) break; 230 231 Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address); 232 } while (false); 233 234 if (Res && (MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi || 235 MI.getOpcode() == AMDGPU::V_MAC_F32_e64_si || 236 MI.getOpcode() == AMDGPU::V_MAC_F16_e64_vi)) { 237 // Insert dummy unused src2_modifiers. 238 insertNamedMCOperand(MI, MCOperand::createImm(0), 239 AMDGPU::OpName::src2_modifiers); 240 } 241 242 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) { 243 Res = convertMIMGInst(MI); 244 } 245 246 if (Res && IsSDWA) 247 Res = convertSDWAInst(MI); 248 249 Size = Res ? (MaxInstBytesNum - Bytes.size()) : 0; 250 return Res; 251 } 252 253 DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const { 254 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9]) { 255 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst) != -1) 256 // VOPC - insert clamp 257 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp); 258 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 259 int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst); 260 if (SDst != -1) { 261 // VOPC - insert VCC register as sdst 262 insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC), 263 AMDGPU::OpName::sdst); 264 } else { 265 // VOP1/2 - insert omod if present in instruction 266 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod); 267 } 268 } 269 return MCDisassembler::Success; 270 } 271 272 DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const { 273 int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 274 AMDGPU::OpName::vdst); 275 276 int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 277 AMDGPU::OpName::vdata); 278 279 int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 280 AMDGPU::OpName::dmask); 281 282 assert(VDataIdx != -1); 283 assert(DMaskIdx != -1); 284 285 bool isAtomic = (VDstIdx != -1); 286 287 unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf; 288 if (DMask == 0) 289 return MCDisassembler::Success; 290 291 unsigned ChannelCount = countPopulation(DMask); 292 if (ChannelCount == 1) 293 return MCDisassembler::Success; 294 295 int NewOpcode = -1; 296 297 if (isAtomic) { 298 if (DMask == 0x1 || DMask == 0x3 || DMask == 0xF) { 299 NewOpcode = AMDGPU::getMaskedMIMGAtomicOp(*MCII, MI.getOpcode(), ChannelCount); 300 } 301 if (NewOpcode == -1) return MCDisassembler::Success; 302 } else { 303 NewOpcode = AMDGPU::getMaskedMIMGOp(*MCII, MI.getOpcode(), ChannelCount); 304 assert(NewOpcode != -1 && "could not find matching mimg channel instruction"); 305 } 306 307 auto RCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass; 308 309 // Get first subregister of VData 310 unsigned Vdata0 = MI.getOperand(VDataIdx).getReg(); 311 unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0); 312 Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0; 313 314 // Widen the register to the correct number of enabled channels. 315 auto NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0, 316 &MRI.getRegClass(RCID)); 317 if (NewVdata == AMDGPU::NoRegister) { 318 // It's possible to encode this such that the low register + enabled 319 // components exceeds the register count. 320 return MCDisassembler::Success; 321 } 322 323 MI.setOpcode(NewOpcode); 324 // vaddr will be always appear as a single VGPR. This will look different than 325 // how it is usually emitted because the number of register components is not 326 // in the instruction encoding. 327 MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata); 328 329 if (isAtomic) { 330 // Atomic operations have an additional operand (a copy of data) 331 MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata); 332 } 333 334 return MCDisassembler::Success; 335 } 336 337 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { 338 return getContext().getRegisterInfo()-> 339 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); 340 } 341 342 inline 343 MCOperand AMDGPUDisassembler::errOperand(unsigned V, 344 const Twine& ErrMsg) const { 345 *CommentStream << "Error: " + ErrMsg; 346 347 // ToDo: add support for error operands to MCInst.h 348 // return MCOperand::createError(V); 349 return MCOperand(); 350 } 351 352 inline 353 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const { 354 return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI)); 355 } 356 357 inline 358 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, 359 unsigned Val) const { 360 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; 361 if (Val >= RegCl.getNumRegs()) 362 return errOperand(Val, Twine(getRegClassName(RegClassID)) + 363 ": unknown register " + Twine(Val)); 364 return createRegOperand(RegCl.getRegister(Val)); 365 } 366 367 inline 368 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID, 369 unsigned Val) const { 370 // ToDo: SI/CI have 104 SGPRs, VI - 102 371 // Valery: here we accepting as much as we can, let assembler sort it out 372 int shift = 0; 373 switch (SRegClassID) { 374 case AMDGPU::SGPR_32RegClassID: 375 case AMDGPU::TTMP_32RegClassID: 376 break; 377 case AMDGPU::SGPR_64RegClassID: 378 case AMDGPU::TTMP_64RegClassID: 379 shift = 1; 380 break; 381 case AMDGPU::SGPR_128RegClassID: 382 case AMDGPU::TTMP_128RegClassID: 383 // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in 384 // this bundle? 385 case AMDGPU::SGPR_256RegClassID: 386 case AMDGPU::TTMP_256RegClassID: 387 // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in 388 // this bundle? 389 case AMDGPU::SGPR_512RegClassID: 390 case AMDGPU::TTMP_512RegClassID: 391 shift = 2; 392 break; 393 // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in 394 // this bundle? 395 default: 396 llvm_unreachable("unhandled register class"); 397 } 398 399 if (Val % (1 << shift)) { 400 *CommentStream << "Warning: " << getRegClassName(SRegClassID) 401 << ": scalar reg isn't aligned " << Val; 402 } 403 404 return createRegOperand(SRegClassID, Val >> shift); 405 } 406 407 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const { 408 return decodeSrcOp(OPW32, Val); 409 } 410 411 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const { 412 return decodeSrcOp(OPW64, Val); 413 } 414 415 MCOperand AMDGPUDisassembler::decodeOperand_VS_128(unsigned Val) const { 416 return decodeSrcOp(OPW128, Val); 417 } 418 419 MCOperand AMDGPUDisassembler::decodeOperand_VSrc16(unsigned Val) const { 420 return decodeSrcOp(OPW16, Val); 421 } 422 423 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV216(unsigned Val) const { 424 return decodeSrcOp(OPWV216, Val); 425 } 426 427 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const { 428 // Some instructions have operand restrictions beyond what the encoding 429 // allows. Some ordinarily VSrc_32 operands are VGPR_32, so clear the extra 430 // high bit. 431 Val &= 255; 432 433 return createRegOperand(AMDGPU::VGPR_32RegClassID, Val); 434 } 435 436 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const { 437 return createRegOperand(AMDGPU::VReg_64RegClassID, Val); 438 } 439 440 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const { 441 return createRegOperand(AMDGPU::VReg_96RegClassID, Val); 442 } 443 444 MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const { 445 return createRegOperand(AMDGPU::VReg_128RegClassID, Val); 446 } 447 448 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const { 449 // table-gen generated disassembler doesn't care about operand types 450 // leaving only registry class so SSrc_32 operand turns into SReg_32 451 // and therefore we accept immediates and literals here as well 452 return decodeSrcOp(OPW32, Val); 453 } 454 455 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0_XEXEC( 456 unsigned Val) const { 457 // SReg_32_XM0 is SReg_32 without M0 or EXEC_LO/EXEC_HI 458 return decodeOperand_SReg_32(Val); 459 } 460 461 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XEXEC_HI( 462 unsigned Val) const { 463 // SReg_32_XM0 is SReg_32 without EXEC_HI 464 return decodeOperand_SReg_32(Val); 465 } 466 467 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const { 468 return decodeSrcOp(OPW64, Val); 469 } 470 471 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64_XEXEC(unsigned Val) const { 472 return decodeSrcOp(OPW64, Val); 473 } 474 475 MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const { 476 return decodeSrcOp(OPW128, Val); 477 } 478 479 MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const { 480 return decodeDstOp(OPW256, Val); 481 } 482 483 MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const { 484 return decodeDstOp(OPW512, Val); 485 } 486 487 MCOperand AMDGPUDisassembler::decodeLiteralConstant() const { 488 // For now all literal constants are supposed to be unsigned integer 489 // ToDo: deal with signed/unsigned 64-bit integer constants 490 // ToDo: deal with float/double constants 491 if (!HasLiteral) { 492 if (Bytes.size() < 4) { 493 return errOperand(0, "cannot read literal, inst bytes left " + 494 Twine(Bytes.size())); 495 } 496 HasLiteral = true; 497 Literal = eatBytes<uint32_t>(Bytes); 498 } 499 return MCOperand::createImm(Literal); 500 } 501 502 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) { 503 using namespace AMDGPU::EncValues; 504 505 assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX); 506 return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ? 507 (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) : 508 (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm))); 509 // Cast prevents negative overflow. 510 } 511 512 static int64_t getInlineImmVal32(unsigned Imm) { 513 switch (Imm) { 514 case 240: 515 return FloatToBits(0.5f); 516 case 241: 517 return FloatToBits(-0.5f); 518 case 242: 519 return FloatToBits(1.0f); 520 case 243: 521 return FloatToBits(-1.0f); 522 case 244: 523 return FloatToBits(2.0f); 524 case 245: 525 return FloatToBits(-2.0f); 526 case 246: 527 return FloatToBits(4.0f); 528 case 247: 529 return FloatToBits(-4.0f); 530 case 248: // 1 / (2 * PI) 531 return 0x3e22f983; 532 default: 533 llvm_unreachable("invalid fp inline imm"); 534 } 535 } 536 537 static int64_t getInlineImmVal64(unsigned Imm) { 538 switch (Imm) { 539 case 240: 540 return DoubleToBits(0.5); 541 case 241: 542 return DoubleToBits(-0.5); 543 case 242: 544 return DoubleToBits(1.0); 545 case 243: 546 return DoubleToBits(-1.0); 547 case 244: 548 return DoubleToBits(2.0); 549 case 245: 550 return DoubleToBits(-2.0); 551 case 246: 552 return DoubleToBits(4.0); 553 case 247: 554 return DoubleToBits(-4.0); 555 case 248: // 1 / (2 * PI) 556 return 0x3fc45f306dc9c882; 557 default: 558 llvm_unreachable("invalid fp inline imm"); 559 } 560 } 561 562 static int64_t getInlineImmVal16(unsigned Imm) { 563 switch (Imm) { 564 case 240: 565 return 0x3800; 566 case 241: 567 return 0xB800; 568 case 242: 569 return 0x3C00; 570 case 243: 571 return 0xBC00; 572 case 244: 573 return 0x4000; 574 case 245: 575 return 0xC000; 576 case 246: 577 return 0x4400; 578 case 247: 579 return 0xC400; 580 case 248: // 1 / (2 * PI) 581 return 0x3118; 582 default: 583 llvm_unreachable("invalid fp inline imm"); 584 } 585 } 586 587 MCOperand AMDGPUDisassembler::decodeFPImmed(OpWidthTy Width, unsigned Imm) { 588 assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN 589 && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX); 590 591 // ToDo: case 248: 1/(2*PI) - is allowed only on VI 592 switch (Width) { 593 case OPW32: 594 return MCOperand::createImm(getInlineImmVal32(Imm)); 595 case OPW64: 596 return MCOperand::createImm(getInlineImmVal64(Imm)); 597 case OPW16: 598 case OPWV216: 599 return MCOperand::createImm(getInlineImmVal16(Imm)); 600 default: 601 llvm_unreachable("implement me"); 602 } 603 } 604 605 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const { 606 using namespace AMDGPU; 607 608 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 609 switch (Width) { 610 default: // fall 611 case OPW32: 612 case OPW16: 613 case OPWV216: 614 return VGPR_32RegClassID; 615 case OPW64: return VReg_64RegClassID; 616 case OPW128: return VReg_128RegClassID; 617 } 618 } 619 620 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const { 621 using namespace AMDGPU; 622 623 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 624 switch (Width) { 625 default: // fall 626 case OPW32: 627 case OPW16: 628 case OPWV216: 629 return SGPR_32RegClassID; 630 case OPW64: return SGPR_64RegClassID; 631 case OPW128: return SGPR_128RegClassID; 632 case OPW256: return SGPR_256RegClassID; 633 case OPW512: return SGPR_512RegClassID; 634 } 635 } 636 637 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const { 638 using namespace AMDGPU; 639 640 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 641 switch (Width) { 642 default: // fall 643 case OPW32: 644 case OPW16: 645 case OPWV216: 646 return TTMP_32RegClassID; 647 case OPW64: return TTMP_64RegClassID; 648 case OPW128: return TTMP_128RegClassID; 649 case OPW256: return TTMP_256RegClassID; 650 case OPW512: return TTMP_512RegClassID; 651 } 652 } 653 654 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const { 655 using namespace AMDGPU::EncValues; 656 657 unsigned TTmpMin = isGFX9() ? TTMP_GFX9_MIN : TTMP_VI_MIN; 658 unsigned TTmpMax = isGFX9() ? TTMP_GFX9_MAX : TTMP_VI_MAX; 659 660 return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1; 661 } 662 663 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val) const { 664 using namespace AMDGPU::EncValues; 665 666 assert(Val < 512); // enum9 667 668 if (VGPR_MIN <= Val && Val <= VGPR_MAX) { 669 return createRegOperand(getVgprClassId(Width), Val - VGPR_MIN); 670 } 671 if (Val <= SGPR_MAX) { 672 assert(SGPR_MIN == 0); // "SGPR_MIN <= Val" is always true and causes compilation warning. 673 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 674 } 675 676 int TTmpIdx = getTTmpIdx(Val); 677 if (TTmpIdx >= 0) { 678 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 679 } 680 681 if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX) 682 return decodeIntImmed(Val); 683 684 if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX) 685 return decodeFPImmed(Width, Val); 686 687 if (Val == LITERAL_CONST) 688 return decodeLiteralConstant(); 689 690 switch (Width) { 691 case OPW32: 692 case OPW16: 693 case OPWV216: 694 return decodeSpecialReg32(Val); 695 case OPW64: 696 return decodeSpecialReg64(Val); 697 default: 698 llvm_unreachable("unexpected immediate type"); 699 } 700 } 701 702 MCOperand AMDGPUDisassembler::decodeDstOp(const OpWidthTy Width, unsigned Val) const { 703 using namespace AMDGPU::EncValues; 704 705 assert(Val < 128); 706 assert(Width == OPW256 || Width == OPW512); 707 708 if (Val <= SGPR_MAX) { 709 assert(SGPR_MIN == 0); // "SGPR_MIN <= Val" is always true and causes compilation warning. 710 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 711 } 712 713 int TTmpIdx = getTTmpIdx(Val); 714 if (TTmpIdx >= 0) { 715 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 716 } 717 718 llvm_unreachable("unknown dst register"); 719 } 720 721 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { 722 using namespace AMDGPU; 723 724 switch (Val) { 725 case 102: return createRegOperand(FLAT_SCR_LO); 726 case 103: return createRegOperand(FLAT_SCR_HI); 727 case 104: return createRegOperand(XNACK_MASK_LO); 728 case 105: return createRegOperand(XNACK_MASK_HI); 729 case 106: return createRegOperand(VCC_LO); 730 case 107: return createRegOperand(VCC_HI); 731 case 108: assert(!isGFX9()); return createRegOperand(TBA_LO); 732 case 109: assert(!isGFX9()); return createRegOperand(TBA_HI); 733 case 110: assert(!isGFX9()); return createRegOperand(TMA_LO); 734 case 111: assert(!isGFX9()); return createRegOperand(TMA_HI); 735 case 124: return createRegOperand(M0); 736 case 126: return createRegOperand(EXEC_LO); 737 case 127: return createRegOperand(EXEC_HI); 738 case 235: return createRegOperand(SRC_SHARED_BASE); 739 case 236: return createRegOperand(SRC_SHARED_LIMIT); 740 case 237: return createRegOperand(SRC_PRIVATE_BASE); 741 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 742 // TODO: SRC_POPS_EXITING_WAVE_ID 743 // ToDo: no support for vccz register 744 case 251: break; 745 // ToDo: no support for execz register 746 case 252: break; 747 case 253: return createRegOperand(SCC); 748 default: break; 749 } 750 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 751 } 752 753 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { 754 using namespace AMDGPU; 755 756 switch (Val) { 757 case 102: return createRegOperand(FLAT_SCR); 758 case 104: return createRegOperand(XNACK_MASK); 759 case 106: return createRegOperand(VCC); 760 case 108: assert(!isGFX9()); return createRegOperand(TBA); 761 case 110: assert(!isGFX9()); return createRegOperand(TMA); 762 case 126: return createRegOperand(EXEC); 763 default: break; 764 } 765 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 766 } 767 768 MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width, 769 const unsigned Val) const { 770 using namespace AMDGPU::SDWA; 771 using namespace AMDGPU::EncValues; 772 773 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9]) { 774 // XXX: static_cast<int> is needed to avoid stupid warning: 775 // compare with unsigned is always true 776 if (SDWA9EncValues::SRC_VGPR_MIN <= static_cast<int>(Val) && 777 Val <= SDWA9EncValues::SRC_VGPR_MAX) { 778 return createRegOperand(getVgprClassId(Width), 779 Val - SDWA9EncValues::SRC_VGPR_MIN); 780 } 781 if (SDWA9EncValues::SRC_SGPR_MIN <= Val && 782 Val <= SDWA9EncValues::SRC_SGPR_MAX) { 783 return createSRegOperand(getSgprClassId(Width), 784 Val - SDWA9EncValues::SRC_SGPR_MIN); 785 } 786 if (SDWA9EncValues::SRC_TTMP_MIN <= Val && 787 Val <= SDWA9EncValues::SRC_TTMP_MAX) { 788 return createSRegOperand(getTtmpClassId(Width), 789 Val - SDWA9EncValues::SRC_TTMP_MIN); 790 } 791 792 const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN; 793 794 if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX) 795 return decodeIntImmed(SVal); 796 797 if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX) 798 return decodeFPImmed(Width, SVal); 799 800 return decodeSpecialReg32(SVal); 801 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 802 return createRegOperand(getVgprClassId(Width), Val); 803 } 804 llvm_unreachable("unsupported target"); 805 } 806 807 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const { 808 return decodeSDWASrc(OPW16, Val); 809 } 810 811 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const { 812 return decodeSDWASrc(OPW32, Val); 813 } 814 815 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const { 816 using namespace AMDGPU::SDWA; 817 818 assert(STI.getFeatureBits()[AMDGPU::FeatureGFX9] && 819 "SDWAVopcDst should be present only on GFX9"); 820 if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) { 821 Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK; 822 823 int TTmpIdx = getTTmpIdx(Val); 824 if (TTmpIdx >= 0) { 825 return createSRegOperand(getTtmpClassId(OPW64), TTmpIdx); 826 } else if (Val > AMDGPU::EncValues::SGPR_MAX) { 827 return decodeSpecialReg64(Val); 828 } else { 829 return createSRegOperand(getSgprClassId(OPW64), Val); 830 } 831 } else { 832 return createRegOperand(AMDGPU::VCC); 833 } 834 } 835 836 bool AMDGPUDisassembler::isVI() const { 837 return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]; 838 } 839 840 bool AMDGPUDisassembler::isGFX9() const { 841 return STI.getFeatureBits()[AMDGPU::FeatureGFX9]; 842 } 843 844 //===----------------------------------------------------------------------===// 845 // AMDGPUSymbolizer 846 //===----------------------------------------------------------------------===// 847 848 // Try to find symbol name for specified label 849 bool AMDGPUSymbolizer::tryAddingSymbolicOperand(MCInst &Inst, 850 raw_ostream &/*cStream*/, int64_t Value, 851 uint64_t /*Address*/, bool IsBranch, 852 uint64_t /*Offset*/, uint64_t /*InstSize*/) { 853 using SymbolInfoTy = std::tuple<uint64_t, StringRef, uint8_t>; 854 using SectionSymbolsTy = std::vector<SymbolInfoTy>; 855 856 if (!IsBranch) { 857 return false; 858 } 859 860 auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo); 861 auto Result = std::find_if(Symbols->begin(), Symbols->end(), 862 [Value](const SymbolInfoTy& Val) { 863 return std::get<0>(Val) == static_cast<uint64_t>(Value) 864 && std::get<2>(Val) == ELF::STT_NOTYPE; 865 }); 866 if (Result != Symbols->end()) { 867 auto *Sym = Ctx.getOrCreateSymbol(std::get<1>(*Result)); 868 const auto *Add = MCSymbolRefExpr::create(Sym, Ctx); 869 Inst.addOperand(MCOperand::createExpr(Add)); 870 return true; 871 } 872 return false; 873 } 874 875 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream, 876 int64_t Value, 877 uint64_t Address) { 878 llvm_unreachable("unimplemented"); 879 } 880 881 //===----------------------------------------------------------------------===// 882 // Initialization 883 //===----------------------------------------------------------------------===// 884 885 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/, 886 LLVMOpInfoCallback /*GetOpInfo*/, 887 LLVMSymbolLookupCallback /*SymbolLookUp*/, 888 void *DisInfo, 889 MCContext *Ctx, 890 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 891 return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo); 892 } 893 894 static MCDisassembler *createAMDGPUDisassembler(const Target &T, 895 const MCSubtargetInfo &STI, 896 MCContext &Ctx) { 897 return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo()); 898 } 899 900 extern "C" void LLVMInitializeAMDGPUDisassembler() { 901 TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(), 902 createAMDGPUDisassembler); 903 TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(), 904 createAMDGPUSymbolizer); 905 } 906