1//===-- DSInstructions.td - DS Instruction Defintions ---------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9class DS_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> pattern=[]> :
10  InstSI <outs, ins, "", pattern>,
11  SIMCInstr <opName, SIEncodingFamily.NONE> {
12
13  let LGKM_CNT = 1;
14  let DS = 1;
15  let Size = 8;
16  let UseNamedOperandTable = 1;
17
18  // Most instruction load and store data, so set this as the default.
19  let mayLoad = 1;
20  let mayStore = 1;
21  let maybeAtomic = 1;
22
23  let hasSideEffects = 0;
24  let SchedRW = [WriteLDS];
25
26  let isPseudo = 1;
27  let isCodeGenOnly = 1;
28
29  let AsmMatchConverter = "cvtDS";
30
31  string Mnemonic = opName;
32  string AsmOperands = asmOps;
33
34  // Well these bits a kind of hack because it would be more natural
35  // to test "outs" and "ins" dags for the presence of particular operands
36  bits<1> has_vdst = 1;
37  bits<1> has_addr = 1;
38  bits<1> has_data0 = 1;
39  bits<1> has_data1 = 1;
40
41  bits<1> has_gws_data0 = 0; // data0 is encoded as addr
42
43  bits<1> has_offset  = 1; // has "offset" that should be split to offset0,1
44  bits<1> has_offset0 = 1;
45  bits<1> has_offset1 = 1;
46
47  bits<1> has_gds = 1;
48  bits<1> gdsValue = 0; // if has_gds == 0 set gds to this value
49
50  bits<1> has_m0_read = 1;
51
52  let Uses = !if(has_m0_read, [M0, EXEC], [EXEC]);
53}
54
55class DS_Real <DS_Pseudo ds> :
56  InstSI <ds.OutOperandList, ds.InOperandList, ds.Mnemonic # " " # ds.AsmOperands, []>,
57  Enc64 {
58
59  let isPseudo = 0;
60  let isCodeGenOnly = 0;
61  let DS = 1;
62  let UseNamedOperandTable = 1;
63
64  // copy relevant pseudo op flags
65  let SubtargetPredicate = ds.SubtargetPredicate;
66  let OtherPredicates = ds.OtherPredicates;
67  let AsmMatchConverter  = ds.AsmMatchConverter;
68
69  // encoding fields
70  bits<8> vdst;
71  bits<1> gds;
72  bits<8> addr;
73  bits<8> data0;
74  bits<8> data1;
75  bits<8> offset0;
76  bits<8> offset1;
77
78  bits<16> offset;
79  let offset0 = !if(ds.has_offset, offset{7-0}, ?);
80  let offset1 = !if(ds.has_offset, offset{15-8}, ?);
81}
82
83
84// DS Pseudo instructions
85
86class DS_0A1D_NORET<string opName, RegisterClass rc = VGPR_32>
87: DS_Pseudo<opName,
88  (outs),
89  (ins rc:$data0, offset:$offset, gds:$gds),
90  "$data0$offset$gds"> {
91
92  let has_addr = 0;
93  let has_data1 = 0;
94  let has_vdst = 0;
95}
96
97class DS_1A1D_NORET<string opName, RegisterClass rc = VGPR_32>
98: DS_Pseudo<opName,
99  (outs),
100  (ins VGPR_32:$addr, rc:$data0, offset:$offset, gds:$gds),
101  "$addr, $data0$offset$gds"> {
102
103  let has_data1 = 0;
104  let has_vdst = 0;
105}
106
107multiclass DS_1A1D_NORET_mc<string opName, RegisterClass rc = VGPR_32> {
108  def "" : DS_1A1D_NORET<opName, rc>,
109           AtomicNoRet<opName, 0>;
110
111  let has_m0_read = 0 in {
112    def _gfx9 : DS_1A1D_NORET<opName, rc>,
113                AtomicNoRet<opName#"_gfx9", 0>;
114  }
115}
116
117class DS_1A2D_NORET<string opName, RegisterClass rc = VGPR_32>
118: DS_Pseudo<opName,
119  (outs),
120  (ins VGPR_32:$addr, rc:$data0, rc:$data1, offset:$offset, gds:$gds),
121  "$addr, $data0, $data1"#"$offset"#"$gds"> {
122
123  let has_vdst = 0;
124}
125
126multiclass DS_1A2D_NORET_mc<string opName, RegisterClass rc = VGPR_32> {
127  def "" : DS_1A2D_NORET<opName, rc>,
128           AtomicNoRet<opName, 0>;
129
130  let has_m0_read = 0 in {
131    def _gfx9 : DS_1A2D_NORET<opName, rc>,
132                AtomicNoRet<opName#"_gfx9", 0>;
133  }
134}
135
136class DS_1A2D_Off8_NORET <string opName, RegisterClass rc = VGPR_32>
137: DS_Pseudo<opName,
138  (outs),
139  (ins VGPR_32:$addr, rc:$data0, rc:$data1,
140       offset0:$offset0, offset1:$offset1, gds:$gds),
141  "$addr, $data0, $data1$offset0$offset1$gds"> {
142
143  let has_vdst = 0;
144  let has_offset = 0;
145  let AsmMatchConverter = "cvtDSOffset01";
146}
147
148multiclass DS_1A2D_Off8_NORET_mc <string opName, RegisterClass rc = VGPR_32> {
149  def "" : DS_1A2D_Off8_NORET<opName, rc>;
150
151  let has_m0_read = 0 in {
152    def _gfx9 : DS_1A2D_Off8_NORET<opName, rc>;
153  }
154}
155
156class DS_1A1D_RET <string opName, RegisterClass rc = VGPR_32>
157: DS_Pseudo<opName,
158  (outs rc:$vdst),
159  (ins VGPR_32:$addr, rc:$data0, offset:$offset, gds:$gds),
160  "$vdst, $addr, $data0$offset$gds"> {
161
162  let hasPostISelHook = 1;
163  let has_data1 = 0;
164}
165
166multiclass DS_1A1D_RET_mc <string opName, RegisterClass rc = VGPR_32,
167                           string NoRetOp = ""> {
168  def "" : DS_1A1D_RET<opName, rc>,
169    AtomicNoRet<NoRetOp, !if(!eq(NoRetOp, ""), 0, 1)>;
170
171  let has_m0_read = 0 in {
172    def _gfx9 : DS_1A1D_RET<opName, rc>,
173      AtomicNoRet<!if(!eq(NoRetOp, ""), "", NoRetOp#"_gfx9"),
174                  !if(!eq(NoRetOp, ""), 0, 1)>;
175  }
176}
177
178class DS_1A2D_RET<string opName,
179                  RegisterClass rc = VGPR_32,
180                  RegisterClass src = rc>
181: DS_Pseudo<opName,
182  (outs rc:$vdst),
183  (ins VGPR_32:$addr, src:$data0, src:$data1, offset:$offset, gds:$gds),
184  "$vdst, $addr, $data0, $data1$offset$gds"> {
185
186  let hasPostISelHook = 1;
187}
188
189multiclass DS_1A2D_RET_mc<string opName,
190                          RegisterClass rc = VGPR_32,
191                          string NoRetOp = "",
192                          RegisterClass src = rc> {
193  def "" : DS_1A2D_RET<opName, rc, src>,
194    AtomicNoRet<NoRetOp, !if(!eq(NoRetOp, ""), 0, 1)>;
195
196  let has_m0_read = 0 in {
197    def _gfx9 : DS_1A2D_RET<opName, rc, src>,
198      AtomicNoRet<NoRetOp#"_gfx9", !if(!eq(NoRetOp, ""), 0, 1)>;
199  }
200}
201
202class DS_1A2D_Off8_RET<string opName,
203                       RegisterClass rc = VGPR_32,
204                       RegisterClass src = rc>
205: DS_Pseudo<opName,
206  (outs rc:$vdst),
207  (ins VGPR_32:$addr, src:$data0, src:$data1, offset0:$offset0, offset1:$offset1, gds:$gds),
208  "$vdst, $addr, $data0, $data1$offset0$offset1$gds"> {
209
210  let has_offset = 0;
211  let AsmMatchConverter = "cvtDSOffset01";
212
213  let hasPostISelHook = 1;
214}
215
216multiclass DS_1A2D_Off8_RET_mc<string opName,
217                               RegisterClass rc = VGPR_32,
218                               RegisterClass src = rc> {
219  def "" : DS_1A2D_Off8_RET<opName, rc, src>;
220
221  let has_m0_read = 0 in {
222    def _gfx9 : DS_1A2D_Off8_RET<opName, rc, src>;
223  }
224}
225
226
227class DS_1A_RET<string opName, RegisterClass rc = VGPR_32, bit HasTiedOutput = 0, Operand ofs = offset>
228: DS_Pseudo<opName,
229  (outs rc:$vdst),
230  !if(HasTiedOutput,
231    (ins VGPR_32:$addr, ofs:$offset, gds:$gds, rc:$vdst_in),
232    (ins VGPR_32:$addr, ofs:$offset, gds:$gds)),
233  "$vdst, $addr$offset$gds"> {
234  let Constraints = !if(HasTiedOutput, "$vdst = $vdst_in", "");
235  let DisableEncoding = !if(HasTiedOutput, "$vdst_in", "");
236  let has_data0 = 0;
237  let has_data1 = 0;
238}
239
240multiclass DS_1A_RET_mc<string opName, RegisterClass rc = VGPR_32, bit HasTiedOutput = 0, Operand ofs = offset> {
241  def "" : DS_1A_RET<opName, rc, HasTiedOutput, ofs>;
242
243  let has_m0_read = 0 in {
244    def _gfx9 : DS_1A_RET<opName, rc, HasTiedOutput, ofs>;
245  }
246}
247
248class DS_1A_RET_Tied<string opName, RegisterClass rc = VGPR_32> :
249  DS_1A_RET<opName, rc, 1>;
250
251class DS_1A_Off8_RET <string opName, RegisterClass rc = VGPR_32>
252: DS_Pseudo<opName,
253  (outs rc:$vdst),
254  (ins VGPR_32:$addr, offset0:$offset0, offset1:$offset1, gds:$gds),
255  "$vdst, $addr$offset0$offset1$gds"> {
256
257  let has_offset = 0;
258  let has_data0 = 0;
259  let has_data1 = 0;
260  let AsmMatchConverter = "cvtDSOffset01";
261}
262
263multiclass DS_1A_Off8_RET_mc <string opName, RegisterClass rc = VGPR_32> {
264  def "" : DS_1A_Off8_RET<opName, rc>;
265
266  let has_m0_read = 0 in {
267    def _gfx9 : DS_1A_Off8_RET<opName, rc>;
268  }
269}
270
271class DS_1A_RET_GDS <string opName> : DS_Pseudo<opName,
272  (outs VGPR_32:$vdst),
273  (ins VGPR_32:$addr, offset:$offset),
274  "$vdst, $addr$offset gds"> {
275
276  let has_data0 = 0;
277  let has_data1 = 0;
278  let has_gds = 0;
279  let gdsValue = 1;
280  let AsmMatchConverter = "cvtDSGds";
281}
282
283class DS_0A_RET <string opName> : DS_Pseudo<opName,
284  (outs VGPR_32:$vdst),
285  (ins offset:$offset, gds:$gds),
286  "$vdst$offset$gds"> {
287
288  let mayLoad = 1;
289  let mayStore = 1;
290
291  let has_addr = 0;
292  let has_data0 = 0;
293  let has_data1 = 0;
294}
295
296class DS_1A <string opName> : DS_Pseudo<opName,
297  (outs),
298  (ins VGPR_32:$addr, offset:$offset, gds:$gds),
299  "$addr$offset$gds"> {
300
301  let mayLoad = 1;
302  let mayStore = 1;
303
304  let has_vdst = 0;
305  let has_data0 = 0;
306  let has_data1 = 0;
307}
308
309multiclass DS_1A_mc <string opName> {
310  def "" : DS_1A<opName>;
311
312  let has_m0_read = 0 in {
313    def _gfx9 : DS_1A<opName>;
314  }
315}
316
317
318class DS_GWS <string opName, dag ins, string asmOps>
319: DS_Pseudo<opName, (outs), ins, asmOps> {
320
321  let has_vdst  = 0;
322  let has_addr  = 0;
323  let has_data0 = 0;
324  let has_data1 = 0;
325
326  let has_gds   = 0;
327  let gdsValue  = 1;
328  let AsmMatchConverter = "cvtDSGds";
329}
330
331class DS_GWS_0D <string opName>
332: DS_GWS<opName,
333  (ins offset:$offset, gds:$gds), "$offset gds"> {
334  let hasSideEffects = 1;
335}
336
337class DS_GWS_1D <string opName>
338: DS_GWS<opName,
339  (ins VGPR_32:$data0, offset:$offset, gds:$gds), "$data0$offset gds"> {
340
341  let has_gws_data0 = 1;
342  let hasSideEffects = 1;
343}
344
345class DS_VOID <string opName> : DS_Pseudo<opName,
346  (outs), (ins), ""> {
347  let mayLoad = 0;
348  let mayStore = 0;
349  let hasSideEffects = 1;
350  let UseNamedOperandTable = 0;
351  let AsmMatchConverter = "";
352
353  let has_vdst = 0;
354  let has_addr = 0;
355  let has_data0 = 0;
356  let has_data1 = 0;
357  let has_offset = 0;
358  let has_offset0 = 0;
359  let has_offset1 = 0;
360  let has_gds = 0;
361}
362
363class DS_1A1D_PERMUTE <string opName, SDPatternOperator node = null_frag>
364: DS_Pseudo<opName,
365  (outs VGPR_32:$vdst),
366  (ins VGPR_32:$addr, VGPR_32:$data0, offset:$offset),
367  "$vdst, $addr, $data0$offset",
368  [(set i32:$vdst,
369   (node (DS1Addr1Offset i32:$addr, i16:$offset), i32:$data0))] > {
370
371  let mayLoad = 0;
372  let mayStore = 0;
373  let isConvergent = 1;
374
375  let has_data1 = 0;
376  let has_gds = 0;
377}
378
379defm DS_ADD_U32       : DS_1A1D_NORET_mc<"ds_add_u32">;
380defm DS_SUB_U32       : DS_1A1D_NORET_mc<"ds_sub_u32">;
381defm DS_RSUB_U32      : DS_1A1D_NORET_mc<"ds_rsub_u32">;
382defm DS_INC_U32       : DS_1A1D_NORET_mc<"ds_inc_u32">;
383defm DS_DEC_U32       : DS_1A1D_NORET_mc<"ds_dec_u32">;
384defm DS_MIN_I32       : DS_1A1D_NORET_mc<"ds_min_i32">;
385defm DS_MAX_I32       : DS_1A1D_NORET_mc<"ds_max_i32">;
386defm DS_MIN_U32       : DS_1A1D_NORET_mc<"ds_min_u32">;
387defm DS_MAX_U32       : DS_1A1D_NORET_mc<"ds_max_u32">;
388defm DS_AND_B32       : DS_1A1D_NORET_mc<"ds_and_b32">;
389defm DS_OR_B32        : DS_1A1D_NORET_mc<"ds_or_b32">;
390defm DS_XOR_B32       : DS_1A1D_NORET_mc<"ds_xor_b32">;
391defm DS_ADD_F32       : DS_1A1D_NORET_mc<"ds_add_f32">;
392defm DS_MIN_F32       : DS_1A1D_NORET_mc<"ds_min_f32">;
393defm DS_MAX_F32       : DS_1A1D_NORET_mc<"ds_max_f32">;
394
395let mayLoad = 0 in {
396defm DS_WRITE_B8      : DS_1A1D_NORET_mc<"ds_write_b8">;
397defm DS_WRITE_B16     : DS_1A1D_NORET_mc<"ds_write_b16">;
398defm DS_WRITE_B32     : DS_1A1D_NORET_mc<"ds_write_b32">;
399defm DS_WRITE2_B32    : DS_1A2D_Off8_NORET_mc<"ds_write2_b32">;
400defm DS_WRITE2ST64_B32: DS_1A2D_Off8_NORET_mc<"ds_write2st64_b32">;
401
402
403let has_m0_read = 0 in {
404
405let SubtargetPredicate = HasD16LoadStore in {
406def DS_WRITE_B8_D16_HI  : DS_1A1D_NORET<"ds_write_b8_d16_hi">;
407def DS_WRITE_B16_D16_HI : DS_1A1D_NORET<"ds_write_b16_d16_hi">;
408}
409
410} // End has_m0_read = 0
411
412let SubtargetPredicate = HasDSAddTid in {
413def DS_WRITE_ADDTID_B32 : DS_0A1D_NORET<"ds_write_addtid_b32">;
414}
415
416} // End mayLoad = 0
417
418defm DS_MSKOR_B32     : DS_1A2D_NORET_mc<"ds_mskor_b32">;
419defm DS_CMPST_B32     : DS_1A2D_NORET_mc<"ds_cmpst_b32">;
420defm DS_CMPST_F32     : DS_1A2D_NORET_mc<"ds_cmpst_f32">;
421
422defm DS_ADD_U64       : DS_1A1D_NORET_mc<"ds_add_u64", VReg_64>;
423defm DS_SUB_U64       : DS_1A1D_NORET_mc<"ds_sub_u64", VReg_64>;
424defm DS_RSUB_U64      : DS_1A1D_NORET_mc<"ds_rsub_u64", VReg_64>;
425defm DS_INC_U64       : DS_1A1D_NORET_mc<"ds_inc_u64", VReg_64>;
426defm DS_DEC_U64       : DS_1A1D_NORET_mc<"ds_dec_u64", VReg_64>;
427defm DS_MIN_I64       : DS_1A1D_NORET_mc<"ds_min_i64", VReg_64>;
428defm DS_MAX_I64       : DS_1A1D_NORET_mc<"ds_max_i64", VReg_64>;
429defm DS_MIN_U64       : DS_1A1D_NORET_mc<"ds_min_u64", VReg_64>;
430defm DS_MAX_U64       : DS_1A1D_NORET_mc<"ds_max_u64", VReg_64>;
431defm DS_AND_B64       : DS_1A1D_NORET_mc<"ds_and_b64", VReg_64>;
432defm DS_OR_B64        : DS_1A1D_NORET_mc<"ds_or_b64", VReg_64>;
433defm DS_XOR_B64       : DS_1A1D_NORET_mc<"ds_xor_b64", VReg_64>;
434defm DS_MSKOR_B64     : DS_1A2D_NORET_mc<"ds_mskor_b64", VReg_64>;
435let mayLoad = 0 in {
436defm DS_WRITE_B64     : DS_1A1D_NORET_mc<"ds_write_b64", VReg_64>;
437defm DS_WRITE2_B64    : DS_1A2D_Off8_NORET_mc<"ds_write2_b64", VReg_64>;
438defm DS_WRITE2ST64_B64: DS_1A2D_Off8_NORET_mc<"ds_write2st64_b64", VReg_64>;
439}
440defm DS_CMPST_B64     : DS_1A2D_NORET_mc<"ds_cmpst_b64", VReg_64>;
441defm DS_CMPST_F64     : DS_1A2D_NORET_mc<"ds_cmpst_f64", VReg_64>;
442defm DS_MIN_F64       : DS_1A1D_NORET_mc<"ds_min_f64", VReg_64>;
443defm DS_MAX_F64       : DS_1A1D_NORET_mc<"ds_max_f64", VReg_64>;
444
445defm DS_ADD_RTN_U32   : DS_1A1D_RET_mc<"ds_add_rtn_u32", VGPR_32, "ds_add_u32">;
446defm DS_ADD_RTN_F32   : DS_1A1D_RET_mc<"ds_add_rtn_f32", VGPR_32, "ds_add_f32">;
447defm DS_SUB_RTN_U32   : DS_1A1D_RET_mc<"ds_sub_rtn_u32", VGPR_32, "ds_sub_u32">;
448defm DS_RSUB_RTN_U32  : DS_1A1D_RET_mc<"ds_rsub_rtn_u32", VGPR_32, "ds_rsub_u32">;
449defm DS_INC_RTN_U32   : DS_1A1D_RET_mc<"ds_inc_rtn_u32", VGPR_32, "ds_inc_u32">;
450defm DS_DEC_RTN_U32   : DS_1A1D_RET_mc<"ds_dec_rtn_u32", VGPR_32, "ds_dec_u32">;
451defm DS_MIN_RTN_I32   : DS_1A1D_RET_mc<"ds_min_rtn_i32", VGPR_32, "ds_min_i32">;
452defm DS_MAX_RTN_I32   : DS_1A1D_RET_mc<"ds_max_rtn_i32", VGPR_32, "ds_max_i32">;
453defm DS_MIN_RTN_U32   : DS_1A1D_RET_mc<"ds_min_rtn_u32", VGPR_32, "ds_min_u32">;
454defm DS_MAX_RTN_U32   : DS_1A1D_RET_mc<"ds_max_rtn_u32", VGPR_32, "ds_max_u32">;
455defm DS_AND_RTN_B32   : DS_1A1D_RET_mc<"ds_and_rtn_b32", VGPR_32, "ds_and_b32">;
456defm DS_OR_RTN_B32    : DS_1A1D_RET_mc<"ds_or_rtn_b32", VGPR_32, "ds_or_b32">;
457defm DS_XOR_RTN_B32   : DS_1A1D_RET_mc<"ds_xor_rtn_b32", VGPR_32, "ds_xor_b32">;
458defm DS_MSKOR_RTN_B32 : DS_1A2D_RET_mc<"ds_mskor_rtn_b32", VGPR_32, "ds_mskor_b32">;
459defm DS_CMPST_RTN_B32 : DS_1A2D_RET_mc<"ds_cmpst_rtn_b32", VGPR_32, "ds_cmpst_b32">;
460defm DS_CMPST_RTN_F32 : DS_1A2D_RET_mc<"ds_cmpst_rtn_f32", VGPR_32, "ds_cmpst_f32">;
461defm DS_MIN_RTN_F32   : DS_1A1D_RET_mc<"ds_min_rtn_f32", VGPR_32, "ds_min_f32">;
462defm DS_MAX_RTN_F32   : DS_1A1D_RET_mc<"ds_max_rtn_f32", VGPR_32, "ds_max_f32">;
463
464defm DS_WRXCHG_RTN_B32 : DS_1A1D_RET_mc<"ds_wrxchg_rtn_b32">;
465defm DS_WRXCHG2_RTN_B32 : DS_1A2D_Off8_RET_mc<"ds_wrxchg2_rtn_b32", VReg_64, VGPR_32>;
466defm DS_WRXCHG2ST64_RTN_B32 : DS_1A2D_Off8_RET_mc<"ds_wrxchg2st64_rtn_b32", VReg_64, VGPR_32>;
467
468defm DS_ADD_RTN_U64  : DS_1A1D_RET_mc<"ds_add_rtn_u64", VReg_64, "ds_add_u64">;
469defm DS_SUB_RTN_U64  : DS_1A1D_RET_mc<"ds_sub_rtn_u64", VReg_64, "ds_sub_u64">;
470defm DS_RSUB_RTN_U64  : DS_1A1D_RET_mc<"ds_rsub_rtn_u64", VReg_64, "ds_rsub_u64">;
471defm DS_INC_RTN_U64   : DS_1A1D_RET_mc<"ds_inc_rtn_u64", VReg_64, "ds_inc_u64">;
472defm DS_DEC_RTN_U64   : DS_1A1D_RET_mc<"ds_dec_rtn_u64", VReg_64, "ds_dec_u64">;
473defm DS_MIN_RTN_I64    : DS_1A1D_RET_mc<"ds_min_rtn_i64", VReg_64, "ds_min_i64">;
474defm DS_MAX_RTN_I64    : DS_1A1D_RET_mc<"ds_max_rtn_i64", VReg_64, "ds_max_i64">;
475defm DS_MIN_RTN_U64   : DS_1A1D_RET_mc<"ds_min_rtn_u64", VReg_64, "ds_min_u64">;
476defm DS_MAX_RTN_U64   : DS_1A1D_RET_mc<"ds_max_rtn_u64", VReg_64, "ds_max_u64">;
477defm DS_AND_RTN_B64    : DS_1A1D_RET_mc<"ds_and_rtn_b64", VReg_64, "ds_and_b64">;
478defm DS_OR_RTN_B64     : DS_1A1D_RET_mc<"ds_or_rtn_b64", VReg_64, "ds_or_b64">;
479defm DS_XOR_RTN_B64    : DS_1A1D_RET_mc<"ds_xor_rtn_b64", VReg_64, "ds_xor_b64">;
480defm DS_MSKOR_RTN_B64  : DS_1A2D_RET_mc<"ds_mskor_rtn_b64", VReg_64, "ds_mskor_b64">;
481defm DS_CMPST_RTN_B64  : DS_1A2D_RET_mc<"ds_cmpst_rtn_b64", VReg_64, "ds_cmpst_b64">;
482defm DS_CMPST_RTN_F64  : DS_1A2D_RET_mc<"ds_cmpst_rtn_f64", VReg_64, "ds_cmpst_f64">;
483defm DS_MIN_RTN_F64    : DS_1A1D_RET_mc<"ds_min_rtn_f64", VReg_64, "ds_min_f64">;
484defm DS_MAX_RTN_F64    : DS_1A1D_RET_mc<"ds_max_rtn_f64", VReg_64, "ds_max_f64">;
485
486defm DS_WRXCHG_RTN_B64 : DS_1A1D_RET_mc<"ds_wrxchg_rtn_b64", VReg_64>;
487defm DS_WRXCHG2_RTN_B64 : DS_1A2D_Off8_RET_mc<"ds_wrxchg2_rtn_b64", VReg_128, VReg_64>;
488defm DS_WRXCHG2ST64_RTN_B64 : DS_1A2D_Off8_RET_mc<"ds_wrxchg2st64_rtn_b64", VReg_128, VReg_64>;
489
490let isConvergent = 1, usesCustomInserter = 1 in {
491def DS_GWS_INIT       : DS_GWS_1D<"ds_gws_init"> {
492  let mayLoad = 0;
493}
494def DS_GWS_SEMA_V     : DS_GWS_0D<"ds_gws_sema_v">;
495def DS_GWS_SEMA_BR    : DS_GWS_1D<"ds_gws_sema_br">;
496def DS_GWS_SEMA_P     : DS_GWS_0D<"ds_gws_sema_p">;
497def DS_GWS_BARRIER    : DS_GWS_1D<"ds_gws_barrier">;
498}
499
500def DS_ADD_SRC2_U32   : DS_1A<"ds_add_src2_u32">;
501def DS_SUB_SRC2_U32   : DS_1A<"ds_sub_src2_u32">;
502def DS_RSUB_SRC2_U32  : DS_1A<"ds_rsub_src2_u32">;
503def DS_INC_SRC2_U32   : DS_1A<"ds_inc_src2_u32">;
504def DS_DEC_SRC2_U32   : DS_1A<"ds_dec_src2_u32">;
505def DS_MIN_SRC2_I32   : DS_1A<"ds_min_src2_i32">;
506def DS_MAX_SRC2_I32   : DS_1A<"ds_max_src2_i32">;
507def DS_MIN_SRC2_U32   : DS_1A<"ds_min_src2_u32">;
508def DS_MAX_SRC2_U32   : DS_1A<"ds_max_src2_u32">;
509def DS_AND_SRC2_B32   : DS_1A<"ds_and_src2_b32">;
510def DS_OR_SRC2_B32    : DS_1A<"ds_or_src2_b32">;
511def DS_XOR_SRC2_B32   : DS_1A<"ds_xor_src2_b32">;
512def DS_MIN_SRC2_F32   : DS_1A<"ds_min_src2_f32">;
513def DS_MAX_SRC2_F32   : DS_1A<"ds_max_src2_f32">;
514
515def DS_ADD_SRC2_U64   : DS_1A<"ds_add_src2_u64">;
516def DS_SUB_SRC2_U64   : DS_1A<"ds_sub_src2_u64">;
517def DS_RSUB_SRC2_U64  : DS_1A<"ds_rsub_src2_u64">;
518def DS_INC_SRC2_U64   : DS_1A<"ds_inc_src2_u64">;
519def DS_DEC_SRC2_U64   : DS_1A<"ds_dec_src2_u64">;
520def DS_MIN_SRC2_I64   : DS_1A<"ds_min_src2_i64">;
521def DS_MAX_SRC2_I64   : DS_1A<"ds_max_src2_i64">;
522def DS_MIN_SRC2_U64   : DS_1A<"ds_min_src2_u64">;
523def DS_MAX_SRC2_U64   : DS_1A<"ds_max_src2_u64">;
524def DS_AND_SRC2_B64   : DS_1A<"ds_and_src2_b64">;
525def DS_OR_SRC2_B64    : DS_1A<"ds_or_src2_b64">;
526def DS_XOR_SRC2_B64   : DS_1A<"ds_xor_src2_b64">;
527def DS_MIN_SRC2_F64   : DS_1A<"ds_min_src2_f64">;
528def DS_MAX_SRC2_F64   : DS_1A<"ds_max_src2_f64">;
529
530def DS_WRITE_SRC2_B32 : DS_1A<"ds_write_src2_b32">;
531def DS_WRITE_SRC2_B64 : DS_1A<"ds_write_src2_b64">;
532
533let Uses = [EXEC], mayLoad = 0, mayStore = 0, isConvergent = 1 in {
534def DS_SWIZZLE_B32 : DS_1A_RET <"ds_swizzle_b32", VGPR_32, 0, SwizzleImm>;
535}
536
537let mayStore = 0 in {
538defm DS_READ_I8      : DS_1A_RET_mc<"ds_read_i8">;
539defm DS_READ_U8      : DS_1A_RET_mc<"ds_read_u8">;
540defm DS_READ_I16     : DS_1A_RET_mc<"ds_read_i16">;
541defm DS_READ_U16     : DS_1A_RET_mc<"ds_read_u16">;
542defm DS_READ_B32     : DS_1A_RET_mc<"ds_read_b32">;
543defm DS_READ_B64     : DS_1A_RET_mc<"ds_read_b64", VReg_64>;
544
545defm DS_READ2_B32    : DS_1A_Off8_RET_mc<"ds_read2_b32", VReg_64>;
546defm DS_READ2ST64_B32: DS_1A_Off8_RET_mc<"ds_read2st64_b32", VReg_64>;
547
548defm DS_READ2_B64    : DS_1A_Off8_RET_mc<"ds_read2_b64", VReg_128>;
549defm DS_READ2ST64_B64: DS_1A_Off8_RET_mc<"ds_read2st64_b64", VReg_128>;
550
551let has_m0_read = 0 in {
552let SubtargetPredicate = HasD16LoadStore in {
553def DS_READ_U8_D16     : DS_1A_RET_Tied<"ds_read_u8_d16">;
554def DS_READ_U8_D16_HI  : DS_1A_RET_Tied<"ds_read_u8_d16_hi">;
555def DS_READ_I8_D16     : DS_1A_RET_Tied<"ds_read_i8_d16">;
556def DS_READ_I8_D16_HI  : DS_1A_RET_Tied<"ds_read_i8_d16_hi">;
557def DS_READ_U16_D16    : DS_1A_RET_Tied<"ds_read_u16_d16">;
558def DS_READ_U16_D16_HI : DS_1A_RET_Tied<"ds_read_u16_d16_hi">;
559}
560} // End has_m0_read = 0
561
562let SubtargetPredicate = HasDSAddTid in {
563def DS_READ_ADDTID_B32 : DS_0A_RET<"ds_read_addtid_b32">;
564}
565
566} // End mayStore = 0
567
568def DS_CONSUME       : DS_0A_RET<"ds_consume">;
569def DS_APPEND        : DS_0A_RET<"ds_append">;
570def DS_ORDERED_COUNT : DS_1A_RET_GDS<"ds_ordered_count">;
571
572//===----------------------------------------------------------------------===//
573// Instruction definitions for CI and newer.
574//===----------------------------------------------------------------------===//
575
576let SubtargetPredicate = isGFX7Plus in {
577
578defm DS_WRAP_RTN_B32 : DS_1A2D_RET_mc<"ds_wrap_rtn_b32", VGPR_32>;
579defm DS_CONDXCHG32_RTN_B64 : DS_1A1D_RET_mc<"ds_condxchg32_rtn_b64", VReg_64>;
580
581let isConvergent = 1, usesCustomInserter = 1 in {
582def DS_GWS_SEMA_RELEASE_ALL : DS_GWS_0D<"ds_gws_sema_release_all">;
583}
584
585let mayStore = 0 in {
586defm DS_READ_B96 : DS_1A_RET_mc<"ds_read_b96", VReg_96>;
587defm DS_READ_B128: DS_1A_RET_mc<"ds_read_b128", VReg_128>;
588} // End mayStore = 0
589
590let mayLoad = 0 in {
591defm DS_WRITE_B96 : DS_1A1D_NORET_mc<"ds_write_b96", VReg_96>;
592defm DS_WRITE_B128 : DS_1A1D_NORET_mc<"ds_write_b128", VReg_128>;
593} // End mayLoad = 0
594
595def DS_NOP : DS_VOID<"ds_nop">;
596
597} // let SubtargetPredicate = isGFX7Plus
598
599//===----------------------------------------------------------------------===//
600// Instruction definitions for VI and newer.
601//===----------------------------------------------------------------------===//
602
603let SubtargetPredicate = isGFX8Plus in {
604
605let Uses = [EXEC] in {
606def DS_PERMUTE_B32  : DS_1A1D_PERMUTE <"ds_permute_b32",
607                                       int_amdgcn_ds_permute>;
608def DS_BPERMUTE_B32 : DS_1A1D_PERMUTE <"ds_bpermute_b32",
609                                       int_amdgcn_ds_bpermute>;
610}
611
612def DS_ADD_SRC2_F32 : DS_1A<"ds_add_src2_f32">;
613
614} // let SubtargetPredicate = isGFX8Plus
615
616//===----------------------------------------------------------------------===//
617// DS Patterns
618//===----------------------------------------------------------------------===//
619
620def : GCNPat <
621  (int_amdgcn_ds_swizzle i32:$src, timm:$offset16),
622  (DS_SWIZZLE_B32 VGPR_32:$src, (as_i16timm $offset16), (i1 0))
623>;
624
625class DSReadPat <DS_Pseudo inst, ValueType vt, PatFrag frag, int gds=0> : GCNPat <
626  (vt (frag (DS1Addr1Offset i32:$ptr, i16:$offset))),
627  (inst $ptr, offset:$offset, (i1 gds))
628>;
629
630multiclass DSReadPat_mc<DS_Pseudo inst, ValueType vt, string frag> {
631
632  let OtherPredicates = [LDSRequiresM0Init] in {
633    def : DSReadPat<inst, vt, !cast<PatFrag>(frag#"_m0")>;
634  }
635
636  let OtherPredicates = [NotLDSRequiresM0Init] in {
637    def : DSReadPat<!cast<DS_Pseudo>(!cast<string>(inst)#"_gfx9"), vt, !cast<PatFrag>(frag)>;
638  }
639}
640
641class DSReadPat_D16 <DS_Pseudo inst, PatFrag frag, ValueType vt> : GCNPat <
642  (frag (DS1Addr1Offset i32:$ptr, i16:$offset), vt:$in),
643  (inst $ptr, offset:$offset, (i1 0), $in)
644>;
645
646defm : DSReadPat_mc <DS_READ_I8, i32, "sextloadi8_local">;
647defm : DSReadPat_mc <DS_READ_I8,  i16, "sextloadi8_local">;
648defm : DSReadPat_mc <DS_READ_U8,  i32, "extloadi8_local">;
649defm : DSReadPat_mc <DS_READ_U8,  i32, "zextloadi8_local">;
650defm : DSReadPat_mc <DS_READ_U8,  i16, "extloadi8_local">;
651defm : DSReadPat_mc <DS_READ_U8,  i16, "zextloadi8_local">;
652defm : DSReadPat_mc <DS_READ_I16, i32, "sextloadi16_local">;
653defm : DSReadPat_mc <DS_READ_I16, i32, "sextloadi16_local">;
654defm : DSReadPat_mc <DS_READ_U16, i32, "extloadi16_local">;
655defm : DSReadPat_mc <DS_READ_U16, i32, "zextloadi16_local">;
656defm : DSReadPat_mc <DS_READ_U16, i16, "load_local">;
657
658foreach vt = Reg32Types.types in {
659defm : DSReadPat_mc <DS_READ_B32, vt, "load_local">;
660}
661
662defm : DSReadPat_mc <DS_READ_B32, i32, "atomic_load_32_local">;
663defm : DSReadPat_mc <DS_READ_B64, i64, "atomic_load_64_local">;
664
665let AddedComplexity = 100 in {
666
667foreach vt = VReg_64.RegTypes in {
668defm : DSReadPat_mc <DS_READ_B64, vt, "load_align8_local">;
669}
670
671defm : DSReadPat_mc <DS_READ_B128, v4i32, "load_align16_local">;
672
673} // End AddedComplexity = 100
674
675let OtherPredicates = [D16PreservesUnusedBits] in {
676def : DSReadPat_D16<DS_READ_U16_D16_HI, load_d16_hi_local, v2i16>;
677def : DSReadPat_D16<DS_READ_U16_D16_HI, load_d16_hi_local, v2f16>;
678def : DSReadPat_D16<DS_READ_U8_D16_HI, az_extloadi8_d16_hi_local, v2i16>;
679def : DSReadPat_D16<DS_READ_U8_D16_HI, az_extloadi8_d16_hi_local, v2f16>;
680def : DSReadPat_D16<DS_READ_I8_D16_HI, sextloadi8_d16_hi_local, v2i16>;
681def : DSReadPat_D16<DS_READ_I8_D16_HI, sextloadi8_d16_hi_local, v2f16>;
682
683def : DSReadPat_D16<DS_READ_U16_D16, load_d16_lo_local, v2i16>;
684def : DSReadPat_D16<DS_READ_U16_D16, load_d16_lo_local, v2f16>;
685def : DSReadPat_D16<DS_READ_U8_D16, az_extloadi8_d16_lo_local, v2i16>;
686def : DSReadPat_D16<DS_READ_U8_D16, az_extloadi8_d16_lo_local, v2f16>;
687def : DSReadPat_D16<DS_READ_I8_D16, sextloadi8_d16_lo_local, v2i16>;
688def : DSReadPat_D16<DS_READ_I8_D16, sextloadi8_d16_lo_local, v2f16>;
689}
690
691class DSWritePat <DS_Pseudo inst, ValueType vt, PatFrag frag, int gds=0> : GCNPat <
692  (frag vt:$value, (DS1Addr1Offset i32:$ptr, i16:$offset)),
693  (inst $ptr, getVregSrcForVT<vt>.ret:$value, offset:$offset, (i1 gds))
694>;
695
696multiclass DSWritePat_mc <DS_Pseudo inst, ValueType vt, string frag> {
697  let OtherPredicates = [LDSRequiresM0Init] in {
698    def : DSWritePat<inst, vt, !cast<PatFrag>(frag#"_m0")>;
699  }
700
701  let OtherPredicates = [NotLDSRequiresM0Init] in {
702    def : DSWritePat<!cast<DS_Pseudo>(!cast<string>(inst)#"_gfx9"), vt, !cast<PatFrag>(frag)>;
703  }
704}
705
706// Irritatingly, atomic_store reverses the order of operands from a
707// normal store.
708class DSAtomicWritePat <DS_Pseudo inst, ValueType vt, PatFrag frag> : GCNPat <
709  (frag (DS1Addr1Offset i32:$ptr, i16:$offset), vt:$value),
710  (inst $ptr, $value, offset:$offset, (i1 0))
711>;
712
713multiclass DSAtomicWritePat_mc <DS_Pseudo inst, ValueType vt, string frag> {
714  let OtherPredicates = [LDSRequiresM0Init] in {
715    def : DSAtomicWritePat<inst, vt, !cast<PatFrag>(frag#"_m0")>;
716  }
717
718  let OtherPredicates = [NotLDSRequiresM0Init] in {
719    def : DSAtomicWritePat<!cast<DS_Pseudo>(!cast<string>(inst)#"_gfx9"), vt, !cast<PatFrag>(frag)>;
720  }
721}
722
723defm : DSWritePat_mc <DS_WRITE_B8, i32, "truncstorei8_local">;
724defm : DSWritePat_mc <DS_WRITE_B16, i32, "truncstorei16_local">;
725defm : DSWritePat_mc <DS_WRITE_B8, i16, "truncstorei8_local">;
726defm : DSWritePat_mc <DS_WRITE_B16, i16, "store_local">;
727
728foreach vt = VGPR_32.RegTypes in {
729defm : DSWritePat_mc <DS_WRITE_B32, vt, "store_local">;
730}
731
732defm : DSAtomicWritePat_mc <DS_WRITE_B32, i32, "atomic_store_local_32">;
733defm : DSAtomicWritePat_mc <DS_WRITE_B64, i64, "atomic_store_local_64">;
734
735let OtherPredicates = [D16PreservesUnusedBits] in {
736def : DSWritePat <DS_WRITE_B16_D16_HI, i32, store_hi16_local>;
737def : DSWritePat <DS_WRITE_B8_D16_HI, i32, truncstorei8_hi16_local>;
738}
739
740class DS64Bit4ByteAlignedReadPat<DS_Pseudo inst, ValueType vt, PatFrag frag> : GCNPat <
741  (vt:$value (frag (DS64Bit4ByteAligned i32:$ptr, i8:$offset0, i8:$offset1))),
742  (inst $ptr, $offset0, $offset1, (i1 0))
743>;
744
745class DS64Bit4ByteAlignedWritePat<DS_Pseudo inst, ValueType vt, PatFrag frag> : GCNPat<
746  (frag vt:$value, (DS64Bit4ByteAligned i32:$ptr, i8:$offset0, i8:$offset1)),
747  (inst $ptr, (i32 (EXTRACT_SUBREG VReg_64:$value, sub0)),
748              (i32 (EXTRACT_SUBREG VReg_64:$value, sub1)), $offset0, $offset1,
749              (i1 0))
750>;
751
752multiclass DS64Bit4ByteAlignedPat_mc<ValueType vt> {
753  let OtherPredicates = [LDSRequiresM0Init, isGFX7Plus] in {
754    def : DS64Bit4ByteAlignedReadPat<DS_READ2_B32, vt, load_local_m0>;
755    def : DS64Bit4ByteAlignedWritePat<DS_WRITE2_B32, vt, store_local_m0>;
756  }
757
758  let OtherPredicates = [NotLDSRequiresM0Init] in {
759    def : DS64Bit4ByteAlignedReadPat<DS_READ2_B32_gfx9, vt, load_local>;
760    def : DS64Bit4ByteAlignedWritePat<DS_WRITE2_B32_gfx9, vt, store_local>;
761  }
762}
763
764// v2i32 loads are split into i32 loads on SI during lowering, due to a bug
765// related to bounds checking.
766foreach vt = VReg_64.RegTypes in {
767defm : DS64Bit4ByteAlignedPat_mc<vt>;
768}
769
770let AddedComplexity = 100 in {
771
772foreach vt = VReg_64.RegTypes in {
773defm : DSWritePat_mc <DS_WRITE_B64, vt, "store_align8_local">;
774}
775
776defm : DSWritePat_mc <DS_WRITE_B128, v4i32, "store_align16_local">;
777
778} // End AddedComplexity = 100
779class DSAtomicRetPat<DS_Pseudo inst, ValueType vt, PatFrag frag, bit gds=0> : GCNPat <
780  (frag (DS1Addr1Offset i32:$ptr, i16:$offset), vt:$value),
781  (inst $ptr, getVregSrcForVT<vt>.ret:$value, offset:$offset, (i1 gds))
782>;
783
784multiclass DSAtomicRetPat_mc<DS_Pseudo inst, ValueType vt, string frag> {
785  let OtherPredicates = [LDSRequiresM0Init] in {
786    def : DSAtomicRetPat<inst, vt, !cast<PatFrag>(frag#"_local_m0_"#vt.Size)>;
787  }
788
789  let OtherPredicates = [NotLDSRequiresM0Init] in {
790    def : DSAtomicRetPat<!cast<DS_Pseudo>(!cast<string>(inst)#"_gfx9"), vt,
791                         !cast<PatFrag>(frag#"_local_"#vt.Size)>;
792  }
793
794  def : DSAtomicRetPat<inst, vt, !cast<PatFrag>(frag#"_region_m0_"#vt.Size), 1>;
795}
796
797
798
799class DSAtomicCmpXChg<DS_Pseudo inst, ValueType vt, PatFrag frag, bit gds=0> : GCNPat <
800  (frag (DS1Addr1Offset i32:$ptr, i16:$offset), vt:$cmp, vt:$swap),
801  (inst $ptr, getVregSrcForVT<vt>.ret:$cmp, getVregSrcForVT<vt>.ret:$swap, offset:$offset, (i1 gds))
802>;
803
804multiclass DSAtomicCmpXChg_mc<DS_Pseudo inst, ValueType vt, string frag> {
805  let OtherPredicates = [LDSRequiresM0Init] in {
806    def : DSAtomicCmpXChg<inst, vt, !cast<PatFrag>(frag#"_local_m0_"#vt.Size)>;
807  }
808
809  let OtherPredicates = [NotLDSRequiresM0Init] in {
810    def : DSAtomicCmpXChg<!cast<DS_Pseudo>(!cast<string>(inst)#"_gfx9"), vt,
811                          !cast<PatFrag>(frag#"_local_"#vt.Size)>;
812  }
813
814  def : DSAtomicCmpXChg<inst, vt, !cast<PatFrag>(frag#"_region_m0_"#vt.Size), 1>;
815}
816
817
818
819// 32-bit atomics.
820defm : DSAtomicRetPat_mc<DS_WRXCHG_RTN_B32, i32, "atomic_swap">;
821defm : DSAtomicRetPat_mc<DS_ADD_RTN_U32, i32, "atomic_load_add">;
822defm : DSAtomicRetPat_mc<DS_SUB_RTN_U32, i32, "atomic_load_sub">;
823defm : DSAtomicRetPat_mc<DS_INC_RTN_U32, i32, "atomic_inc">;
824defm : DSAtomicRetPat_mc<DS_DEC_RTN_U32, i32, "atomic_dec">;
825defm : DSAtomicRetPat_mc<DS_AND_RTN_B32, i32, "atomic_load_and">;
826defm : DSAtomicRetPat_mc<DS_OR_RTN_B32, i32, "atomic_load_or">;
827defm : DSAtomicRetPat_mc<DS_XOR_RTN_B32, i32, "atomic_load_xor">;
828defm : DSAtomicRetPat_mc<DS_MIN_RTN_I32, i32, "atomic_load_min">;
829defm : DSAtomicRetPat_mc<DS_MAX_RTN_I32, i32, "atomic_load_max">;
830defm : DSAtomicRetPat_mc<DS_MIN_RTN_U32, i32, "atomic_load_umin">;
831defm : DSAtomicRetPat_mc<DS_MAX_RTN_U32, i32, "atomic_load_umax">;
832defm : DSAtomicCmpXChg_mc<DS_CMPST_RTN_B32, i32, "atomic_cmp_swap">;
833defm : DSAtomicRetPat_mc<DS_MIN_RTN_F32, f32, "atomic_load_fmin">;
834defm : DSAtomicRetPat_mc<DS_MAX_RTN_F32, f32, "atomic_load_fmax">;
835defm : DSAtomicRetPat_mc<DS_ADD_RTN_F32, f32, "atomic_load_fadd">;
836
837// 64-bit atomics.
838defm : DSAtomicRetPat_mc<DS_WRXCHG_RTN_B64, i64, "atomic_swap">;
839defm : DSAtomicRetPat_mc<DS_ADD_RTN_U64, i64, "atomic_load_add">;
840defm : DSAtomicRetPat_mc<DS_SUB_RTN_U64, i64, "atomic_load_sub">;
841defm : DSAtomicRetPat_mc<DS_INC_RTN_U64, i64, "atomic_inc">;
842defm : DSAtomicRetPat_mc<DS_DEC_RTN_U64, i64, "atomic_dec">;
843defm : DSAtomicRetPat_mc<DS_AND_RTN_B64, i64, "atomic_load_and">;
844defm : DSAtomicRetPat_mc<DS_OR_RTN_B64, i64, "atomic_load_or">;
845defm : DSAtomicRetPat_mc<DS_XOR_RTN_B64, i64, "atomic_load_xor">;
846defm : DSAtomicRetPat_mc<DS_MIN_RTN_I64, i64, "atomic_load_min">;
847defm : DSAtomicRetPat_mc<DS_MAX_RTN_I64, i64, "atomic_load_max">;
848defm : DSAtomicRetPat_mc<DS_MIN_RTN_U64, i64, "atomic_load_umin">;
849defm : DSAtomicRetPat_mc<DS_MAX_RTN_U64, i64, "atomic_load_umax">;
850
851defm : DSAtomicCmpXChg_mc<DS_CMPST_RTN_B64, i64, "atomic_cmp_swap">;
852
853def : Pat <
854  (SIds_ordered_count i32:$value, i16:$offset),
855  (DS_ORDERED_COUNT $value, (as_i16imm $offset))
856>;
857
858//===----------------------------------------------------------------------===//
859// Target-specific instruction encodings.
860//===----------------------------------------------------------------------===//
861
862//===----------------------------------------------------------------------===//
863// Base ENC_DS for GFX6, GFX7, GFX10.
864//===----------------------------------------------------------------------===//
865
866class Base_DS_Real_gfx6_gfx7_gfx10<bits<8> op, DS_Pseudo ps, int ef> :
867    DS_Real<ps>, SIMCInstr <ps.Mnemonic, ef> {
868
869  let Inst{7-0}   = !if(ps.has_offset0, offset0, 0);
870  let Inst{15-8}  = !if(ps.has_offset1, offset1, 0);
871  let Inst{17}    = !if(ps.has_gds, gds, ps.gdsValue);
872  let Inst{25-18} = op;
873  let Inst{31-26} = 0x36;
874  let Inst{39-32} = !if(ps.has_addr, addr, !if(ps.has_gws_data0, data0, 0));
875  let Inst{47-40} = !if(ps.has_data0, data0, 0);
876  let Inst{55-48} = !if(ps.has_data1, data1, 0);
877  let Inst{63-56} = !if(ps.has_vdst, vdst, 0);
878}
879
880//===----------------------------------------------------------------------===//
881// GFX10.
882//===----------------------------------------------------------------------===//
883
884let AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10" in {
885  multiclass DS_Real_gfx10<bits<8> op>  {
886    def _gfx10 : Base_DS_Real_gfx6_gfx7_gfx10<op, !cast<DS_Pseudo>(NAME),
887                                              SIEncodingFamily.GFX10>;
888  }
889} // End AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10"
890
891defm DS_ADD_F32          : DS_Real_gfx10<0x015>;
892defm DS_ADD_RTN_F32      : DS_Real_gfx10<0x055>;
893defm DS_ADD_SRC2_F32     : DS_Real_gfx10<0x095>;
894defm DS_WRITE_B8_D16_HI  : DS_Real_gfx10<0x0a0>;
895defm DS_WRITE_B16_D16_HI : DS_Real_gfx10<0x0a1>;
896defm DS_READ_U8_D16      : DS_Real_gfx10<0x0a2>;
897defm DS_READ_U8_D16_HI   : DS_Real_gfx10<0x0a3>;
898defm DS_READ_I8_D16      : DS_Real_gfx10<0x0a4>;
899defm DS_READ_I8_D16_HI   : DS_Real_gfx10<0x0a5>;
900defm DS_READ_U16_D16     : DS_Real_gfx10<0x0a6>;
901defm DS_READ_U16_D16_HI  : DS_Real_gfx10<0x0a7>;
902defm DS_WRITE_ADDTID_B32 : DS_Real_gfx10<0x0b0>;
903defm DS_READ_ADDTID_B32  : DS_Real_gfx10<0x0b1>;
904defm DS_PERMUTE_B32      : DS_Real_gfx10<0x0b2>;
905defm DS_BPERMUTE_B32     : DS_Real_gfx10<0x0b3>;
906
907//===----------------------------------------------------------------------===//
908// GFX7, GFX10.
909//===----------------------------------------------------------------------===//
910
911let AssemblerPredicate = isGFX7Only, DecoderNamespace = "GFX7" in {
912  multiclass DS_Real_gfx7<bits<8> op> {
913    def _gfx7 : Base_DS_Real_gfx6_gfx7_gfx10<op, !cast<DS_Pseudo>(NAME),
914                                             SIEncodingFamily.SI>;
915  }
916} // End AssemblerPredicate = isGFX7Only, DecoderNamespace = "GFX7"
917
918multiclass DS_Real_gfx7_gfx10<bits<8> op> :
919  DS_Real_gfx7<op>, DS_Real_gfx10<op>;
920
921// FIXME-GFX7: Add tests when upstreaming this part.
922defm DS_GWS_SEMA_RELEASE_ALL : DS_Real_gfx7_gfx10<0x018>;
923defm DS_WRAP_RTN_B32         : DS_Real_gfx7_gfx10<0x034>;
924defm DS_CONDXCHG32_RTN_B64   : DS_Real_gfx7_gfx10<0x07e>;
925defm DS_WRITE_B96            : DS_Real_gfx7_gfx10<0x0de>;
926defm DS_WRITE_B128           : DS_Real_gfx7_gfx10<0x0df>;
927defm DS_READ_B96             : DS_Real_gfx7_gfx10<0x0fe>;
928defm DS_READ_B128            : DS_Real_gfx7_gfx10<0x0ff>;
929
930//===----------------------------------------------------------------------===//
931// GFX6, GFX7, GFX10.
932//===----------------------------------------------------------------------===//
933
934let AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" in {
935  multiclass DS_Real_gfx6_gfx7<bits<8> op> {
936    def _gfx6_gfx7 : Base_DS_Real_gfx6_gfx7_gfx10<op, !cast<DS_Pseudo>(NAME),
937                                                  SIEncodingFamily.SI>;
938  }
939} // End AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7"
940
941multiclass DS_Real_gfx6_gfx7_gfx10<bits<8> op> :
942  DS_Real_gfx6_gfx7<op>, DS_Real_gfx10<op>;
943
944defm DS_ADD_U32             : DS_Real_gfx6_gfx7_gfx10<0x000>;
945defm DS_SUB_U32             : DS_Real_gfx6_gfx7_gfx10<0x001>;
946defm DS_RSUB_U32            : DS_Real_gfx6_gfx7_gfx10<0x002>;
947defm DS_INC_U32             : DS_Real_gfx6_gfx7_gfx10<0x003>;
948defm DS_DEC_U32             : DS_Real_gfx6_gfx7_gfx10<0x004>;
949defm DS_MIN_I32             : DS_Real_gfx6_gfx7_gfx10<0x005>;
950defm DS_MAX_I32             : DS_Real_gfx6_gfx7_gfx10<0x006>;
951defm DS_MIN_U32             : DS_Real_gfx6_gfx7_gfx10<0x007>;
952defm DS_MAX_U32             : DS_Real_gfx6_gfx7_gfx10<0x008>;
953defm DS_AND_B32             : DS_Real_gfx6_gfx7_gfx10<0x009>;
954defm DS_OR_B32              : DS_Real_gfx6_gfx7_gfx10<0x00a>;
955defm DS_XOR_B32             : DS_Real_gfx6_gfx7_gfx10<0x00b>;
956defm DS_MSKOR_B32           : DS_Real_gfx6_gfx7_gfx10<0x00c>;
957defm DS_WRITE_B32           : DS_Real_gfx6_gfx7_gfx10<0x00d>;
958defm DS_WRITE2_B32          : DS_Real_gfx6_gfx7_gfx10<0x00e>;
959defm DS_WRITE2ST64_B32      : DS_Real_gfx6_gfx7_gfx10<0x00f>;
960defm DS_CMPST_B32           : DS_Real_gfx6_gfx7_gfx10<0x010>;
961defm DS_CMPST_F32           : DS_Real_gfx6_gfx7_gfx10<0x011>;
962defm DS_MIN_F32             : DS_Real_gfx6_gfx7_gfx10<0x012>;
963defm DS_MAX_F32             : DS_Real_gfx6_gfx7_gfx10<0x013>;
964defm DS_NOP                 : DS_Real_gfx6_gfx7_gfx10<0x014>;
965defm DS_GWS_INIT            : DS_Real_gfx6_gfx7_gfx10<0x019>;
966defm DS_GWS_SEMA_V          : DS_Real_gfx6_gfx7_gfx10<0x01a>;
967defm DS_GWS_SEMA_BR         : DS_Real_gfx6_gfx7_gfx10<0x01b>;
968defm DS_GWS_SEMA_P          : DS_Real_gfx6_gfx7_gfx10<0x01c>;
969defm DS_GWS_BARRIER         : DS_Real_gfx6_gfx7_gfx10<0x01d>;
970defm DS_WRITE_B8            : DS_Real_gfx6_gfx7_gfx10<0x01e>;
971defm DS_WRITE_B16           : DS_Real_gfx6_gfx7_gfx10<0x01f>;
972defm DS_ADD_RTN_U32         : DS_Real_gfx6_gfx7_gfx10<0x020>;
973defm DS_SUB_RTN_U32         : DS_Real_gfx6_gfx7_gfx10<0x021>;
974defm DS_RSUB_RTN_U32        : DS_Real_gfx6_gfx7_gfx10<0x022>;
975defm DS_INC_RTN_U32         : DS_Real_gfx6_gfx7_gfx10<0x023>;
976defm DS_DEC_RTN_U32         : DS_Real_gfx6_gfx7_gfx10<0x024>;
977defm DS_MIN_RTN_I32         : DS_Real_gfx6_gfx7_gfx10<0x025>;
978defm DS_MAX_RTN_I32         : DS_Real_gfx6_gfx7_gfx10<0x026>;
979defm DS_MIN_RTN_U32         : DS_Real_gfx6_gfx7_gfx10<0x027>;
980defm DS_MAX_RTN_U32         : DS_Real_gfx6_gfx7_gfx10<0x028>;
981defm DS_AND_RTN_B32         : DS_Real_gfx6_gfx7_gfx10<0x029>;
982defm DS_OR_RTN_B32          : DS_Real_gfx6_gfx7_gfx10<0x02a>;
983defm DS_XOR_RTN_B32         : DS_Real_gfx6_gfx7_gfx10<0x02b>;
984defm DS_MSKOR_RTN_B32       : DS_Real_gfx6_gfx7_gfx10<0x02c>;
985defm DS_WRXCHG_RTN_B32      : DS_Real_gfx6_gfx7_gfx10<0x02d>;
986defm DS_WRXCHG2_RTN_B32     : DS_Real_gfx6_gfx7_gfx10<0x02e>;
987defm DS_WRXCHG2ST64_RTN_B32 : DS_Real_gfx6_gfx7_gfx10<0x02f>;
988defm DS_CMPST_RTN_B32       : DS_Real_gfx6_gfx7_gfx10<0x030>;
989defm DS_CMPST_RTN_F32       : DS_Real_gfx6_gfx7_gfx10<0x031>;
990defm DS_MIN_RTN_F32         : DS_Real_gfx6_gfx7_gfx10<0x032>;
991defm DS_MAX_RTN_F32         : DS_Real_gfx6_gfx7_gfx10<0x033>;
992defm DS_SWIZZLE_B32         : DS_Real_gfx6_gfx7_gfx10<0x035>;
993defm DS_READ_B32            : DS_Real_gfx6_gfx7_gfx10<0x036>;
994defm DS_READ2_B32           : DS_Real_gfx6_gfx7_gfx10<0x037>;
995defm DS_READ2ST64_B32       : DS_Real_gfx6_gfx7_gfx10<0x038>;
996defm DS_READ_I8             : DS_Real_gfx6_gfx7_gfx10<0x039>;
997defm DS_READ_U8             : DS_Real_gfx6_gfx7_gfx10<0x03a>;
998defm DS_READ_I16            : DS_Real_gfx6_gfx7_gfx10<0x03b>;
999defm DS_READ_U16            : DS_Real_gfx6_gfx7_gfx10<0x03c>;
1000defm DS_CONSUME             : DS_Real_gfx6_gfx7_gfx10<0x03d>;
1001defm DS_APPEND              : DS_Real_gfx6_gfx7_gfx10<0x03e>;
1002defm DS_ORDERED_COUNT       : DS_Real_gfx6_gfx7_gfx10<0x03f>;
1003defm DS_ADD_U64             : DS_Real_gfx6_gfx7_gfx10<0x040>;
1004defm DS_SUB_U64             : DS_Real_gfx6_gfx7_gfx10<0x041>;
1005defm DS_RSUB_U64            : DS_Real_gfx6_gfx7_gfx10<0x042>;
1006defm DS_INC_U64             : DS_Real_gfx6_gfx7_gfx10<0x043>;
1007defm DS_DEC_U64             : DS_Real_gfx6_gfx7_gfx10<0x044>;
1008defm DS_MIN_I64             : DS_Real_gfx6_gfx7_gfx10<0x045>;
1009defm DS_MAX_I64             : DS_Real_gfx6_gfx7_gfx10<0x046>;
1010defm DS_MIN_U64             : DS_Real_gfx6_gfx7_gfx10<0x047>;
1011defm DS_MAX_U64             : DS_Real_gfx6_gfx7_gfx10<0x048>;
1012defm DS_AND_B64             : DS_Real_gfx6_gfx7_gfx10<0x049>;
1013defm DS_OR_B64              : DS_Real_gfx6_gfx7_gfx10<0x04a>;
1014defm DS_XOR_B64             : DS_Real_gfx6_gfx7_gfx10<0x04b>;
1015defm DS_MSKOR_B64           : DS_Real_gfx6_gfx7_gfx10<0x04c>;
1016defm DS_WRITE_B64           : DS_Real_gfx6_gfx7_gfx10<0x04d>;
1017defm DS_WRITE2_B64          : DS_Real_gfx6_gfx7_gfx10<0x04e>;
1018defm DS_WRITE2ST64_B64      : DS_Real_gfx6_gfx7_gfx10<0x04f>;
1019defm DS_CMPST_B64           : DS_Real_gfx6_gfx7_gfx10<0x050>;
1020defm DS_CMPST_F64           : DS_Real_gfx6_gfx7_gfx10<0x051>;
1021defm DS_MIN_F64             : DS_Real_gfx6_gfx7_gfx10<0x052>;
1022defm DS_MAX_F64             : DS_Real_gfx6_gfx7_gfx10<0x053>;
1023defm DS_ADD_RTN_U64         : DS_Real_gfx6_gfx7_gfx10<0x060>;
1024defm DS_SUB_RTN_U64         : DS_Real_gfx6_gfx7_gfx10<0x061>;
1025defm DS_RSUB_RTN_U64        : DS_Real_gfx6_gfx7_gfx10<0x062>;
1026defm DS_INC_RTN_U64         : DS_Real_gfx6_gfx7_gfx10<0x063>;
1027defm DS_DEC_RTN_U64         : DS_Real_gfx6_gfx7_gfx10<0x064>;
1028defm DS_MIN_RTN_I64         : DS_Real_gfx6_gfx7_gfx10<0x065>;
1029defm DS_MAX_RTN_I64         : DS_Real_gfx6_gfx7_gfx10<0x066>;
1030defm DS_MIN_RTN_U64         : DS_Real_gfx6_gfx7_gfx10<0x067>;
1031defm DS_MAX_RTN_U64         : DS_Real_gfx6_gfx7_gfx10<0x068>;
1032defm DS_AND_RTN_B64         : DS_Real_gfx6_gfx7_gfx10<0x069>;
1033defm DS_OR_RTN_B64          : DS_Real_gfx6_gfx7_gfx10<0x06a>;
1034defm DS_XOR_RTN_B64         : DS_Real_gfx6_gfx7_gfx10<0x06b>;
1035defm DS_MSKOR_RTN_B64       : DS_Real_gfx6_gfx7_gfx10<0x06c>;
1036defm DS_WRXCHG_RTN_B64      : DS_Real_gfx6_gfx7_gfx10<0x06d>;
1037defm DS_WRXCHG2_RTN_B64     : DS_Real_gfx6_gfx7_gfx10<0x06e>;
1038defm DS_WRXCHG2ST64_RTN_B64 : DS_Real_gfx6_gfx7_gfx10<0x06f>;
1039defm DS_CMPST_RTN_B64       : DS_Real_gfx6_gfx7_gfx10<0x070>;
1040defm DS_CMPST_RTN_F64       : DS_Real_gfx6_gfx7_gfx10<0x071>;
1041defm DS_MIN_RTN_F64         : DS_Real_gfx6_gfx7_gfx10<0x072>;
1042defm DS_MAX_RTN_F64         : DS_Real_gfx6_gfx7_gfx10<0x073>;
1043defm DS_READ_B64            : DS_Real_gfx6_gfx7_gfx10<0x076>;
1044defm DS_READ2_B64           : DS_Real_gfx6_gfx7_gfx10<0x077>;
1045defm DS_READ2ST64_B64       : DS_Real_gfx6_gfx7_gfx10<0x078>;
1046defm DS_ADD_SRC2_U32        : DS_Real_gfx6_gfx7_gfx10<0x080>;
1047defm DS_SUB_SRC2_U32        : DS_Real_gfx6_gfx7_gfx10<0x081>;
1048defm DS_RSUB_SRC2_U32       : DS_Real_gfx6_gfx7_gfx10<0x082>;
1049defm DS_INC_SRC2_U32        : DS_Real_gfx6_gfx7_gfx10<0x083>;
1050defm DS_DEC_SRC2_U32        : DS_Real_gfx6_gfx7_gfx10<0x084>;
1051defm DS_MIN_SRC2_I32        : DS_Real_gfx6_gfx7_gfx10<0x085>;
1052defm DS_MAX_SRC2_I32        : DS_Real_gfx6_gfx7_gfx10<0x086>;
1053defm DS_MIN_SRC2_U32        : DS_Real_gfx6_gfx7_gfx10<0x087>;
1054defm DS_MAX_SRC2_U32        : DS_Real_gfx6_gfx7_gfx10<0x088>;
1055defm DS_AND_SRC2_B32        : DS_Real_gfx6_gfx7_gfx10<0x089>;
1056defm DS_OR_SRC2_B32         : DS_Real_gfx6_gfx7_gfx10<0x08a>;
1057defm DS_XOR_SRC2_B32        : DS_Real_gfx6_gfx7_gfx10<0x08b>;
1058defm DS_WRITE_SRC2_B32      : DS_Real_gfx6_gfx7_gfx10<0x08d>;
1059defm DS_MIN_SRC2_F32        : DS_Real_gfx6_gfx7_gfx10<0x092>;
1060defm DS_MAX_SRC2_F32        : DS_Real_gfx6_gfx7_gfx10<0x093>;
1061defm DS_ADD_SRC2_U64        : DS_Real_gfx6_gfx7_gfx10<0x0c0>;
1062defm DS_SUB_SRC2_U64        : DS_Real_gfx6_gfx7_gfx10<0x0c1>;
1063defm DS_RSUB_SRC2_U64       : DS_Real_gfx6_gfx7_gfx10<0x0c2>;
1064defm DS_INC_SRC2_U64        : DS_Real_gfx6_gfx7_gfx10<0x0c3>;
1065defm DS_DEC_SRC2_U64        : DS_Real_gfx6_gfx7_gfx10<0x0c4>;
1066defm DS_MIN_SRC2_I64        : DS_Real_gfx6_gfx7_gfx10<0x0c5>;
1067defm DS_MAX_SRC2_I64        : DS_Real_gfx6_gfx7_gfx10<0x0c6>;
1068defm DS_MIN_SRC2_U64        : DS_Real_gfx6_gfx7_gfx10<0x0c7>;
1069defm DS_MAX_SRC2_U64        : DS_Real_gfx6_gfx7_gfx10<0x0c8>;
1070defm DS_AND_SRC2_B64        : DS_Real_gfx6_gfx7_gfx10<0x0c9>;
1071defm DS_OR_SRC2_B64         : DS_Real_gfx6_gfx7_gfx10<0x0ca>;
1072defm DS_XOR_SRC2_B64        : DS_Real_gfx6_gfx7_gfx10<0x0cb>;
1073defm DS_WRITE_SRC2_B64      : DS_Real_gfx6_gfx7_gfx10<0x0cd>;
1074defm DS_MIN_SRC2_F64        : DS_Real_gfx6_gfx7_gfx10<0x0d2>;
1075defm DS_MAX_SRC2_F64        : DS_Real_gfx6_gfx7_gfx10<0x0d3>;
1076
1077//===----------------------------------------------------------------------===//
1078// GFX8, GFX9 (VI).
1079//===----------------------------------------------------------------------===//
1080
1081class DS_Real_vi <bits<8> op, DS_Pseudo ds> :
1082  DS_Real <ds>,
1083  SIMCInstr <ds.Mnemonic, SIEncodingFamily.VI> {
1084  let AssemblerPredicate = isGFX8GFX9;
1085  let DecoderNamespace = "GFX8";
1086
1087  // encoding
1088  let Inst{7-0}   = !if(ds.has_offset0, offset0, 0);
1089  let Inst{15-8}  = !if(ds.has_offset1, offset1, 0);
1090  let Inst{16}    = !if(ds.has_gds, gds, ds.gdsValue);
1091  let Inst{24-17} = op;
1092  let Inst{31-26} = 0x36; // ds prefix
1093  let Inst{39-32} = !if(ds.has_addr, addr, !if(ds.has_gws_data0, data0, 0));
1094  let Inst{47-40} = !if(ds.has_data0, data0, 0);
1095  let Inst{55-48} = !if(ds.has_data1, data1, 0);
1096  let Inst{63-56} = !if(ds.has_vdst, vdst, 0);
1097}
1098
1099def DS_ADD_U32_vi         : DS_Real_vi<0x0,  DS_ADD_U32>;
1100def DS_SUB_U32_vi         : DS_Real_vi<0x1,  DS_SUB_U32>;
1101def DS_RSUB_U32_vi        : DS_Real_vi<0x2,  DS_RSUB_U32>;
1102def DS_INC_U32_vi         : DS_Real_vi<0x3,  DS_INC_U32>;
1103def DS_DEC_U32_vi         : DS_Real_vi<0x4,  DS_DEC_U32>;
1104def DS_MIN_I32_vi         : DS_Real_vi<0x5,  DS_MIN_I32>;
1105def DS_MAX_I32_vi         : DS_Real_vi<0x6,  DS_MAX_I32>;
1106def DS_MIN_U32_vi         : DS_Real_vi<0x7,  DS_MIN_U32>;
1107def DS_MAX_U32_vi         : DS_Real_vi<0x8,  DS_MAX_U32>;
1108def DS_AND_B32_vi         : DS_Real_vi<0x9,  DS_AND_B32>;
1109def DS_OR_B32_vi          : DS_Real_vi<0xa,  DS_OR_B32>;
1110def DS_XOR_B32_vi         : DS_Real_vi<0xb,  DS_XOR_B32>;
1111def DS_MSKOR_B32_vi       : DS_Real_vi<0xc,  DS_MSKOR_B32>;
1112def DS_WRITE_B32_vi       : DS_Real_vi<0xd,  DS_WRITE_B32>;
1113def DS_WRITE2_B32_vi      : DS_Real_vi<0xe,  DS_WRITE2_B32>;
1114def DS_WRITE2ST64_B32_vi  : DS_Real_vi<0xf,  DS_WRITE2ST64_B32>;
1115def DS_CMPST_B32_vi       : DS_Real_vi<0x10, DS_CMPST_B32>;
1116def DS_CMPST_F32_vi       : DS_Real_vi<0x11, DS_CMPST_F32>;
1117def DS_MIN_F32_vi         : DS_Real_vi<0x12, DS_MIN_F32>;
1118def DS_MAX_F32_vi         : DS_Real_vi<0x13, DS_MAX_F32>;
1119def DS_NOP_vi             : DS_Real_vi<0x14, DS_NOP>;
1120def DS_ADD_F32_vi         : DS_Real_vi<0x15, DS_ADD_F32>;
1121def DS_GWS_INIT_vi        : DS_Real_vi<0x99, DS_GWS_INIT>;
1122def DS_GWS_SEMA_V_vi      : DS_Real_vi<0x9a, DS_GWS_SEMA_V>;
1123def DS_GWS_SEMA_BR_vi     : DS_Real_vi<0x9b, DS_GWS_SEMA_BR>;
1124def DS_GWS_SEMA_P_vi      : DS_Real_vi<0x9c, DS_GWS_SEMA_P>;
1125def DS_GWS_BARRIER_vi     : DS_Real_vi<0x9d, DS_GWS_BARRIER>;
1126def DS_WRITE_ADDTID_B32_vi : DS_Real_vi<0x1d, DS_WRITE_ADDTID_B32>;
1127def DS_WRITE_B8_vi        : DS_Real_vi<0x1e, DS_WRITE_B8>;
1128def DS_WRITE_B16_vi       : DS_Real_vi<0x1f, DS_WRITE_B16>;
1129def DS_ADD_RTN_U32_vi     : DS_Real_vi<0x20, DS_ADD_RTN_U32>;
1130def DS_SUB_RTN_U32_vi     : DS_Real_vi<0x21, DS_SUB_RTN_U32>;
1131def DS_RSUB_RTN_U32_vi    : DS_Real_vi<0x22, DS_RSUB_RTN_U32>;
1132def DS_INC_RTN_U32_vi     : DS_Real_vi<0x23, DS_INC_RTN_U32>;
1133def DS_DEC_RTN_U32_vi     : DS_Real_vi<0x24, DS_DEC_RTN_U32>;
1134def DS_MIN_RTN_I32_vi     : DS_Real_vi<0x25, DS_MIN_RTN_I32>;
1135def DS_MAX_RTN_I32_vi     : DS_Real_vi<0x26, DS_MAX_RTN_I32>;
1136def DS_MIN_RTN_U32_vi     : DS_Real_vi<0x27, DS_MIN_RTN_U32>;
1137def DS_MAX_RTN_U32_vi     : DS_Real_vi<0x28, DS_MAX_RTN_U32>;
1138def DS_AND_RTN_B32_vi     : DS_Real_vi<0x29, DS_AND_RTN_B32>;
1139def DS_OR_RTN_B32_vi      : DS_Real_vi<0x2a, DS_OR_RTN_B32>;
1140def DS_XOR_RTN_B32_vi     : DS_Real_vi<0x2b, DS_XOR_RTN_B32>;
1141def DS_MSKOR_RTN_B32_vi   : DS_Real_vi<0x2c, DS_MSKOR_RTN_B32>;
1142def DS_WRXCHG_RTN_B32_vi  : DS_Real_vi<0x2d, DS_WRXCHG_RTN_B32>;
1143def DS_WRXCHG2_RTN_B32_vi : DS_Real_vi<0x2e, DS_WRXCHG2_RTN_B32>;
1144def DS_WRXCHG2ST64_RTN_B32_vi : DS_Real_vi<0x2f, DS_WRXCHG2ST64_RTN_B32>;
1145def DS_CMPST_RTN_B32_vi   : DS_Real_vi<0x30, DS_CMPST_RTN_B32>;
1146def DS_CMPST_RTN_F32_vi   : DS_Real_vi<0x31, DS_CMPST_RTN_F32>;
1147def DS_MIN_RTN_F32_vi     : DS_Real_vi<0x32, DS_MIN_RTN_F32>;
1148def DS_MAX_RTN_F32_vi     : DS_Real_vi<0x33, DS_MAX_RTN_F32>;
1149def DS_WRAP_RTN_B32_vi    : DS_Real_vi<0x34, DS_WRAP_RTN_B32>;
1150def DS_ADD_RTN_F32_vi     : DS_Real_vi<0x35, DS_ADD_RTN_F32>;
1151def DS_READ_B32_vi        : DS_Real_vi<0x36, DS_READ_B32>;
1152def DS_READ2_B32_vi       : DS_Real_vi<0x37, DS_READ2_B32>;
1153def DS_READ2ST64_B32_vi   : DS_Real_vi<0x38, DS_READ2ST64_B32>;
1154def DS_READ_I8_vi         : DS_Real_vi<0x39, DS_READ_I8>;
1155def DS_READ_U8_vi         : DS_Real_vi<0x3a, DS_READ_U8>;
1156def DS_READ_I16_vi        : DS_Real_vi<0x3b, DS_READ_I16>;
1157def DS_READ_U16_vi        : DS_Real_vi<0x3c, DS_READ_U16>;
1158def DS_READ_ADDTID_B32_vi : DS_Real_vi<0xb6, DS_READ_ADDTID_B32>;
1159def DS_CONSUME_vi         : DS_Real_vi<0xbd, DS_CONSUME>;
1160def DS_APPEND_vi          : DS_Real_vi<0xbe, DS_APPEND>;
1161def DS_ORDERED_COUNT_vi   : DS_Real_vi<0xbf, DS_ORDERED_COUNT>;
1162def DS_SWIZZLE_B32_vi     : DS_Real_vi<0x3d, DS_SWIZZLE_B32>;
1163def DS_PERMUTE_B32_vi     : DS_Real_vi<0x3e, DS_PERMUTE_B32>;
1164def DS_BPERMUTE_B32_vi    : DS_Real_vi<0x3f, DS_BPERMUTE_B32>;
1165
1166def DS_ADD_U64_vi         : DS_Real_vi<0x40, DS_ADD_U64>;
1167def DS_SUB_U64_vi         : DS_Real_vi<0x41, DS_SUB_U64>;
1168def DS_RSUB_U64_vi        : DS_Real_vi<0x42, DS_RSUB_U64>;
1169def DS_INC_U64_vi         : DS_Real_vi<0x43, DS_INC_U64>;
1170def DS_DEC_U64_vi         : DS_Real_vi<0x44, DS_DEC_U64>;
1171def DS_MIN_I64_vi         : DS_Real_vi<0x45, DS_MIN_I64>;
1172def DS_MAX_I64_vi         : DS_Real_vi<0x46, DS_MAX_I64>;
1173def DS_MIN_U64_vi         : DS_Real_vi<0x47, DS_MIN_U64>;
1174def DS_MAX_U64_vi         : DS_Real_vi<0x48, DS_MAX_U64>;
1175def DS_AND_B64_vi         : DS_Real_vi<0x49, DS_AND_B64>;
1176def DS_OR_B64_vi          : DS_Real_vi<0x4a, DS_OR_B64>;
1177def DS_XOR_B64_vi         : DS_Real_vi<0x4b, DS_XOR_B64>;
1178def DS_MSKOR_B64_vi       : DS_Real_vi<0x4c, DS_MSKOR_B64>;
1179def DS_WRITE_B64_vi       : DS_Real_vi<0x4d, DS_WRITE_B64>;
1180def DS_WRITE2_B64_vi      : DS_Real_vi<0x4E, DS_WRITE2_B64>;
1181def DS_WRITE2ST64_B64_vi  : DS_Real_vi<0x4f, DS_WRITE2ST64_B64>;
1182def DS_CMPST_B64_vi       : DS_Real_vi<0x50, DS_CMPST_B64>;
1183def DS_CMPST_F64_vi       : DS_Real_vi<0x51, DS_CMPST_F64>;
1184def DS_MIN_F64_vi         : DS_Real_vi<0x52, DS_MIN_F64>;
1185def DS_MAX_F64_vi         : DS_Real_vi<0x53, DS_MAX_F64>;
1186
1187def DS_WRITE_B8_D16_HI_vi  : DS_Real_vi<0x54, DS_WRITE_B8_D16_HI>;
1188def DS_WRITE_B16_D16_HI_vi : DS_Real_vi<0x55, DS_WRITE_B16_D16_HI>;
1189
1190def DS_READ_U8_D16_vi     : DS_Real_vi<0x56, DS_READ_U8_D16>;
1191def DS_READ_U8_D16_HI_vi  : DS_Real_vi<0x57, DS_READ_U8_D16_HI>;
1192def DS_READ_I8_D16_vi     : DS_Real_vi<0x58, DS_READ_I8_D16>;
1193def DS_READ_I8_D16_HI_vi  : DS_Real_vi<0x59, DS_READ_I8_D16_HI>;
1194def DS_READ_U16_D16_vi    : DS_Real_vi<0x5a, DS_READ_U16_D16>;
1195def DS_READ_U16_D16_HI_vi : DS_Real_vi<0x5b, DS_READ_U16_D16_HI>;
1196
1197def DS_ADD_RTN_U64_vi     : DS_Real_vi<0x60, DS_ADD_RTN_U64>;
1198def DS_SUB_RTN_U64_vi     : DS_Real_vi<0x61, DS_SUB_RTN_U64>;
1199def DS_RSUB_RTN_U64_vi    : DS_Real_vi<0x62, DS_RSUB_RTN_U64>;
1200def DS_INC_RTN_U64_vi     : DS_Real_vi<0x63, DS_INC_RTN_U64>;
1201def DS_DEC_RTN_U64_vi     : DS_Real_vi<0x64, DS_DEC_RTN_U64>;
1202def DS_MIN_RTN_I64_vi     : DS_Real_vi<0x65, DS_MIN_RTN_I64>;
1203def DS_MAX_RTN_I64_vi     : DS_Real_vi<0x66, DS_MAX_RTN_I64>;
1204def DS_MIN_RTN_U64_vi     : DS_Real_vi<0x67, DS_MIN_RTN_U64>;
1205def DS_MAX_RTN_U64_vi     : DS_Real_vi<0x68, DS_MAX_RTN_U64>;
1206def DS_AND_RTN_B64_vi     : DS_Real_vi<0x69, DS_AND_RTN_B64>;
1207def DS_OR_RTN_B64_vi      : DS_Real_vi<0x6a, DS_OR_RTN_B64>;
1208def DS_XOR_RTN_B64_vi     : DS_Real_vi<0x6b, DS_XOR_RTN_B64>;
1209def DS_MSKOR_RTN_B64_vi   : DS_Real_vi<0x6c, DS_MSKOR_RTN_B64>;
1210def DS_WRXCHG_RTN_B64_vi  : DS_Real_vi<0x6d, DS_WRXCHG_RTN_B64>;
1211def DS_WRXCHG2_RTN_B64_vi : DS_Real_vi<0x6e, DS_WRXCHG2_RTN_B64>;
1212def DS_WRXCHG2ST64_RTN_B64_vi : DS_Real_vi<0x6f, DS_WRXCHG2ST64_RTN_B64>;
1213def DS_CONDXCHG32_RTN_B64_vi   : DS_Real_vi<0x7e, DS_CONDXCHG32_RTN_B64>;
1214def DS_GWS_SEMA_RELEASE_ALL_vi : DS_Real_vi<0x98, DS_GWS_SEMA_RELEASE_ALL>;
1215def DS_CMPST_RTN_B64_vi   : DS_Real_vi<0x70, DS_CMPST_RTN_B64>;
1216def DS_CMPST_RTN_F64_vi   : DS_Real_vi<0x71, DS_CMPST_RTN_F64>;
1217def DS_MIN_RTN_F64_vi     : DS_Real_vi<0x72, DS_MIN_RTN_F64>;
1218def DS_MAX_RTN_F64_vi     : DS_Real_vi<0x73, DS_MAX_RTN_F64>;
1219
1220def DS_READ_B64_vi        : DS_Real_vi<0x76, DS_READ_B64>;
1221def DS_READ2_B64_vi       : DS_Real_vi<0x77, DS_READ2_B64>;
1222def DS_READ2ST64_B64_vi   : DS_Real_vi<0x78, DS_READ2ST64_B64>;
1223
1224def DS_ADD_SRC2_U32_vi    : DS_Real_vi<0x80, DS_ADD_SRC2_U32>;
1225def DS_SUB_SRC2_U32_vi    : DS_Real_vi<0x81, DS_SUB_SRC2_U32>;
1226def DS_RSUB_SRC2_U32_vi   : DS_Real_vi<0x82, DS_RSUB_SRC2_U32>;
1227def DS_INC_SRC2_U32_vi    : DS_Real_vi<0x83, DS_INC_SRC2_U32>;
1228def DS_DEC_SRC2_U32_vi    : DS_Real_vi<0x84, DS_DEC_SRC2_U32>;
1229def DS_MIN_SRC2_I32_vi    : DS_Real_vi<0x85, DS_MIN_SRC2_I32>;
1230def DS_MAX_SRC2_I32_vi    : DS_Real_vi<0x86, DS_MAX_SRC2_I32>;
1231def DS_MIN_SRC2_U32_vi    : DS_Real_vi<0x87, DS_MIN_SRC2_U32>;
1232def DS_MAX_SRC2_U32_vi    : DS_Real_vi<0x88, DS_MAX_SRC2_U32>;
1233def DS_AND_SRC2_B32_vi    : DS_Real_vi<0x89, DS_AND_SRC2_B32>;
1234def DS_OR_SRC2_B32_vi     : DS_Real_vi<0x8a, DS_OR_SRC2_B32>;
1235def DS_XOR_SRC2_B32_vi    : DS_Real_vi<0x8b, DS_XOR_SRC2_B32>;
1236def DS_WRITE_SRC2_B32_vi  : DS_Real_vi<0x8d, DS_WRITE_SRC2_B32>;
1237def DS_MIN_SRC2_F32_vi    : DS_Real_vi<0x92, DS_MIN_SRC2_F32>;
1238def DS_MAX_SRC2_F32_vi    : DS_Real_vi<0x93, DS_MAX_SRC2_F32>;
1239def DS_ADD_SRC2_F32_vi    : DS_Real_vi<0x95, DS_ADD_SRC2_F32>;
1240def DS_ADD_SRC2_U64_vi    : DS_Real_vi<0xc0, DS_ADD_SRC2_U64>;
1241def DS_SUB_SRC2_U64_vi    : DS_Real_vi<0xc1, DS_SUB_SRC2_U64>;
1242def DS_RSUB_SRC2_U64_vi   : DS_Real_vi<0xc2, DS_RSUB_SRC2_U64>;
1243def DS_INC_SRC2_U64_vi    : DS_Real_vi<0xc3, DS_INC_SRC2_U64>;
1244def DS_DEC_SRC2_U64_vi    : DS_Real_vi<0xc4, DS_DEC_SRC2_U64>;
1245def DS_MIN_SRC2_I64_vi    : DS_Real_vi<0xc5, DS_MIN_SRC2_I64>;
1246def DS_MAX_SRC2_I64_vi    : DS_Real_vi<0xc6, DS_MAX_SRC2_I64>;
1247def DS_MIN_SRC2_U64_vi    : DS_Real_vi<0xc7, DS_MIN_SRC2_U64>;
1248def DS_MAX_SRC2_U64_vi    : DS_Real_vi<0xc8, DS_MAX_SRC2_U64>;
1249def DS_AND_SRC2_B64_vi    : DS_Real_vi<0xc9, DS_AND_SRC2_B64>;
1250def DS_OR_SRC2_B64_vi     : DS_Real_vi<0xca, DS_OR_SRC2_B64>;
1251def DS_XOR_SRC2_B64_vi    : DS_Real_vi<0xcb, DS_XOR_SRC2_B64>;
1252def DS_WRITE_SRC2_B64_vi  : DS_Real_vi<0xcd, DS_WRITE_SRC2_B64>;
1253def DS_MIN_SRC2_F64_vi    : DS_Real_vi<0xd2, DS_MIN_SRC2_F64>;
1254def DS_MAX_SRC2_F64_vi    : DS_Real_vi<0xd3, DS_MAX_SRC2_F64>;
1255def DS_WRITE_B96_vi       : DS_Real_vi<0xde, DS_WRITE_B96>;
1256def DS_WRITE_B128_vi      : DS_Real_vi<0xdf, DS_WRITE_B128>;
1257def DS_READ_B96_vi        : DS_Real_vi<0xfe, DS_READ_B96>;
1258def DS_READ_B128_vi       : DS_Real_vi<0xff, DS_READ_B128>;
1259