1//===-- DSInstructions.td - DS Instruction Definitions --------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9class DS_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> pattern=[]> :
10  InstSI <outs, ins, "", pattern>,
11  SIMCInstr <opName, SIEncodingFamily.NONE> {
12
13  let LGKM_CNT = 1;
14  let DS = 1;
15  let Size = 8;
16  let UseNamedOperandTable = 1;
17
18  // Most instruction load and store data, so set this as the default.
19  let mayLoad = 1;
20  let mayStore = 1;
21  let maybeAtomic = 1;
22
23  let hasSideEffects = 0;
24  let SchedRW = [WriteLDS];
25
26  let isPseudo = 1;
27  let isCodeGenOnly = 1;
28
29  let AsmMatchConverter = "cvtDS";
30
31  string Mnemonic = opName;
32  string AsmOperands = asmOps;
33
34  // Well these bits a kind of hack because it would be more natural
35  // to test "outs" and "ins" dags for the presence of particular operands
36  bits<1> has_vdst = 1;
37  bits<1> has_addr = 1;
38  bits<1> has_data0 = 1;
39  bits<1> has_data1 = 1;
40
41  bits<1> has_gws_data0 = 0; // data0 is encoded as addr
42
43  bits<1> has_offset  = 1; // has "offset" that should be split to offset0,1
44  bits<1> has_offset0 = 1;
45  bits<1> has_offset1 = 1;
46
47  bits<1> has_gds = 1;
48  bits<1> gdsValue = 0; // if has_gds == 0 set gds to this value
49
50  bits<1> has_m0_read = 1;
51
52  let Uses = !if(has_m0_read, [M0, EXEC], [EXEC]);
53}
54
55class DS_Real <DS_Pseudo ds> :
56  InstSI <ds.OutOperandList, ds.InOperandList, ds.Mnemonic # ds.AsmOperands, []>,
57  Enc64 {
58
59  let isPseudo = 0;
60  let isCodeGenOnly = 0;
61  let DS = 1;
62  let UseNamedOperandTable = 1;
63
64  // copy relevant pseudo op flags
65  let SubtargetPredicate = ds.SubtargetPredicate;
66  let OtherPredicates    = ds.OtherPredicates;
67  let AsmMatchConverter  = ds.AsmMatchConverter;
68  let SchedRW            = ds.SchedRW;
69
70  // encoding fields
71  bits<10> vdst;
72  bits<1> gds;
73  bits<8> addr;
74  bits<10> data0;
75  bits<10> data1;
76  bits<8> offset0;
77  bits<8> offset1;
78
79  bits<16> offset;
80  let offset0 = !if(ds.has_offset, offset{7-0}, ?);
81  let offset1 = !if(ds.has_offset, offset{15-8}, ?);
82
83  bits<1> acc = !if(ds.has_vdst, vdst{9},
84                    !if(!or(ds.has_data0, ds.has_gws_data0), data0{9}, 0));
85}
86
87
88// DS Pseudo instructions
89
90class DS_0A1D_NORET<string opName, RegisterClass rc = VGPR_32>
91: DS_Pseudo<opName,
92  (outs),
93  (ins getLdStRegisterOperand<rc>.ret:$data0, offset:$offset, gds:$gds),
94  " $data0$offset$gds"> {
95
96  let has_addr = 0;
97  let has_data1 = 0;
98  let has_vdst = 0;
99}
100
101class DS_1A1D_NORET<string opName, RegisterClass rc = VGPR_32>
102: DS_Pseudo<opName,
103  (outs),
104  (ins VGPR_32:$addr, getLdStRegisterOperand<rc>.ret:$data0, offset:$offset, gds:$gds),
105  " $addr, $data0$offset$gds"> {
106
107  let has_data1 = 0;
108  let has_vdst = 0;
109  let IsAtomicNoRet = 1;
110}
111
112multiclass DS_1A1D_NORET_mc<string opName, RegisterClass rc = VGPR_32> {
113  def "" : DS_1A1D_NORET<opName, rc>,
114           AtomicNoRet<opName, 0>;
115
116  let has_m0_read = 0 in {
117    def _gfx9 : DS_1A1D_NORET<opName, rc>,
118                AtomicNoRet<opName#"_gfx9", 0>;
119  }
120}
121
122multiclass DS_1A1D_NORET_mc_gfx9<string opName, RegisterClass rc = VGPR_32> {
123  let has_m0_read = 0 in {
124    def "" : DS_1A1D_NORET<opName, rc>,
125                AtomicNoRet<opName, 0>;
126  }
127}
128
129class DS_1A2D_NORET<string opName, RegisterClass rc = VGPR_32,
130                    RegisterOperand data_op = getLdStRegisterOperand<rc>.ret>
131: DS_Pseudo<opName,
132  (outs),
133  (ins VGPR_32:$addr, data_op:$data0, data_op:$data1, offset:$offset, gds:$gds),
134  " $addr, $data0, $data1$offset$gds"> {
135
136  let has_vdst = 0;
137  let IsAtomicNoRet = 1;
138}
139
140multiclass DS_1A2D_NORET_mc<string opName, RegisterClass rc = VGPR_32> {
141  def "" : DS_1A2D_NORET<opName, rc>,
142           AtomicNoRet<opName, 0>;
143
144  let has_m0_read = 0 in {
145    def _gfx9 : DS_1A2D_NORET<opName, rc>,
146                AtomicNoRet<opName#"_gfx9", 0>;
147  }
148}
149
150class DS_1A2D_Off8_NORET <string opName, RegisterClass rc = VGPR_32,
151                          RegisterOperand data_op = getLdStRegisterOperand<rc>.ret>
152: DS_Pseudo<opName,
153  (outs),
154  (ins VGPR_32:$addr, data_op:$data0, data_op:$data1,
155       offset0:$offset0, offset1:$offset1, gds:$gds),
156  " $addr, $data0, $data1$offset0$offset1$gds"> {
157
158  let has_vdst = 0;
159  let has_offset = 0;
160  let AsmMatchConverter = "cvtDSOffset01";
161}
162
163multiclass DS_1A2D_Off8_NORET_mc <string opName, RegisterClass rc = VGPR_32> {
164  def "" : DS_1A2D_Off8_NORET<opName, rc>;
165
166  let has_m0_read = 0 in {
167    def _gfx9 : DS_1A2D_Off8_NORET<opName, rc>;
168  }
169}
170
171class DS_1A1D_RET <string opName, RegisterClass rc = VGPR_32,
172                  RegisterOperand data_op = getLdStRegisterOperand<rc>.ret>
173: DS_Pseudo<opName,
174  (outs data_op:$vdst),
175  (ins VGPR_32:$addr, data_op:$data0, offset:$offset, gds:$gds),
176  " $vdst, $addr, $data0$offset$gds"> {
177
178  let hasPostISelHook = 1;
179  let has_data1 = 0;
180  let IsAtomicRet = 1;
181}
182
183multiclass DS_1A1D_RET_mc <string opName, RegisterClass rc = VGPR_32,
184                           string NoRetOp = ""> {
185  def "" : DS_1A1D_RET<opName, rc>,
186    AtomicNoRet<NoRetOp, !ne(NoRetOp, "")>;
187
188  let has_m0_read = 0 in {
189    def _gfx9 : DS_1A1D_RET<opName, rc>,
190      AtomicNoRet<!if(!eq(NoRetOp, ""), "", NoRetOp#"_gfx9"),
191                  !ne(NoRetOp, "")>;
192  }
193}
194
195multiclass DS_1A1D_RET_mc_gfx9 <string opName, RegisterClass rc = VGPR_32,
196                                string NoRetOp = ""> {
197  let has_m0_read = 0 in {
198    def "" : DS_1A1D_RET<opName, rc>,
199      AtomicNoRet<!if(!eq(NoRetOp, ""), "", NoRetOp),
200                  !if(!eq(NoRetOp, ""), 0, 1)>;
201  }
202}
203
204class DS_1A2D_RET<string opName,
205                  RegisterClass rc = VGPR_32,
206                  RegisterClass src = rc,
207                  RegisterOperand dst_op = getLdStRegisterOperand<rc>.ret,
208                  RegisterOperand src_op = getLdStRegisterOperand<src>.ret>
209: DS_Pseudo<opName,
210  (outs dst_op:$vdst),
211  (ins VGPR_32:$addr, src_op:$data0, src_op:$data1, offset:$offset, gds:$gds),
212  " $vdst, $addr, $data0, $data1$offset$gds"> {
213
214  let hasPostISelHook = 1;
215  let IsAtomicRet = 1;
216}
217
218multiclass DS_1A2D_RET_mc<string opName,
219                          RegisterClass rc = VGPR_32,
220                          string NoRetOp = "",
221                          RegisterClass src = rc> {
222  def "" : DS_1A2D_RET<opName, rc, src>,
223    AtomicNoRet<NoRetOp, !ne(NoRetOp, "")>;
224
225  let has_m0_read = 0 in {
226    def _gfx9 : DS_1A2D_RET<opName, rc, src>,
227      AtomicNoRet<NoRetOp#"_gfx9", !ne(NoRetOp, "")>;
228  }
229}
230
231class DS_1A2D_Off8_RET<string opName,
232                       RegisterClass rc = VGPR_32,
233                       RegisterClass src = rc,
234                       RegisterOperand dst_op = getLdStRegisterOperand<rc>.ret,
235                       RegisterOperand src_op = getLdStRegisterOperand<src>.ret>
236: DS_Pseudo<opName,
237  (outs dst_op:$vdst),
238  (ins VGPR_32:$addr, src_op:$data0, src_op:$data1, offset0:$offset0, offset1:$offset1, gds:$gds),
239  " $vdst, $addr, $data0, $data1$offset0$offset1$gds"> {
240
241  let has_offset = 0;
242  let AsmMatchConverter = "cvtDSOffset01";
243
244  let hasPostISelHook = 1;
245}
246
247multiclass DS_1A2D_Off8_RET_mc<string opName,
248                               RegisterClass rc = VGPR_32,
249                               RegisterClass src = rc> {
250  def "" : DS_1A2D_Off8_RET<opName, rc, src>;
251
252  let has_m0_read = 0 in {
253    def _gfx9 : DS_1A2D_Off8_RET<opName, rc, src>;
254  }
255}
256
257
258class DS_1A_RET<string opName, RegisterClass rc = VGPR_32, bit HasTiedOutput = 0, Operand ofs = offset,
259                RegisterOperand data_op = getLdStRegisterOperand<rc>.ret>
260: DS_Pseudo<opName,
261  (outs data_op:$vdst),
262  !if(HasTiedOutput,
263    (ins VGPR_32:$addr, ofs:$offset, gds:$gds, data_op:$vdst_in),
264    (ins VGPR_32:$addr, ofs:$offset, gds:$gds)),
265  " $vdst, $addr$offset$gds"> {
266  let Constraints = !if(HasTiedOutput, "$vdst = $vdst_in", "");
267  let DisableEncoding = !if(HasTiedOutput, "$vdst_in", "");
268  let has_data0 = 0;
269  let has_data1 = 0;
270}
271
272multiclass DS_1A_RET_mc<string opName, RegisterClass rc = VGPR_32, bit HasTiedOutput = 0, Operand ofs = offset> {
273  def "" : DS_1A_RET<opName, rc, HasTiedOutput, ofs>;
274
275  let has_m0_read = 0 in {
276    def _gfx9 : DS_1A_RET<opName, rc, HasTiedOutput, ofs>;
277  }
278}
279
280class DS_1A_RET_Tied<string opName, RegisterClass rc = VGPR_32> :
281  DS_1A_RET<opName, rc, 1>;
282
283class DS_1A_Off8_RET <string opName, RegisterClass rc = VGPR_32>
284: DS_Pseudo<opName,
285  (outs getLdStRegisterOperand<rc>.ret:$vdst),
286  (ins VGPR_32:$addr, offset0:$offset0, offset1:$offset1, gds:$gds),
287  " $vdst, $addr$offset0$offset1$gds"> {
288
289  let has_offset = 0;
290  let has_data0 = 0;
291  let has_data1 = 0;
292  let AsmMatchConverter = "cvtDSOffset01";
293}
294
295multiclass DS_1A_Off8_RET_mc <string opName, RegisterClass rc = VGPR_32> {
296  def "" : DS_1A_Off8_RET<opName, rc>;
297
298  let has_m0_read = 0 in {
299    def _gfx9 : DS_1A_Off8_RET<opName, rc>;
300  }
301}
302
303class DS_1A_RET_GDS <string opName> : DS_Pseudo<opName,
304  (outs getLdStRegisterOperand<VGPR_32>.ret:$vdst),
305  (ins VGPR_32:$addr, offset:$offset),
306  " $vdst, $addr$offset gds"> {
307
308  let has_data0 = 0;
309  let has_data1 = 0;
310  let has_gds = 0;
311  let gdsValue = 1;
312  let AsmMatchConverter = "cvtDSGds";
313}
314
315class DS_0A_RET <string opName> : DS_Pseudo<opName,
316  (outs getLdStRegisterOperand<VGPR_32>.ret:$vdst),
317  (ins offset:$offset, gds:$gds),
318  " $vdst$offset$gds"> {
319
320  let mayLoad = 1;
321  let mayStore = 1;
322
323  let has_addr = 0;
324  let has_data0 = 0;
325  let has_data1 = 0;
326}
327
328class DS_1A <string opName> : DS_Pseudo<opName,
329  (outs),
330  (ins VGPR_32:$addr, offset:$offset, gds:$gds),
331  " $addr$offset$gds"> {
332
333  let mayLoad = 1;
334  let mayStore = 1;
335
336  let has_vdst = 0;
337  let has_data0 = 0;
338  let has_data1 = 0;
339}
340
341multiclass DS_1A_mc <string opName> {
342  def "" : DS_1A<opName>;
343
344  let has_m0_read = 0 in {
345    def _gfx9 : DS_1A<opName>;
346  }
347}
348
349
350class DS_GWS <string opName, dag ins, string asmOps>
351: DS_Pseudo<opName, (outs), ins, asmOps> {
352
353  let has_vdst  = 0;
354  let has_addr  = 0;
355  let has_data0 = 0;
356  let has_data1 = 0;
357
358  let has_gds   = 0;
359  let gdsValue  = 1;
360  let AsmMatchConverter = "cvtDSGds";
361}
362
363class DS_GWS_0D <string opName>
364: DS_GWS<opName,
365  (ins offset:$offset), "$offset gds"> {
366  let hasSideEffects = 1;
367}
368
369class DS_GWS_1D <string opName>
370: DS_GWS<opName,
371  (ins getLdStRegisterOperand<VGPR_32>.ret:$data0, offset:$offset),
372  " $data0$offset gds"> {
373
374  let has_gws_data0 = 1;
375  let hasSideEffects = 1;
376}
377
378class DS_VOID <string opName> : DS_Pseudo<opName,
379  (outs), (ins), ""> {
380  let mayLoad = 0;
381  let mayStore = 0;
382  let hasSideEffects = 1;
383  let UseNamedOperandTable = 0;
384  let AsmMatchConverter = "";
385
386  let has_vdst = 0;
387  let has_addr = 0;
388  let has_data0 = 0;
389  let has_data1 = 0;
390  let has_offset = 0;
391  let has_offset0 = 0;
392  let has_offset1 = 0;
393  let has_gds = 0;
394}
395
396class DS_1A1D_PERMUTE <string opName, SDPatternOperator node = null_frag,
397                       RegisterOperand data_op = getLdStRegisterOperand<VGPR_32>.ret>
398: DS_Pseudo<opName,
399  (outs data_op:$vdst),
400  (ins VGPR_32:$addr, data_op:$data0, offset:$offset),
401  " $vdst, $addr, $data0$offset",
402  [(set i32:$vdst,
403   (node (DS1Addr1Offset i32:$addr, i16:$offset), i32:$data0))] > {
404
405  let mayLoad = 0;
406  let mayStore = 0;
407  let isConvergent = 1;
408
409  let has_data1 = 0;
410  let has_gds = 0;
411}
412
413defm DS_ADD_U32       : DS_1A1D_NORET_mc<"ds_add_u32">;
414defm DS_SUB_U32       : DS_1A1D_NORET_mc<"ds_sub_u32">;
415defm DS_RSUB_U32      : DS_1A1D_NORET_mc<"ds_rsub_u32">;
416defm DS_INC_U32       : DS_1A1D_NORET_mc<"ds_inc_u32">;
417defm DS_DEC_U32       : DS_1A1D_NORET_mc<"ds_dec_u32">;
418defm DS_MIN_I32       : DS_1A1D_NORET_mc<"ds_min_i32">;
419defm DS_MAX_I32       : DS_1A1D_NORET_mc<"ds_max_i32">;
420defm DS_MIN_U32       : DS_1A1D_NORET_mc<"ds_min_u32">;
421defm DS_MAX_U32       : DS_1A1D_NORET_mc<"ds_max_u32">;
422defm DS_AND_B32       : DS_1A1D_NORET_mc<"ds_and_b32">;
423defm DS_OR_B32        : DS_1A1D_NORET_mc<"ds_or_b32">;
424defm DS_XOR_B32       : DS_1A1D_NORET_mc<"ds_xor_b32">;
425
426let SubtargetPredicate = HasLDSFPAtomics in {
427defm DS_ADD_F32       : DS_1A1D_NORET_mc<"ds_add_f32">;
428}
429
430// FIXME: Are these really present pre-gfx8?
431defm DS_MIN_F32       : DS_1A1D_NORET_mc<"ds_min_f32">;
432defm DS_MAX_F32       : DS_1A1D_NORET_mc<"ds_max_f32">;
433
434let mayLoad = 0 in {
435defm DS_WRITE_B8      : DS_1A1D_NORET_mc<"ds_write_b8">;
436defm DS_WRITE_B16     : DS_1A1D_NORET_mc<"ds_write_b16">;
437defm DS_WRITE_B32     : DS_1A1D_NORET_mc<"ds_write_b32">;
438defm DS_WRITE2_B32    : DS_1A2D_Off8_NORET_mc<"ds_write2_b32">;
439defm DS_WRITE2ST64_B32: DS_1A2D_Off8_NORET_mc<"ds_write2st64_b32">;
440
441
442let has_m0_read = 0 in {
443
444let SubtargetPredicate = HasD16LoadStore in {
445def DS_WRITE_B8_D16_HI  : DS_1A1D_NORET<"ds_write_b8_d16_hi">;
446def DS_WRITE_B16_D16_HI : DS_1A1D_NORET<"ds_write_b16_d16_hi">;
447}
448
449} // End has_m0_read = 0
450
451let SubtargetPredicate = HasDSAddTid in {
452def DS_WRITE_ADDTID_B32 : DS_0A1D_NORET<"ds_write_addtid_b32">;
453}
454
455} // End mayLoad = 0
456
457let SubtargetPredicate = isGFX90APlus in {
458  defm DS_ADD_F64     : DS_1A1D_NORET_mc_gfx9<"ds_add_f64", VReg_64>;
459  defm DS_ADD_RTN_F64 : DS_1A1D_RET_mc_gfx9<"ds_add_rtn_f64 ", VReg_64, "ds_add_f64">;
460} // End SubtargetPredicate = isGFX90APlus
461
462defm DS_MSKOR_B32     : DS_1A2D_NORET_mc<"ds_mskor_b32">;
463defm DS_CMPST_B32     : DS_1A2D_NORET_mc<"ds_cmpst_b32">;
464defm DS_CMPST_F32     : DS_1A2D_NORET_mc<"ds_cmpst_f32">;
465
466defm DS_ADD_U64       : DS_1A1D_NORET_mc<"ds_add_u64", VReg_64>;
467defm DS_SUB_U64       : DS_1A1D_NORET_mc<"ds_sub_u64", VReg_64>;
468defm DS_RSUB_U64      : DS_1A1D_NORET_mc<"ds_rsub_u64", VReg_64>;
469defm DS_INC_U64       : DS_1A1D_NORET_mc<"ds_inc_u64", VReg_64>;
470defm DS_DEC_U64       : DS_1A1D_NORET_mc<"ds_dec_u64", VReg_64>;
471defm DS_MIN_I64       : DS_1A1D_NORET_mc<"ds_min_i64", VReg_64>;
472defm DS_MAX_I64       : DS_1A1D_NORET_mc<"ds_max_i64", VReg_64>;
473defm DS_MIN_U64       : DS_1A1D_NORET_mc<"ds_min_u64", VReg_64>;
474defm DS_MAX_U64       : DS_1A1D_NORET_mc<"ds_max_u64", VReg_64>;
475defm DS_AND_B64       : DS_1A1D_NORET_mc<"ds_and_b64", VReg_64>;
476defm DS_OR_B64        : DS_1A1D_NORET_mc<"ds_or_b64", VReg_64>;
477defm DS_XOR_B64       : DS_1A1D_NORET_mc<"ds_xor_b64", VReg_64>;
478defm DS_MSKOR_B64     : DS_1A2D_NORET_mc<"ds_mskor_b64", VReg_64>;
479let mayLoad = 0 in {
480defm DS_WRITE_B64     : DS_1A1D_NORET_mc<"ds_write_b64", VReg_64>;
481defm DS_WRITE2_B64    : DS_1A2D_Off8_NORET_mc<"ds_write2_b64", VReg_64>;
482defm DS_WRITE2ST64_B64: DS_1A2D_Off8_NORET_mc<"ds_write2st64_b64", VReg_64>;
483}
484defm DS_CMPST_B64     : DS_1A2D_NORET_mc<"ds_cmpst_b64", VReg_64>;
485defm DS_CMPST_F64     : DS_1A2D_NORET_mc<"ds_cmpst_f64", VReg_64>;
486defm DS_MIN_F64       : DS_1A1D_NORET_mc<"ds_min_f64", VReg_64>;
487defm DS_MAX_F64       : DS_1A1D_NORET_mc<"ds_max_f64", VReg_64>;
488
489defm DS_ADD_RTN_U32   : DS_1A1D_RET_mc<"ds_add_rtn_u32", VGPR_32, "ds_add_u32">;
490
491let SubtargetPredicate = HasLDSFPAtomics in {
492defm DS_ADD_RTN_F32   : DS_1A1D_RET_mc<"ds_add_rtn_f32", VGPR_32, "ds_add_f32">;
493}
494defm DS_SUB_RTN_U32   : DS_1A1D_RET_mc<"ds_sub_rtn_u32", VGPR_32, "ds_sub_u32">;
495defm DS_RSUB_RTN_U32  : DS_1A1D_RET_mc<"ds_rsub_rtn_u32", VGPR_32, "ds_rsub_u32">;
496defm DS_INC_RTN_U32   : DS_1A1D_RET_mc<"ds_inc_rtn_u32", VGPR_32, "ds_inc_u32">;
497defm DS_DEC_RTN_U32   : DS_1A1D_RET_mc<"ds_dec_rtn_u32", VGPR_32, "ds_dec_u32">;
498defm DS_MIN_RTN_I32   : DS_1A1D_RET_mc<"ds_min_rtn_i32", VGPR_32, "ds_min_i32">;
499defm DS_MAX_RTN_I32   : DS_1A1D_RET_mc<"ds_max_rtn_i32", VGPR_32, "ds_max_i32">;
500defm DS_MIN_RTN_U32   : DS_1A1D_RET_mc<"ds_min_rtn_u32", VGPR_32, "ds_min_u32">;
501defm DS_MAX_RTN_U32   : DS_1A1D_RET_mc<"ds_max_rtn_u32", VGPR_32, "ds_max_u32">;
502defm DS_AND_RTN_B32   : DS_1A1D_RET_mc<"ds_and_rtn_b32", VGPR_32, "ds_and_b32">;
503defm DS_OR_RTN_B32    : DS_1A1D_RET_mc<"ds_or_rtn_b32", VGPR_32, "ds_or_b32">;
504defm DS_XOR_RTN_B32   : DS_1A1D_RET_mc<"ds_xor_rtn_b32", VGPR_32, "ds_xor_b32">;
505defm DS_MSKOR_RTN_B32 : DS_1A2D_RET_mc<"ds_mskor_rtn_b32", VGPR_32, "ds_mskor_b32">;
506defm DS_CMPST_RTN_B32 : DS_1A2D_RET_mc<"ds_cmpst_rtn_b32", VGPR_32, "ds_cmpst_b32">;
507defm DS_CMPST_RTN_F32 : DS_1A2D_RET_mc<"ds_cmpst_rtn_f32", VGPR_32, "ds_cmpst_f32">;
508defm DS_MIN_RTN_F32   : DS_1A1D_RET_mc<"ds_min_rtn_f32", VGPR_32, "ds_min_f32">;
509defm DS_MAX_RTN_F32   : DS_1A1D_RET_mc<"ds_max_rtn_f32", VGPR_32, "ds_max_f32">;
510
511defm DS_WRXCHG_RTN_B32 : DS_1A1D_RET_mc<"ds_wrxchg_rtn_b32">;
512defm DS_WRXCHG2_RTN_B32 : DS_1A2D_Off8_RET_mc<"ds_wrxchg2_rtn_b32", VReg_64, VGPR_32>;
513defm DS_WRXCHG2ST64_RTN_B32 : DS_1A2D_Off8_RET_mc<"ds_wrxchg2st64_rtn_b32", VReg_64, VGPR_32>;
514
515defm DS_ADD_RTN_U64  : DS_1A1D_RET_mc<"ds_add_rtn_u64", VReg_64, "ds_add_u64">;
516defm DS_SUB_RTN_U64  : DS_1A1D_RET_mc<"ds_sub_rtn_u64", VReg_64, "ds_sub_u64">;
517defm DS_RSUB_RTN_U64  : DS_1A1D_RET_mc<"ds_rsub_rtn_u64", VReg_64, "ds_rsub_u64">;
518defm DS_INC_RTN_U64   : DS_1A1D_RET_mc<"ds_inc_rtn_u64", VReg_64, "ds_inc_u64">;
519defm DS_DEC_RTN_U64   : DS_1A1D_RET_mc<"ds_dec_rtn_u64", VReg_64, "ds_dec_u64">;
520defm DS_MIN_RTN_I64    : DS_1A1D_RET_mc<"ds_min_rtn_i64", VReg_64, "ds_min_i64">;
521defm DS_MAX_RTN_I64    : DS_1A1D_RET_mc<"ds_max_rtn_i64", VReg_64, "ds_max_i64">;
522defm DS_MIN_RTN_U64   : DS_1A1D_RET_mc<"ds_min_rtn_u64", VReg_64, "ds_min_u64">;
523defm DS_MAX_RTN_U64   : DS_1A1D_RET_mc<"ds_max_rtn_u64", VReg_64, "ds_max_u64">;
524defm DS_AND_RTN_B64    : DS_1A1D_RET_mc<"ds_and_rtn_b64", VReg_64, "ds_and_b64">;
525defm DS_OR_RTN_B64     : DS_1A1D_RET_mc<"ds_or_rtn_b64", VReg_64, "ds_or_b64">;
526defm DS_XOR_RTN_B64    : DS_1A1D_RET_mc<"ds_xor_rtn_b64", VReg_64, "ds_xor_b64">;
527defm DS_MSKOR_RTN_B64  : DS_1A2D_RET_mc<"ds_mskor_rtn_b64", VReg_64, "ds_mskor_b64">;
528defm DS_CMPST_RTN_B64  : DS_1A2D_RET_mc<"ds_cmpst_rtn_b64", VReg_64, "ds_cmpst_b64">;
529defm DS_CMPST_RTN_F64  : DS_1A2D_RET_mc<"ds_cmpst_rtn_f64", VReg_64, "ds_cmpst_f64">;
530defm DS_MIN_RTN_F64    : DS_1A1D_RET_mc<"ds_min_rtn_f64", VReg_64, "ds_min_f64">;
531defm DS_MAX_RTN_F64    : DS_1A1D_RET_mc<"ds_max_rtn_f64", VReg_64, "ds_max_f64">;
532
533defm DS_WRXCHG_RTN_B64 : DS_1A1D_RET_mc<"ds_wrxchg_rtn_b64", VReg_64>;
534defm DS_WRXCHG2_RTN_B64 : DS_1A2D_Off8_RET_mc<"ds_wrxchg2_rtn_b64", VReg_128, VReg_64>;
535defm DS_WRXCHG2ST64_RTN_B64 : DS_1A2D_Off8_RET_mc<"ds_wrxchg2st64_rtn_b64", VReg_128, VReg_64>;
536
537let isConvergent = 1, usesCustomInserter = 1 in {
538def DS_GWS_INIT       : DS_GWS_1D<"ds_gws_init"> {
539  let mayLoad = 0;
540}
541def DS_GWS_SEMA_V     : DS_GWS_0D<"ds_gws_sema_v">;
542def DS_GWS_SEMA_BR    : DS_GWS_1D<"ds_gws_sema_br">;
543def DS_GWS_SEMA_P     : DS_GWS_0D<"ds_gws_sema_p">;
544def DS_GWS_BARRIER    : DS_GWS_1D<"ds_gws_barrier">;
545}
546
547let SubtargetPredicate = HasDsSrc2Insts in {
548def DS_ADD_SRC2_U32   : DS_1A<"ds_add_src2_u32">;
549def DS_SUB_SRC2_U32   : DS_1A<"ds_sub_src2_u32">;
550def DS_RSUB_SRC2_U32  : DS_1A<"ds_rsub_src2_u32">;
551def DS_INC_SRC2_U32   : DS_1A<"ds_inc_src2_u32">;
552def DS_DEC_SRC2_U32   : DS_1A<"ds_dec_src2_u32">;
553def DS_MIN_SRC2_I32   : DS_1A<"ds_min_src2_i32">;
554def DS_MAX_SRC2_I32   : DS_1A<"ds_max_src2_i32">;
555def DS_MIN_SRC2_U32   : DS_1A<"ds_min_src2_u32">;
556def DS_MAX_SRC2_U32   : DS_1A<"ds_max_src2_u32">;
557def DS_AND_SRC2_B32   : DS_1A<"ds_and_src2_b32">;
558def DS_OR_SRC2_B32    : DS_1A<"ds_or_src2_b32">;
559def DS_XOR_SRC2_B32   : DS_1A<"ds_xor_src2_b32">;
560def DS_MIN_SRC2_F32   : DS_1A<"ds_min_src2_f32">;
561def DS_MAX_SRC2_F32   : DS_1A<"ds_max_src2_f32">;
562
563def DS_ADD_SRC2_U64   : DS_1A<"ds_add_src2_u64">;
564def DS_SUB_SRC2_U64   : DS_1A<"ds_sub_src2_u64">;
565def DS_RSUB_SRC2_U64  : DS_1A<"ds_rsub_src2_u64">;
566def DS_INC_SRC2_U64   : DS_1A<"ds_inc_src2_u64">;
567def DS_DEC_SRC2_U64   : DS_1A<"ds_dec_src2_u64">;
568def DS_MIN_SRC2_I64   : DS_1A<"ds_min_src2_i64">;
569def DS_MAX_SRC2_I64   : DS_1A<"ds_max_src2_i64">;
570def DS_MIN_SRC2_U64   : DS_1A<"ds_min_src2_u64">;
571def DS_MAX_SRC2_U64   : DS_1A<"ds_max_src2_u64">;
572def DS_AND_SRC2_B64   : DS_1A<"ds_and_src2_b64">;
573def DS_OR_SRC2_B64    : DS_1A<"ds_or_src2_b64">;
574def DS_XOR_SRC2_B64   : DS_1A<"ds_xor_src2_b64">;
575def DS_MIN_SRC2_F64   : DS_1A<"ds_min_src2_f64">;
576def DS_MAX_SRC2_F64   : DS_1A<"ds_max_src2_f64">;
577
578def DS_WRITE_SRC2_B32 : DS_1A<"ds_write_src2_b32">;
579def DS_WRITE_SRC2_B64 : DS_1A<"ds_write_src2_b64">;
580} // End SubtargetPredicate = HasDsSrc2Insts
581
582let Uses = [EXEC], mayLoad = 0, mayStore = 0, isConvergent = 1 in {
583def DS_SWIZZLE_B32 : DS_1A_RET <"ds_swizzle_b32", VGPR_32, 0, SwizzleImm>;
584}
585
586let mayStore = 0 in {
587defm DS_READ_I8      : DS_1A_RET_mc<"ds_read_i8">;
588defm DS_READ_U8      : DS_1A_RET_mc<"ds_read_u8">;
589defm DS_READ_I16     : DS_1A_RET_mc<"ds_read_i16">;
590defm DS_READ_U16     : DS_1A_RET_mc<"ds_read_u16">;
591defm DS_READ_B32     : DS_1A_RET_mc<"ds_read_b32">;
592defm DS_READ_B64     : DS_1A_RET_mc<"ds_read_b64", VReg_64>;
593
594defm DS_READ2_B32    : DS_1A_Off8_RET_mc<"ds_read2_b32", VReg_64>;
595defm DS_READ2ST64_B32: DS_1A_Off8_RET_mc<"ds_read2st64_b32", VReg_64>;
596
597defm DS_READ2_B64    : DS_1A_Off8_RET_mc<"ds_read2_b64", VReg_128>;
598defm DS_READ2ST64_B64: DS_1A_Off8_RET_mc<"ds_read2st64_b64", VReg_128>;
599
600let has_m0_read = 0 in {
601let SubtargetPredicate = HasD16LoadStore in {
602def DS_READ_U8_D16     : DS_1A_RET_Tied<"ds_read_u8_d16">;
603def DS_READ_U8_D16_HI  : DS_1A_RET_Tied<"ds_read_u8_d16_hi">;
604def DS_READ_I8_D16     : DS_1A_RET_Tied<"ds_read_i8_d16">;
605def DS_READ_I8_D16_HI  : DS_1A_RET_Tied<"ds_read_i8_d16_hi">;
606def DS_READ_U16_D16    : DS_1A_RET_Tied<"ds_read_u16_d16">;
607def DS_READ_U16_D16_HI : DS_1A_RET_Tied<"ds_read_u16_d16_hi">;
608}
609} // End has_m0_read = 0
610
611let SubtargetPredicate = HasDSAddTid in {
612def DS_READ_ADDTID_B32 : DS_0A_RET<"ds_read_addtid_b32">;
613}
614
615} // End mayStore = 0
616
617def DS_CONSUME       : DS_0A_RET<"ds_consume">;
618def DS_APPEND        : DS_0A_RET<"ds_append">;
619def DS_ORDERED_COUNT : DS_1A_RET_GDS<"ds_ordered_count">;
620
621//===----------------------------------------------------------------------===//
622// Instruction definitions for CI and newer.
623//===----------------------------------------------------------------------===//
624
625let SubtargetPredicate = isGFX7Plus in {
626
627defm DS_WRAP_RTN_B32 : DS_1A2D_RET_mc<"ds_wrap_rtn_b32", VGPR_32>;
628defm DS_CONDXCHG32_RTN_B64 : DS_1A1D_RET_mc<"ds_condxchg32_rtn_b64", VReg_64>;
629
630let isConvergent = 1, usesCustomInserter = 1 in {
631def DS_GWS_SEMA_RELEASE_ALL : DS_GWS_0D<"ds_gws_sema_release_all">;
632}
633
634let mayStore = 0 in {
635defm DS_READ_B96 : DS_1A_RET_mc<"ds_read_b96", VReg_96>;
636defm DS_READ_B128: DS_1A_RET_mc<"ds_read_b128", VReg_128>;
637} // End mayStore = 0
638
639let mayLoad = 0 in {
640defm DS_WRITE_B96 : DS_1A1D_NORET_mc<"ds_write_b96", VReg_96>;
641defm DS_WRITE_B128 : DS_1A1D_NORET_mc<"ds_write_b128", VReg_128>;
642} // End mayLoad = 0
643
644def DS_NOP : DS_VOID<"ds_nop">;
645
646} // let SubtargetPredicate = isGFX7Plus
647
648//===----------------------------------------------------------------------===//
649// Instruction definitions for VI and newer.
650//===----------------------------------------------------------------------===//
651
652let SubtargetPredicate = isGFX8Plus in {
653
654let Uses = [EXEC] in {
655def DS_PERMUTE_B32  : DS_1A1D_PERMUTE <"ds_permute_b32",
656                                       int_amdgcn_ds_permute>;
657def DS_BPERMUTE_B32 : DS_1A1D_PERMUTE <"ds_bpermute_b32",
658                                       int_amdgcn_ds_bpermute>;
659}
660
661} // let SubtargetPredicate = isGFX8Plus
662
663let SubtargetPredicate = HasLDSFPAtomics, OtherPredicates = [HasDsSrc2Insts] in {
664def DS_ADD_SRC2_F32 : DS_1A<"ds_add_src2_f32">;
665}
666
667//===----------------------------------------------------------------------===//
668// DS Patterns
669//===----------------------------------------------------------------------===//
670
671def : GCNPat <
672  (int_amdgcn_ds_swizzle i32:$src, timm:$offset16),
673  (DS_SWIZZLE_B32 VGPR_32:$src, (as_i16timm $offset16), (i1 0))
674>;
675
676class DSReadPat <DS_Pseudo inst, ValueType vt, PatFrag frag, int gds=0> : GCNPat <
677  (vt (frag (DS1Addr1Offset i32:$ptr, i16:$offset))),
678  (inst $ptr, offset:$offset, (i1 gds))
679>;
680
681multiclass DSReadPat_mc<DS_Pseudo inst, ValueType vt, string frag> {
682
683  let OtherPredicates = [LDSRequiresM0Init] in {
684    def : DSReadPat<inst, vt, !cast<PatFrag>(frag#"_m0")>;
685  }
686
687  let OtherPredicates = [NotLDSRequiresM0Init] in {
688    def : DSReadPat<!cast<DS_Pseudo>(!cast<string>(inst)#"_gfx9"), vt, !cast<PatFrag>(frag)>;
689  }
690}
691
692class DSReadPat_D16 <DS_Pseudo inst, PatFrag frag, ValueType vt> : GCNPat <
693  (frag (DS1Addr1Offset i32:$ptr, i16:$offset), vt:$in),
694  (inst $ptr, offset:$offset, (i1 0), $in)
695>;
696
697defm : DSReadPat_mc <DS_READ_I8, i32, "sextloadi8_local">;
698defm : DSReadPat_mc <DS_READ_I8,  i16, "sextloadi8_local">;
699defm : DSReadPat_mc <DS_READ_U8,  i32, "extloadi8_local">;
700defm : DSReadPat_mc <DS_READ_U8,  i32, "zextloadi8_local">;
701defm : DSReadPat_mc <DS_READ_U8,  i16, "extloadi8_local">;
702defm : DSReadPat_mc <DS_READ_U8,  i16, "zextloadi8_local">;
703defm : DSReadPat_mc <DS_READ_I16, i32, "sextloadi16_local">;
704defm : DSReadPat_mc <DS_READ_I16, i32, "sextloadi16_local">;
705defm : DSReadPat_mc <DS_READ_U16, i32, "extloadi16_local">;
706defm : DSReadPat_mc <DS_READ_U16, i32, "zextloadi16_local">;
707defm : DSReadPat_mc <DS_READ_U16, i16, "load_local">;
708
709foreach vt = Reg32Types.types in {
710defm : DSReadPat_mc <DS_READ_B32, vt, "load_local">;
711}
712
713defm : DSReadPat_mc <DS_READ_B32, i32, "atomic_load_32_local">;
714defm : DSReadPat_mc <DS_READ_B64, i64, "atomic_load_64_local">;
715
716// Prefer ds_read over ds_read2, all other things being equal, because it has
717// a larger immediate offset range.
718let AddedComplexity = 100 in {
719
720foreach vt = VReg_64.RegTypes in {
721defm : DSReadPat_mc <DS_READ_B64, vt, "load_align8_local">;
722}
723
724let SubtargetPredicate = isGFX7Plus in {
725
726foreach vt = VReg_96.RegTypes in {
727defm : DSReadPat_mc <DS_READ_B96, vt, "load_align16_local">;
728}
729
730// For performance reasons restrict this to alignment >= 16 even with
731// unaligned-access-mode. At lower alignments ds_read2_b64 is always a better
732// choice.
733foreach vt = VReg_128.RegTypes in {
734defm : DSReadPat_mc <DS_READ_B128, vt, "load_align16_local">;
735}
736
737let SubtargetPredicate = HasUnalignedAccessMode in {
738
739foreach vt = VReg_96.RegTypes in {
740defm : DSReadPat_mc <DS_READ_B96, vt, "load_local">;
741}
742
743} // End SubtargetPredicate = HasUnalignedAccessMode
744
745} // End SubtargetPredicate = isGFX7Plus
746
747} // End AddedComplexity = 100
748
749let OtherPredicates = [D16PreservesUnusedBits] in {
750def : DSReadPat_D16<DS_READ_U16_D16_HI, load_d16_hi_local, v2i16>;
751def : DSReadPat_D16<DS_READ_U16_D16_HI, load_d16_hi_local, v2f16>;
752def : DSReadPat_D16<DS_READ_U8_D16_HI, az_extloadi8_d16_hi_local, v2i16>;
753def : DSReadPat_D16<DS_READ_U8_D16_HI, az_extloadi8_d16_hi_local, v2f16>;
754def : DSReadPat_D16<DS_READ_I8_D16_HI, sextloadi8_d16_hi_local, v2i16>;
755def : DSReadPat_D16<DS_READ_I8_D16_HI, sextloadi8_d16_hi_local, v2f16>;
756
757def : DSReadPat_D16<DS_READ_U16_D16, load_d16_lo_local, v2i16>;
758def : DSReadPat_D16<DS_READ_U16_D16, load_d16_lo_local, v2f16>;
759def : DSReadPat_D16<DS_READ_U8_D16, az_extloadi8_d16_lo_local, v2i16>;
760def : DSReadPat_D16<DS_READ_U8_D16, az_extloadi8_d16_lo_local, v2f16>;
761def : DSReadPat_D16<DS_READ_I8_D16, sextloadi8_d16_lo_local, v2i16>;
762def : DSReadPat_D16<DS_READ_I8_D16, sextloadi8_d16_lo_local, v2f16>;
763}
764
765class DSWritePat <DS_Pseudo inst, ValueType vt, PatFrag frag, int gds=0> : GCNPat <
766  (frag vt:$value, (DS1Addr1Offset i32:$ptr, i16:$offset)),
767  (inst $ptr, getVregSrcForVT<vt>.ret:$value, offset:$offset, (i1 gds))
768>;
769
770multiclass DSWritePat_mc <DS_Pseudo inst, ValueType vt, string frag> {
771  let OtherPredicates = [LDSRequiresM0Init] in {
772    def : DSWritePat<inst, vt, !cast<PatFrag>(frag#"_m0")>;
773  }
774
775  let OtherPredicates = [NotLDSRequiresM0Init] in {
776    def : DSWritePat<!cast<DS_Pseudo>(!cast<string>(inst)#"_gfx9"), vt, !cast<PatFrag>(frag)>;
777  }
778}
779
780// Irritatingly, atomic_store reverses the order of operands from a
781// normal store.
782class DSAtomicWritePat <DS_Pseudo inst, ValueType vt, PatFrag frag> : GCNPat <
783  (frag (DS1Addr1Offset i32:$ptr, i16:$offset), vt:$value),
784  (inst $ptr, getVregSrcForVT<vt>.ret:$value, offset:$offset, (i1 0))
785>;
786
787multiclass DSAtomicWritePat_mc <DS_Pseudo inst, ValueType vt, string frag> {
788  let OtherPredicates = [LDSRequiresM0Init] in {
789    def : DSAtomicWritePat<inst, vt, !cast<PatFrag>(frag#"_m0")>;
790  }
791
792  let OtherPredicates = [NotLDSRequiresM0Init] in {
793    def : DSAtomicWritePat<!cast<DS_Pseudo>(!cast<string>(inst)#"_gfx9"), vt, !cast<PatFrag>(frag)>;
794  }
795}
796
797defm : DSWritePat_mc <DS_WRITE_B8, i32, "truncstorei8_local">;
798defm : DSWritePat_mc <DS_WRITE_B16, i32, "truncstorei16_local">;
799defm : DSWritePat_mc <DS_WRITE_B8, i16, "truncstorei8_local">;
800defm : DSWritePat_mc <DS_WRITE_B16, i16, "store_local">;
801
802foreach vt = Reg32Types.types in {
803defm : DSWritePat_mc <DS_WRITE_B32, vt, "store_local">;
804}
805
806defm : DSAtomicWritePat_mc <DS_WRITE_B32, i32, "atomic_store_local_32">;
807defm : DSAtomicWritePat_mc <DS_WRITE_B64, i64, "atomic_store_local_64">;
808
809let OtherPredicates = [D16PreservesUnusedBits] in {
810def : DSWritePat <DS_WRITE_B16_D16_HI, i32, store_hi16_local>;
811def : DSWritePat <DS_WRITE_B8_D16_HI, i32, truncstorei8_hi16_local>;
812}
813
814class DS64Bit4ByteAlignedReadPat<DS_Pseudo inst, ValueType vt, PatFrag frag> : GCNPat <
815  (vt:$value (frag (DS64Bit4ByteAligned i32:$ptr, i8:$offset0, i8:$offset1))),
816  (inst $ptr, $offset0, $offset1, (i1 0))
817>;
818
819class DS64Bit4ByteAlignedWritePat<DS_Pseudo inst, ValueType vt, PatFrag frag> : GCNPat<
820  (frag vt:$value, (DS64Bit4ByteAligned i32:$ptr, i8:$offset0, i8:$offset1)),
821  (inst $ptr, (i32 (EXTRACT_SUBREG VReg_64:$value, sub0)),
822              (i32 (EXTRACT_SUBREG VReg_64:$value, sub1)), $offset0, $offset1,
823              (i1 0))
824>;
825
826class DS128Bit8ByteAlignedReadPat<DS_Pseudo inst, ValueType vt, PatFrag frag> : GCNPat <
827  (vt:$value (frag (DS128Bit8ByteAligned i32:$ptr, i8:$offset0, i8:$offset1))),
828  (inst $ptr, $offset0, $offset1, (i1 0))
829>;
830
831class DS128Bit8ByteAlignedWritePat<DS_Pseudo inst, ValueType vt, PatFrag frag> : GCNPat<
832  (frag vt:$value, (DS128Bit8ByteAligned i32:$ptr, i8:$offset0, i8:$offset1)),
833  (inst $ptr, (i64 (EXTRACT_SUBREG VReg_128:$value, sub0_sub1)),
834              (i64 (EXTRACT_SUBREG VReg_128:$value, sub2_sub3)), $offset0, $offset1,
835              (i1 0))
836>;
837
838multiclass DS64Bit4ByteAlignedPat_mc<ValueType vt> {
839  let OtherPredicates = [LDSRequiresM0Init, isGFX7Plus] in {
840    def : DS64Bit4ByteAlignedReadPat<DS_READ2_B32, vt, load_local_m0>;
841    def : DS64Bit4ByteAlignedWritePat<DS_WRITE2_B32, vt, store_local_m0>;
842  }
843
844  let OtherPredicates = [NotLDSRequiresM0Init] in {
845    def : DS64Bit4ByteAlignedReadPat<DS_READ2_B32_gfx9, vt, load_local>;
846    def : DS64Bit4ByteAlignedWritePat<DS_WRITE2_B32_gfx9, vt, store_local>;
847  }
848}
849
850multiclass DS128Bit8ByteAlignedPat_mc<ValueType vt> {
851  let OtherPredicates = [LDSRequiresM0Init, isGFX7Plus] in {
852    def : DS128Bit8ByteAlignedReadPat<DS_READ2_B64, vt, load_local_m0>;
853    def : DS128Bit8ByteAlignedWritePat<DS_WRITE2_B64, vt, store_local_m0>;
854  }
855
856  let OtherPredicates = [NotLDSRequiresM0Init] in {
857    def : DS128Bit8ByteAlignedReadPat<DS_READ2_B64_gfx9, vt, load_local>;
858    def : DS128Bit8ByteAlignedWritePat<DS_WRITE2_B64_gfx9, vt, store_local>;
859  }
860}
861
862// v2i32 loads are split into i32 loads on SI during lowering, due to a bug
863// related to bounds checking.
864foreach vt = VReg_64.RegTypes in {
865defm : DS64Bit4ByteAlignedPat_mc<vt>;
866}
867
868foreach vt = VReg_128.RegTypes in {
869defm : DS128Bit8ByteAlignedPat_mc<vt>;
870}
871
872// Prefer ds_write over ds_write2, all other things being equal, because it has
873// a larger immediate offset range.
874let AddedComplexity = 100 in {
875
876foreach vt = VReg_64.RegTypes in {
877defm : DSWritePat_mc <DS_WRITE_B64, vt, "store_align8_local">;
878}
879
880let SubtargetPredicate = isGFX7Plus in {
881
882foreach vt = VReg_96.RegTypes in {
883defm : DSWritePat_mc <DS_WRITE_B96, vt, "store_align16_local">;
884}
885
886// For performance reasons restrict this to alignment >= 16 even with
887// unaligned-access-mode. At lower alignments ds_write2_b64 is always a better
888// choice.
889foreach vt = VReg_128.RegTypes in {
890defm : DSWritePat_mc <DS_WRITE_B128, vt, "store_align16_local">;
891}
892
893let SubtargetPredicate = HasUnalignedAccessMode in {
894
895foreach vt = VReg_96.RegTypes in {
896defm : DSWritePat_mc <DS_WRITE_B96, vt, "store_local">;
897}
898
899} // End SubtargetPredicate = HasUnalignedAccessMode
900
901} // End SubtargetPredicate = isGFX7Plus
902
903} // End AddedComplexity = 100
904
905class DSAtomicRetPat<DS_Pseudo inst, ValueType vt, PatFrag frag, bit gds=0> : GCNPat <
906  (frag (DS1Addr1Offset i32:$ptr, i16:$offset), vt:$value),
907  (inst $ptr, getVregSrcForVT<vt>.ret:$value, offset:$offset, (i1 gds))
908>;
909
910multiclass DSAtomicRetPat_mc<DS_Pseudo inst, ValueType vt, string frag> {
911  let OtherPredicates = [LDSRequiresM0Init] in {
912    def : DSAtomicRetPat<inst, vt, !cast<PatFrag>(frag#"_local_m0_"#vt.Size)>;
913  }
914
915  let OtherPredicates = [NotLDSRequiresM0Init] in {
916    def : DSAtomicRetPat<!cast<DS_Pseudo>(!cast<string>(inst)#"_gfx9"), vt,
917                         !cast<PatFrag>(frag#"_local_"#vt.Size)>;
918  }
919
920  def : DSAtomicRetPat<inst, vt, !cast<PatFrag>(frag#"_region_m0_"#vt.Size), 1>;
921}
922
923
924
925class DSAtomicCmpXChg<DS_Pseudo inst, ValueType vt, PatFrag frag, bit gds=0> : GCNPat <
926  (frag (DS1Addr1Offset i32:$ptr, i16:$offset), vt:$cmp, vt:$swap),
927  (inst $ptr, getVregSrcForVT<vt>.ret:$cmp, getVregSrcForVT<vt>.ret:$swap, offset:$offset, (i1 gds))
928>;
929
930multiclass DSAtomicCmpXChg_mc<DS_Pseudo inst, ValueType vt, string frag> {
931  let OtherPredicates = [LDSRequiresM0Init] in {
932    def : DSAtomicCmpXChg<inst, vt, !cast<PatFrag>(frag#"_local_m0_"#vt.Size)>;
933  }
934
935  let OtherPredicates = [NotLDSRequiresM0Init] in {
936    def : DSAtomicCmpXChg<!cast<DS_Pseudo>(!cast<string>(inst)#"_gfx9"), vt,
937                          !cast<PatFrag>(frag#"_local_"#vt.Size)>;
938  }
939
940  def : DSAtomicCmpXChg<inst, vt, !cast<PatFrag>(frag#"_region_m0_"#vt.Size), 1>;
941}
942
943
944
945// 32-bit atomics.
946defm : DSAtomicRetPat_mc<DS_WRXCHG_RTN_B32, i32, "atomic_swap">;
947defm : DSAtomicRetPat_mc<DS_ADD_RTN_U32, i32, "atomic_load_add">;
948defm : DSAtomicRetPat_mc<DS_SUB_RTN_U32, i32, "atomic_load_sub">;
949defm : DSAtomicRetPat_mc<DS_INC_RTN_U32, i32, "atomic_inc">;
950defm : DSAtomicRetPat_mc<DS_DEC_RTN_U32, i32, "atomic_dec">;
951defm : DSAtomicRetPat_mc<DS_AND_RTN_B32, i32, "atomic_load_and">;
952defm : DSAtomicRetPat_mc<DS_OR_RTN_B32, i32, "atomic_load_or">;
953defm : DSAtomicRetPat_mc<DS_XOR_RTN_B32, i32, "atomic_load_xor">;
954defm : DSAtomicRetPat_mc<DS_MIN_RTN_I32, i32, "atomic_load_min">;
955defm : DSAtomicRetPat_mc<DS_MAX_RTN_I32, i32, "atomic_load_max">;
956defm : DSAtomicRetPat_mc<DS_MIN_RTN_U32, i32, "atomic_load_umin">;
957defm : DSAtomicRetPat_mc<DS_MAX_RTN_U32, i32, "atomic_load_umax">;
958defm : DSAtomicCmpXChg_mc<DS_CMPST_RTN_B32, i32, "atomic_cmp_swap">;
959
960let SubtargetPredicate = HasLDSFPAtomics in {
961defm : DSAtomicRetPat_mc<DS_MIN_RTN_F32, f32, "atomic_load_fmin">;
962defm : DSAtomicRetPat_mc<DS_MAX_RTN_F32, f32, "atomic_load_fmax">;
963defm : DSAtomicRetPat_mc<DS_ADD_RTN_F32, f32, "atomic_load_fadd">;
964}
965
966// 64-bit atomics.
967defm : DSAtomicRetPat_mc<DS_WRXCHG_RTN_B64, i64, "atomic_swap">;
968defm : DSAtomicRetPat_mc<DS_ADD_RTN_U64, i64, "atomic_load_add">;
969defm : DSAtomicRetPat_mc<DS_SUB_RTN_U64, i64, "atomic_load_sub">;
970defm : DSAtomicRetPat_mc<DS_INC_RTN_U64, i64, "atomic_inc">;
971defm : DSAtomicRetPat_mc<DS_DEC_RTN_U64, i64, "atomic_dec">;
972defm : DSAtomicRetPat_mc<DS_AND_RTN_B64, i64, "atomic_load_and">;
973defm : DSAtomicRetPat_mc<DS_OR_RTN_B64, i64, "atomic_load_or">;
974defm : DSAtomicRetPat_mc<DS_XOR_RTN_B64, i64, "atomic_load_xor">;
975defm : DSAtomicRetPat_mc<DS_MIN_RTN_I64, i64, "atomic_load_min">;
976defm : DSAtomicRetPat_mc<DS_MAX_RTN_I64, i64, "atomic_load_max">;
977defm : DSAtomicRetPat_mc<DS_MIN_RTN_U64, i64, "atomic_load_umin">;
978defm : DSAtomicRetPat_mc<DS_MAX_RTN_U64, i64, "atomic_load_umax">;
979
980defm : DSAtomicCmpXChg_mc<DS_CMPST_RTN_B64, i64, "atomic_cmp_swap">;
981
982let SubtargetPredicate = isGFX90APlus in {
983def : DSAtomicRetPat<DS_ADD_RTN_F64, f64, atomic_load_fadd_local_64>;
984}
985
986def : Pat <
987  (SIds_ordered_count i32:$value, i16:$offset),
988  (DS_ORDERED_COUNT $value, (as_i16imm $offset))
989>;
990
991//===----------------------------------------------------------------------===//
992// Target-specific instruction encodings.
993//===----------------------------------------------------------------------===//
994
995//===----------------------------------------------------------------------===//
996// Base ENC_DS for GFX6, GFX7, GFX10.
997//===----------------------------------------------------------------------===//
998
999class Base_DS_Real_gfx6_gfx7_gfx10<bits<8> op, DS_Pseudo ps, int ef> :
1000    DS_Real<ps>, SIMCInstr <ps.Mnemonic, ef> {
1001
1002  let Inst{7-0}   = !if(ps.has_offset0, offset0, 0);
1003  let Inst{15-8}  = !if(ps.has_offset1, offset1, 0);
1004  let Inst{17}    = !if(ps.has_gds, gds, ps.gdsValue);
1005  let Inst{25-18} = op;
1006  let Inst{31-26} = 0x36;
1007  let Inst{39-32} = !if(ps.has_addr, addr, !if(ps.has_gws_data0, data0{7-0}, 0));
1008  let Inst{47-40} = !if(ps.has_data0, data0{7-0}, 0);
1009  let Inst{55-48} = !if(ps.has_data1, data1{7-0}, 0);
1010  let Inst{63-56} = !if(ps.has_vdst, vdst{7-0}, 0);
1011}
1012
1013//===----------------------------------------------------------------------===//
1014// GFX10.
1015//===----------------------------------------------------------------------===//
1016
1017let AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10" in {
1018  multiclass DS_Real_gfx10<bits<8> op>  {
1019    def _gfx10 : Base_DS_Real_gfx6_gfx7_gfx10<op, !cast<DS_Pseudo>(NAME),
1020                                              SIEncodingFamily.GFX10>;
1021  }
1022} // End AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10"
1023
1024defm DS_ADD_F32          : DS_Real_gfx10<0x015>;
1025defm DS_ADD_RTN_F32      : DS_Real_gfx10<0x055>;
1026defm DS_ADD_SRC2_F32     : DS_Real_gfx10<0x095>;
1027defm DS_WRITE_B8_D16_HI  : DS_Real_gfx10<0x0a0>;
1028defm DS_WRITE_B16_D16_HI : DS_Real_gfx10<0x0a1>;
1029defm DS_READ_U8_D16      : DS_Real_gfx10<0x0a2>;
1030defm DS_READ_U8_D16_HI   : DS_Real_gfx10<0x0a3>;
1031defm DS_READ_I8_D16      : DS_Real_gfx10<0x0a4>;
1032defm DS_READ_I8_D16_HI   : DS_Real_gfx10<0x0a5>;
1033defm DS_READ_U16_D16     : DS_Real_gfx10<0x0a6>;
1034defm DS_READ_U16_D16_HI  : DS_Real_gfx10<0x0a7>;
1035defm DS_WRITE_ADDTID_B32 : DS_Real_gfx10<0x0b0>;
1036defm DS_READ_ADDTID_B32  : DS_Real_gfx10<0x0b1>;
1037defm DS_PERMUTE_B32      : DS_Real_gfx10<0x0b2>;
1038defm DS_BPERMUTE_B32     : DS_Real_gfx10<0x0b3>;
1039
1040//===----------------------------------------------------------------------===//
1041// GFX7, GFX10.
1042//===----------------------------------------------------------------------===//
1043
1044let AssemblerPredicate = isGFX7Only, DecoderNamespace = "GFX7" in {
1045  multiclass DS_Real_gfx7<bits<8> op> {
1046    def _gfx7 : Base_DS_Real_gfx6_gfx7_gfx10<op, !cast<DS_Pseudo>(NAME),
1047                                             SIEncodingFamily.SI>;
1048  }
1049} // End AssemblerPredicate = isGFX7Only, DecoderNamespace = "GFX7"
1050
1051multiclass DS_Real_gfx7_gfx10<bits<8> op> :
1052  DS_Real_gfx7<op>, DS_Real_gfx10<op>;
1053
1054// FIXME-GFX7: Add tests when upstreaming this part.
1055defm DS_GWS_SEMA_RELEASE_ALL : DS_Real_gfx7_gfx10<0x018>;
1056defm DS_WRAP_RTN_B32         : DS_Real_gfx7_gfx10<0x034>;
1057defm DS_CONDXCHG32_RTN_B64   : DS_Real_gfx7_gfx10<0x07e>;
1058defm DS_WRITE_B96            : DS_Real_gfx7_gfx10<0x0de>;
1059defm DS_WRITE_B128           : DS_Real_gfx7_gfx10<0x0df>;
1060defm DS_READ_B96             : DS_Real_gfx7_gfx10<0x0fe>;
1061defm DS_READ_B128            : DS_Real_gfx7_gfx10<0x0ff>;
1062
1063//===----------------------------------------------------------------------===//
1064// GFX6, GFX7, GFX10.
1065//===----------------------------------------------------------------------===//
1066
1067let AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" in {
1068  multiclass DS_Real_gfx6_gfx7<bits<8> op> {
1069    def _gfx6_gfx7 : Base_DS_Real_gfx6_gfx7_gfx10<op, !cast<DS_Pseudo>(NAME),
1070                                                  SIEncodingFamily.SI>;
1071  }
1072} // End AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7"
1073
1074multiclass DS_Real_gfx6_gfx7_gfx10<bits<8> op> :
1075  DS_Real_gfx6_gfx7<op>, DS_Real_gfx10<op>;
1076
1077defm DS_ADD_U32             : DS_Real_gfx6_gfx7_gfx10<0x000>;
1078defm DS_SUB_U32             : DS_Real_gfx6_gfx7_gfx10<0x001>;
1079defm DS_RSUB_U32            : DS_Real_gfx6_gfx7_gfx10<0x002>;
1080defm DS_INC_U32             : DS_Real_gfx6_gfx7_gfx10<0x003>;
1081defm DS_DEC_U32             : DS_Real_gfx6_gfx7_gfx10<0x004>;
1082defm DS_MIN_I32             : DS_Real_gfx6_gfx7_gfx10<0x005>;
1083defm DS_MAX_I32             : DS_Real_gfx6_gfx7_gfx10<0x006>;
1084defm DS_MIN_U32             : DS_Real_gfx6_gfx7_gfx10<0x007>;
1085defm DS_MAX_U32             : DS_Real_gfx6_gfx7_gfx10<0x008>;
1086defm DS_AND_B32             : DS_Real_gfx6_gfx7_gfx10<0x009>;
1087defm DS_OR_B32              : DS_Real_gfx6_gfx7_gfx10<0x00a>;
1088defm DS_XOR_B32             : DS_Real_gfx6_gfx7_gfx10<0x00b>;
1089defm DS_MSKOR_B32           : DS_Real_gfx6_gfx7_gfx10<0x00c>;
1090defm DS_WRITE_B32           : DS_Real_gfx6_gfx7_gfx10<0x00d>;
1091defm DS_WRITE2_B32          : DS_Real_gfx6_gfx7_gfx10<0x00e>;
1092defm DS_WRITE2ST64_B32      : DS_Real_gfx6_gfx7_gfx10<0x00f>;
1093defm DS_CMPST_B32           : DS_Real_gfx6_gfx7_gfx10<0x010>;
1094defm DS_CMPST_F32           : DS_Real_gfx6_gfx7_gfx10<0x011>;
1095defm DS_MIN_F32             : DS_Real_gfx6_gfx7_gfx10<0x012>;
1096defm DS_MAX_F32             : DS_Real_gfx6_gfx7_gfx10<0x013>;
1097defm DS_NOP                 : DS_Real_gfx6_gfx7_gfx10<0x014>;
1098defm DS_GWS_INIT            : DS_Real_gfx6_gfx7_gfx10<0x019>;
1099defm DS_GWS_SEMA_V          : DS_Real_gfx6_gfx7_gfx10<0x01a>;
1100defm DS_GWS_SEMA_BR         : DS_Real_gfx6_gfx7_gfx10<0x01b>;
1101defm DS_GWS_SEMA_P          : DS_Real_gfx6_gfx7_gfx10<0x01c>;
1102defm DS_GWS_BARRIER         : DS_Real_gfx6_gfx7_gfx10<0x01d>;
1103defm DS_WRITE_B8            : DS_Real_gfx6_gfx7_gfx10<0x01e>;
1104defm DS_WRITE_B16           : DS_Real_gfx6_gfx7_gfx10<0x01f>;
1105defm DS_ADD_RTN_U32         : DS_Real_gfx6_gfx7_gfx10<0x020>;
1106defm DS_SUB_RTN_U32         : DS_Real_gfx6_gfx7_gfx10<0x021>;
1107defm DS_RSUB_RTN_U32        : DS_Real_gfx6_gfx7_gfx10<0x022>;
1108defm DS_INC_RTN_U32         : DS_Real_gfx6_gfx7_gfx10<0x023>;
1109defm DS_DEC_RTN_U32         : DS_Real_gfx6_gfx7_gfx10<0x024>;
1110defm DS_MIN_RTN_I32         : DS_Real_gfx6_gfx7_gfx10<0x025>;
1111defm DS_MAX_RTN_I32         : DS_Real_gfx6_gfx7_gfx10<0x026>;
1112defm DS_MIN_RTN_U32         : DS_Real_gfx6_gfx7_gfx10<0x027>;
1113defm DS_MAX_RTN_U32         : DS_Real_gfx6_gfx7_gfx10<0x028>;
1114defm DS_AND_RTN_B32         : DS_Real_gfx6_gfx7_gfx10<0x029>;
1115defm DS_OR_RTN_B32          : DS_Real_gfx6_gfx7_gfx10<0x02a>;
1116defm DS_XOR_RTN_B32         : DS_Real_gfx6_gfx7_gfx10<0x02b>;
1117defm DS_MSKOR_RTN_B32       : DS_Real_gfx6_gfx7_gfx10<0x02c>;
1118defm DS_WRXCHG_RTN_B32      : DS_Real_gfx6_gfx7_gfx10<0x02d>;
1119defm DS_WRXCHG2_RTN_B32     : DS_Real_gfx6_gfx7_gfx10<0x02e>;
1120defm DS_WRXCHG2ST64_RTN_B32 : DS_Real_gfx6_gfx7_gfx10<0x02f>;
1121defm DS_CMPST_RTN_B32       : DS_Real_gfx6_gfx7_gfx10<0x030>;
1122defm DS_CMPST_RTN_F32       : DS_Real_gfx6_gfx7_gfx10<0x031>;
1123defm DS_MIN_RTN_F32         : DS_Real_gfx6_gfx7_gfx10<0x032>;
1124defm DS_MAX_RTN_F32         : DS_Real_gfx6_gfx7_gfx10<0x033>;
1125defm DS_SWIZZLE_B32         : DS_Real_gfx6_gfx7_gfx10<0x035>;
1126defm DS_READ_B32            : DS_Real_gfx6_gfx7_gfx10<0x036>;
1127defm DS_READ2_B32           : DS_Real_gfx6_gfx7_gfx10<0x037>;
1128defm DS_READ2ST64_B32       : DS_Real_gfx6_gfx7_gfx10<0x038>;
1129defm DS_READ_I8             : DS_Real_gfx6_gfx7_gfx10<0x039>;
1130defm DS_READ_U8             : DS_Real_gfx6_gfx7_gfx10<0x03a>;
1131defm DS_READ_I16            : DS_Real_gfx6_gfx7_gfx10<0x03b>;
1132defm DS_READ_U16            : DS_Real_gfx6_gfx7_gfx10<0x03c>;
1133defm DS_CONSUME             : DS_Real_gfx6_gfx7_gfx10<0x03d>;
1134defm DS_APPEND              : DS_Real_gfx6_gfx7_gfx10<0x03e>;
1135defm DS_ORDERED_COUNT       : DS_Real_gfx6_gfx7_gfx10<0x03f>;
1136defm DS_ADD_U64             : DS_Real_gfx6_gfx7_gfx10<0x040>;
1137defm DS_SUB_U64             : DS_Real_gfx6_gfx7_gfx10<0x041>;
1138defm DS_RSUB_U64            : DS_Real_gfx6_gfx7_gfx10<0x042>;
1139defm DS_INC_U64             : DS_Real_gfx6_gfx7_gfx10<0x043>;
1140defm DS_DEC_U64             : DS_Real_gfx6_gfx7_gfx10<0x044>;
1141defm DS_MIN_I64             : DS_Real_gfx6_gfx7_gfx10<0x045>;
1142defm DS_MAX_I64             : DS_Real_gfx6_gfx7_gfx10<0x046>;
1143defm DS_MIN_U64             : DS_Real_gfx6_gfx7_gfx10<0x047>;
1144defm DS_MAX_U64             : DS_Real_gfx6_gfx7_gfx10<0x048>;
1145defm DS_AND_B64             : DS_Real_gfx6_gfx7_gfx10<0x049>;
1146defm DS_OR_B64              : DS_Real_gfx6_gfx7_gfx10<0x04a>;
1147defm DS_XOR_B64             : DS_Real_gfx6_gfx7_gfx10<0x04b>;
1148defm DS_MSKOR_B64           : DS_Real_gfx6_gfx7_gfx10<0x04c>;
1149defm DS_WRITE_B64           : DS_Real_gfx6_gfx7_gfx10<0x04d>;
1150defm DS_WRITE2_B64          : DS_Real_gfx6_gfx7_gfx10<0x04e>;
1151defm DS_WRITE2ST64_B64      : DS_Real_gfx6_gfx7_gfx10<0x04f>;
1152defm DS_CMPST_B64           : DS_Real_gfx6_gfx7_gfx10<0x050>;
1153defm DS_CMPST_F64           : DS_Real_gfx6_gfx7_gfx10<0x051>;
1154defm DS_MIN_F64             : DS_Real_gfx6_gfx7_gfx10<0x052>;
1155defm DS_MAX_F64             : DS_Real_gfx6_gfx7_gfx10<0x053>;
1156defm DS_ADD_RTN_U64         : DS_Real_gfx6_gfx7_gfx10<0x060>;
1157defm DS_SUB_RTN_U64         : DS_Real_gfx6_gfx7_gfx10<0x061>;
1158defm DS_RSUB_RTN_U64        : DS_Real_gfx6_gfx7_gfx10<0x062>;
1159defm DS_INC_RTN_U64         : DS_Real_gfx6_gfx7_gfx10<0x063>;
1160defm DS_DEC_RTN_U64         : DS_Real_gfx6_gfx7_gfx10<0x064>;
1161defm DS_MIN_RTN_I64         : DS_Real_gfx6_gfx7_gfx10<0x065>;
1162defm DS_MAX_RTN_I64         : DS_Real_gfx6_gfx7_gfx10<0x066>;
1163defm DS_MIN_RTN_U64         : DS_Real_gfx6_gfx7_gfx10<0x067>;
1164defm DS_MAX_RTN_U64         : DS_Real_gfx6_gfx7_gfx10<0x068>;
1165defm DS_AND_RTN_B64         : DS_Real_gfx6_gfx7_gfx10<0x069>;
1166defm DS_OR_RTN_B64          : DS_Real_gfx6_gfx7_gfx10<0x06a>;
1167defm DS_XOR_RTN_B64         : DS_Real_gfx6_gfx7_gfx10<0x06b>;
1168defm DS_MSKOR_RTN_B64       : DS_Real_gfx6_gfx7_gfx10<0x06c>;
1169defm DS_WRXCHG_RTN_B64      : DS_Real_gfx6_gfx7_gfx10<0x06d>;
1170defm DS_WRXCHG2_RTN_B64     : DS_Real_gfx6_gfx7_gfx10<0x06e>;
1171defm DS_WRXCHG2ST64_RTN_B64 : DS_Real_gfx6_gfx7_gfx10<0x06f>;
1172defm DS_CMPST_RTN_B64       : DS_Real_gfx6_gfx7_gfx10<0x070>;
1173defm DS_CMPST_RTN_F64       : DS_Real_gfx6_gfx7_gfx10<0x071>;
1174defm DS_MIN_RTN_F64         : DS_Real_gfx6_gfx7_gfx10<0x072>;
1175defm DS_MAX_RTN_F64         : DS_Real_gfx6_gfx7_gfx10<0x073>;
1176defm DS_READ_B64            : DS_Real_gfx6_gfx7_gfx10<0x076>;
1177defm DS_READ2_B64           : DS_Real_gfx6_gfx7_gfx10<0x077>;
1178defm DS_READ2ST64_B64       : DS_Real_gfx6_gfx7_gfx10<0x078>;
1179defm DS_ADD_SRC2_U32        : DS_Real_gfx6_gfx7_gfx10<0x080>;
1180defm DS_SUB_SRC2_U32        : DS_Real_gfx6_gfx7_gfx10<0x081>;
1181defm DS_RSUB_SRC2_U32       : DS_Real_gfx6_gfx7_gfx10<0x082>;
1182defm DS_INC_SRC2_U32        : DS_Real_gfx6_gfx7_gfx10<0x083>;
1183defm DS_DEC_SRC2_U32        : DS_Real_gfx6_gfx7_gfx10<0x084>;
1184defm DS_MIN_SRC2_I32        : DS_Real_gfx6_gfx7_gfx10<0x085>;
1185defm DS_MAX_SRC2_I32        : DS_Real_gfx6_gfx7_gfx10<0x086>;
1186defm DS_MIN_SRC2_U32        : DS_Real_gfx6_gfx7_gfx10<0x087>;
1187defm DS_MAX_SRC2_U32        : DS_Real_gfx6_gfx7_gfx10<0x088>;
1188defm DS_AND_SRC2_B32        : DS_Real_gfx6_gfx7_gfx10<0x089>;
1189defm DS_OR_SRC2_B32         : DS_Real_gfx6_gfx7_gfx10<0x08a>;
1190defm DS_XOR_SRC2_B32        : DS_Real_gfx6_gfx7_gfx10<0x08b>;
1191defm DS_WRITE_SRC2_B32      : DS_Real_gfx6_gfx7_gfx10<0x08d>;
1192defm DS_MIN_SRC2_F32        : DS_Real_gfx6_gfx7_gfx10<0x092>;
1193defm DS_MAX_SRC2_F32        : DS_Real_gfx6_gfx7_gfx10<0x093>;
1194defm DS_ADD_SRC2_U64        : DS_Real_gfx6_gfx7_gfx10<0x0c0>;
1195defm DS_SUB_SRC2_U64        : DS_Real_gfx6_gfx7_gfx10<0x0c1>;
1196defm DS_RSUB_SRC2_U64       : DS_Real_gfx6_gfx7_gfx10<0x0c2>;
1197defm DS_INC_SRC2_U64        : DS_Real_gfx6_gfx7_gfx10<0x0c3>;
1198defm DS_DEC_SRC2_U64        : DS_Real_gfx6_gfx7_gfx10<0x0c4>;
1199defm DS_MIN_SRC2_I64        : DS_Real_gfx6_gfx7_gfx10<0x0c5>;
1200defm DS_MAX_SRC2_I64        : DS_Real_gfx6_gfx7_gfx10<0x0c6>;
1201defm DS_MIN_SRC2_U64        : DS_Real_gfx6_gfx7_gfx10<0x0c7>;
1202defm DS_MAX_SRC2_U64        : DS_Real_gfx6_gfx7_gfx10<0x0c8>;
1203defm DS_AND_SRC2_B64        : DS_Real_gfx6_gfx7_gfx10<0x0c9>;
1204defm DS_OR_SRC2_B64         : DS_Real_gfx6_gfx7_gfx10<0x0ca>;
1205defm DS_XOR_SRC2_B64        : DS_Real_gfx6_gfx7_gfx10<0x0cb>;
1206defm DS_WRITE_SRC2_B64      : DS_Real_gfx6_gfx7_gfx10<0x0cd>;
1207defm DS_MIN_SRC2_F64        : DS_Real_gfx6_gfx7_gfx10<0x0d2>;
1208defm DS_MAX_SRC2_F64        : DS_Real_gfx6_gfx7_gfx10<0x0d3>;
1209
1210//===----------------------------------------------------------------------===//
1211// GFX8, GFX9 (VI).
1212//===----------------------------------------------------------------------===//
1213
1214class DS_Real_vi <bits<8> op, DS_Pseudo ds> :
1215  DS_Real <ds>,
1216  SIMCInstr <ds.Mnemonic, SIEncodingFamily.VI> {
1217  let AssemblerPredicate = isGFX8GFX9;
1218  let DecoderNamespace = "GFX8";
1219
1220  // encoding
1221  let Inst{7-0}   = !if(ds.has_offset0, offset0, 0);
1222  let Inst{15-8}  = !if(ds.has_offset1, offset1, 0);
1223  let Inst{16}    = !if(ds.has_gds, gds, ds.gdsValue);
1224  let Inst{24-17} = op;
1225  let Inst{25}    = acc;
1226  let Inst{31-26} = 0x36; // ds prefix
1227  let Inst{39-32} = !if(ds.has_addr, addr, !if(ds.has_gws_data0, data0{7-0}, 0));
1228  let Inst{47-40} = !if(ds.has_data0, data0{7-0}, 0);
1229  let Inst{55-48} = !if(ds.has_data1, data1{7-0}, 0);
1230  let Inst{63-56} = !if(ds.has_vdst, vdst{7-0}, 0);
1231}
1232
1233def DS_ADD_U32_vi         : DS_Real_vi<0x0,  DS_ADD_U32>;
1234def DS_SUB_U32_vi         : DS_Real_vi<0x1,  DS_SUB_U32>;
1235def DS_RSUB_U32_vi        : DS_Real_vi<0x2,  DS_RSUB_U32>;
1236def DS_INC_U32_vi         : DS_Real_vi<0x3,  DS_INC_U32>;
1237def DS_DEC_U32_vi         : DS_Real_vi<0x4,  DS_DEC_U32>;
1238def DS_MIN_I32_vi         : DS_Real_vi<0x5,  DS_MIN_I32>;
1239def DS_MAX_I32_vi         : DS_Real_vi<0x6,  DS_MAX_I32>;
1240def DS_MIN_U32_vi         : DS_Real_vi<0x7,  DS_MIN_U32>;
1241def DS_MAX_U32_vi         : DS_Real_vi<0x8,  DS_MAX_U32>;
1242def DS_AND_B32_vi         : DS_Real_vi<0x9,  DS_AND_B32>;
1243def DS_OR_B32_vi          : DS_Real_vi<0xa,  DS_OR_B32>;
1244def DS_XOR_B32_vi         : DS_Real_vi<0xb,  DS_XOR_B32>;
1245def DS_MSKOR_B32_vi       : DS_Real_vi<0xc,  DS_MSKOR_B32>;
1246def DS_WRITE_B32_vi       : DS_Real_vi<0xd,  DS_WRITE_B32>;
1247def DS_WRITE2_B32_vi      : DS_Real_vi<0xe,  DS_WRITE2_B32>;
1248def DS_WRITE2ST64_B32_vi  : DS_Real_vi<0xf,  DS_WRITE2ST64_B32>;
1249def DS_CMPST_B32_vi       : DS_Real_vi<0x10, DS_CMPST_B32>;
1250def DS_CMPST_F32_vi       : DS_Real_vi<0x11, DS_CMPST_F32>;
1251def DS_MIN_F32_vi         : DS_Real_vi<0x12, DS_MIN_F32>;
1252def DS_MAX_F32_vi         : DS_Real_vi<0x13, DS_MAX_F32>;
1253def DS_NOP_vi             : DS_Real_vi<0x14, DS_NOP>;
1254def DS_ADD_F32_vi         : DS_Real_vi<0x15, DS_ADD_F32>;
1255def DS_GWS_INIT_vi        : DS_Real_vi<0x99, DS_GWS_INIT>;
1256def DS_GWS_SEMA_V_vi      : DS_Real_vi<0x9a, DS_GWS_SEMA_V>;
1257def DS_GWS_SEMA_BR_vi     : DS_Real_vi<0x9b, DS_GWS_SEMA_BR>;
1258def DS_GWS_SEMA_P_vi      : DS_Real_vi<0x9c, DS_GWS_SEMA_P>;
1259def DS_GWS_BARRIER_vi     : DS_Real_vi<0x9d, DS_GWS_BARRIER>;
1260def DS_WRITE_ADDTID_B32_vi : DS_Real_vi<0x1d, DS_WRITE_ADDTID_B32>;
1261def DS_WRITE_B8_vi        : DS_Real_vi<0x1e, DS_WRITE_B8>;
1262def DS_WRITE_B16_vi       : DS_Real_vi<0x1f, DS_WRITE_B16>;
1263def DS_ADD_RTN_U32_vi     : DS_Real_vi<0x20, DS_ADD_RTN_U32>;
1264def DS_SUB_RTN_U32_vi     : DS_Real_vi<0x21, DS_SUB_RTN_U32>;
1265def DS_RSUB_RTN_U32_vi    : DS_Real_vi<0x22, DS_RSUB_RTN_U32>;
1266def DS_INC_RTN_U32_vi     : DS_Real_vi<0x23, DS_INC_RTN_U32>;
1267def DS_DEC_RTN_U32_vi     : DS_Real_vi<0x24, DS_DEC_RTN_U32>;
1268def DS_MIN_RTN_I32_vi     : DS_Real_vi<0x25, DS_MIN_RTN_I32>;
1269def DS_MAX_RTN_I32_vi     : DS_Real_vi<0x26, DS_MAX_RTN_I32>;
1270def DS_MIN_RTN_U32_vi     : DS_Real_vi<0x27, DS_MIN_RTN_U32>;
1271def DS_MAX_RTN_U32_vi     : DS_Real_vi<0x28, DS_MAX_RTN_U32>;
1272def DS_AND_RTN_B32_vi     : DS_Real_vi<0x29, DS_AND_RTN_B32>;
1273def DS_OR_RTN_B32_vi      : DS_Real_vi<0x2a, DS_OR_RTN_B32>;
1274def DS_XOR_RTN_B32_vi     : DS_Real_vi<0x2b, DS_XOR_RTN_B32>;
1275def DS_MSKOR_RTN_B32_vi   : DS_Real_vi<0x2c, DS_MSKOR_RTN_B32>;
1276def DS_WRXCHG_RTN_B32_vi  : DS_Real_vi<0x2d, DS_WRXCHG_RTN_B32>;
1277def DS_WRXCHG2_RTN_B32_vi : DS_Real_vi<0x2e, DS_WRXCHG2_RTN_B32>;
1278def DS_WRXCHG2ST64_RTN_B32_vi : DS_Real_vi<0x2f, DS_WRXCHG2ST64_RTN_B32>;
1279def DS_CMPST_RTN_B32_vi   : DS_Real_vi<0x30, DS_CMPST_RTN_B32>;
1280def DS_CMPST_RTN_F32_vi   : DS_Real_vi<0x31, DS_CMPST_RTN_F32>;
1281def DS_MIN_RTN_F32_vi     : DS_Real_vi<0x32, DS_MIN_RTN_F32>;
1282def DS_MAX_RTN_F32_vi     : DS_Real_vi<0x33, DS_MAX_RTN_F32>;
1283def DS_WRAP_RTN_B32_vi    : DS_Real_vi<0x34, DS_WRAP_RTN_B32>;
1284def DS_ADD_RTN_F32_vi     : DS_Real_vi<0x35, DS_ADD_RTN_F32>;
1285def DS_READ_B32_vi        : DS_Real_vi<0x36, DS_READ_B32>;
1286def DS_READ2_B32_vi       : DS_Real_vi<0x37, DS_READ2_B32>;
1287def DS_READ2ST64_B32_vi   : DS_Real_vi<0x38, DS_READ2ST64_B32>;
1288def DS_READ_I8_vi         : DS_Real_vi<0x39, DS_READ_I8>;
1289def DS_READ_U8_vi         : DS_Real_vi<0x3a, DS_READ_U8>;
1290def DS_READ_I16_vi        : DS_Real_vi<0x3b, DS_READ_I16>;
1291def DS_READ_U16_vi        : DS_Real_vi<0x3c, DS_READ_U16>;
1292def DS_READ_ADDTID_B32_vi : DS_Real_vi<0xb6, DS_READ_ADDTID_B32>;
1293def DS_CONSUME_vi         : DS_Real_vi<0xbd, DS_CONSUME>;
1294def DS_APPEND_vi          : DS_Real_vi<0xbe, DS_APPEND>;
1295def DS_ORDERED_COUNT_vi   : DS_Real_vi<0xbf, DS_ORDERED_COUNT>;
1296def DS_SWIZZLE_B32_vi     : DS_Real_vi<0x3d, DS_SWIZZLE_B32>;
1297def DS_PERMUTE_B32_vi     : DS_Real_vi<0x3e, DS_PERMUTE_B32>;
1298def DS_BPERMUTE_B32_vi    : DS_Real_vi<0x3f, DS_BPERMUTE_B32>;
1299
1300def DS_ADD_U64_vi         : DS_Real_vi<0x40, DS_ADD_U64>;
1301def DS_SUB_U64_vi         : DS_Real_vi<0x41, DS_SUB_U64>;
1302def DS_RSUB_U64_vi        : DS_Real_vi<0x42, DS_RSUB_U64>;
1303def DS_INC_U64_vi         : DS_Real_vi<0x43, DS_INC_U64>;
1304def DS_DEC_U64_vi         : DS_Real_vi<0x44, DS_DEC_U64>;
1305def DS_MIN_I64_vi         : DS_Real_vi<0x45, DS_MIN_I64>;
1306def DS_MAX_I64_vi         : DS_Real_vi<0x46, DS_MAX_I64>;
1307def DS_MIN_U64_vi         : DS_Real_vi<0x47, DS_MIN_U64>;
1308def DS_MAX_U64_vi         : DS_Real_vi<0x48, DS_MAX_U64>;
1309def DS_AND_B64_vi         : DS_Real_vi<0x49, DS_AND_B64>;
1310def DS_OR_B64_vi          : DS_Real_vi<0x4a, DS_OR_B64>;
1311def DS_XOR_B64_vi         : DS_Real_vi<0x4b, DS_XOR_B64>;
1312def DS_MSKOR_B64_vi       : DS_Real_vi<0x4c, DS_MSKOR_B64>;
1313def DS_WRITE_B64_vi       : DS_Real_vi<0x4d, DS_WRITE_B64>;
1314def DS_WRITE2_B64_vi      : DS_Real_vi<0x4E, DS_WRITE2_B64>;
1315def DS_WRITE2ST64_B64_vi  : DS_Real_vi<0x4f, DS_WRITE2ST64_B64>;
1316def DS_CMPST_B64_vi       : DS_Real_vi<0x50, DS_CMPST_B64>;
1317def DS_CMPST_F64_vi       : DS_Real_vi<0x51, DS_CMPST_F64>;
1318def DS_MIN_F64_vi         : DS_Real_vi<0x52, DS_MIN_F64>;
1319def DS_MAX_F64_vi         : DS_Real_vi<0x53, DS_MAX_F64>;
1320
1321def DS_WRITE_B8_D16_HI_vi  : DS_Real_vi<0x54, DS_WRITE_B8_D16_HI>;
1322def DS_WRITE_B16_D16_HI_vi : DS_Real_vi<0x55, DS_WRITE_B16_D16_HI>;
1323
1324def DS_READ_U8_D16_vi     : DS_Real_vi<0x56, DS_READ_U8_D16>;
1325def DS_READ_U8_D16_HI_vi  : DS_Real_vi<0x57, DS_READ_U8_D16_HI>;
1326def DS_READ_I8_D16_vi     : DS_Real_vi<0x58, DS_READ_I8_D16>;
1327def DS_READ_I8_D16_HI_vi  : DS_Real_vi<0x59, DS_READ_I8_D16_HI>;
1328def DS_READ_U16_D16_vi    : DS_Real_vi<0x5a, DS_READ_U16_D16>;
1329def DS_READ_U16_D16_HI_vi : DS_Real_vi<0x5b, DS_READ_U16_D16_HI>;
1330
1331def DS_ADD_RTN_U64_vi     : DS_Real_vi<0x60, DS_ADD_RTN_U64>;
1332def DS_SUB_RTN_U64_vi     : DS_Real_vi<0x61, DS_SUB_RTN_U64>;
1333def DS_RSUB_RTN_U64_vi    : DS_Real_vi<0x62, DS_RSUB_RTN_U64>;
1334def DS_INC_RTN_U64_vi     : DS_Real_vi<0x63, DS_INC_RTN_U64>;
1335def DS_DEC_RTN_U64_vi     : DS_Real_vi<0x64, DS_DEC_RTN_U64>;
1336def DS_MIN_RTN_I64_vi     : DS_Real_vi<0x65, DS_MIN_RTN_I64>;
1337def DS_MAX_RTN_I64_vi     : DS_Real_vi<0x66, DS_MAX_RTN_I64>;
1338def DS_MIN_RTN_U64_vi     : DS_Real_vi<0x67, DS_MIN_RTN_U64>;
1339def DS_MAX_RTN_U64_vi     : DS_Real_vi<0x68, DS_MAX_RTN_U64>;
1340def DS_AND_RTN_B64_vi     : DS_Real_vi<0x69, DS_AND_RTN_B64>;
1341def DS_OR_RTN_B64_vi      : DS_Real_vi<0x6a, DS_OR_RTN_B64>;
1342def DS_XOR_RTN_B64_vi     : DS_Real_vi<0x6b, DS_XOR_RTN_B64>;
1343def DS_MSKOR_RTN_B64_vi   : DS_Real_vi<0x6c, DS_MSKOR_RTN_B64>;
1344def DS_WRXCHG_RTN_B64_vi  : DS_Real_vi<0x6d, DS_WRXCHG_RTN_B64>;
1345def DS_WRXCHG2_RTN_B64_vi : DS_Real_vi<0x6e, DS_WRXCHG2_RTN_B64>;
1346def DS_WRXCHG2ST64_RTN_B64_vi : DS_Real_vi<0x6f, DS_WRXCHG2ST64_RTN_B64>;
1347def DS_CONDXCHG32_RTN_B64_vi   : DS_Real_vi<0x7e, DS_CONDXCHG32_RTN_B64>;
1348def DS_GWS_SEMA_RELEASE_ALL_vi : DS_Real_vi<0x98, DS_GWS_SEMA_RELEASE_ALL>;
1349def DS_CMPST_RTN_B64_vi   : DS_Real_vi<0x70, DS_CMPST_RTN_B64>;
1350def DS_CMPST_RTN_F64_vi   : DS_Real_vi<0x71, DS_CMPST_RTN_F64>;
1351def DS_MIN_RTN_F64_vi     : DS_Real_vi<0x72, DS_MIN_RTN_F64>;
1352def DS_MAX_RTN_F64_vi     : DS_Real_vi<0x73, DS_MAX_RTN_F64>;
1353
1354def DS_READ_B64_vi        : DS_Real_vi<0x76, DS_READ_B64>;
1355def DS_READ2_B64_vi       : DS_Real_vi<0x77, DS_READ2_B64>;
1356def DS_READ2ST64_B64_vi   : DS_Real_vi<0x78, DS_READ2ST64_B64>;
1357
1358def DS_ADD_SRC2_U32_vi    : DS_Real_vi<0x80, DS_ADD_SRC2_U32>;
1359def DS_SUB_SRC2_U32_vi    : DS_Real_vi<0x81, DS_SUB_SRC2_U32>;
1360def DS_RSUB_SRC2_U32_vi   : DS_Real_vi<0x82, DS_RSUB_SRC2_U32>;
1361def DS_INC_SRC2_U32_vi    : DS_Real_vi<0x83, DS_INC_SRC2_U32>;
1362def DS_DEC_SRC2_U32_vi    : DS_Real_vi<0x84, DS_DEC_SRC2_U32>;
1363def DS_MIN_SRC2_I32_vi    : DS_Real_vi<0x85, DS_MIN_SRC2_I32>;
1364def DS_MAX_SRC2_I32_vi    : DS_Real_vi<0x86, DS_MAX_SRC2_I32>;
1365def DS_MIN_SRC2_U32_vi    : DS_Real_vi<0x87, DS_MIN_SRC2_U32>;
1366def DS_MAX_SRC2_U32_vi    : DS_Real_vi<0x88, DS_MAX_SRC2_U32>;
1367def DS_AND_SRC2_B32_vi    : DS_Real_vi<0x89, DS_AND_SRC2_B32>;
1368def DS_OR_SRC2_B32_vi     : DS_Real_vi<0x8a, DS_OR_SRC2_B32>;
1369def DS_XOR_SRC2_B32_vi    : DS_Real_vi<0x8b, DS_XOR_SRC2_B32>;
1370def DS_WRITE_SRC2_B32_vi  : DS_Real_vi<0x8d, DS_WRITE_SRC2_B32>;
1371def DS_MIN_SRC2_F32_vi    : DS_Real_vi<0x92, DS_MIN_SRC2_F32>;
1372def DS_MAX_SRC2_F32_vi    : DS_Real_vi<0x93, DS_MAX_SRC2_F32>;
1373def DS_ADD_SRC2_F32_vi    : DS_Real_vi<0x95, DS_ADD_SRC2_F32>;
1374def DS_ADD_SRC2_U64_vi    : DS_Real_vi<0xc0, DS_ADD_SRC2_U64>;
1375def DS_SUB_SRC2_U64_vi    : DS_Real_vi<0xc1, DS_SUB_SRC2_U64>;
1376def DS_RSUB_SRC2_U64_vi   : DS_Real_vi<0xc2, DS_RSUB_SRC2_U64>;
1377def DS_INC_SRC2_U64_vi    : DS_Real_vi<0xc3, DS_INC_SRC2_U64>;
1378def DS_DEC_SRC2_U64_vi    : DS_Real_vi<0xc4, DS_DEC_SRC2_U64>;
1379def DS_MIN_SRC2_I64_vi    : DS_Real_vi<0xc5, DS_MIN_SRC2_I64>;
1380def DS_MAX_SRC2_I64_vi    : DS_Real_vi<0xc6, DS_MAX_SRC2_I64>;
1381def DS_MIN_SRC2_U64_vi    : DS_Real_vi<0xc7, DS_MIN_SRC2_U64>;
1382def DS_MAX_SRC2_U64_vi    : DS_Real_vi<0xc8, DS_MAX_SRC2_U64>;
1383def DS_AND_SRC2_B64_vi    : DS_Real_vi<0xc9, DS_AND_SRC2_B64>;
1384def DS_OR_SRC2_B64_vi     : DS_Real_vi<0xca, DS_OR_SRC2_B64>;
1385def DS_XOR_SRC2_B64_vi    : DS_Real_vi<0xcb, DS_XOR_SRC2_B64>;
1386def DS_WRITE_SRC2_B64_vi  : DS_Real_vi<0xcd, DS_WRITE_SRC2_B64>;
1387def DS_MIN_SRC2_F64_vi    : DS_Real_vi<0xd2, DS_MIN_SRC2_F64>;
1388def DS_MAX_SRC2_F64_vi    : DS_Real_vi<0xd3, DS_MAX_SRC2_F64>;
1389def DS_WRITE_B96_vi       : DS_Real_vi<0xde, DS_WRITE_B96>;
1390def DS_WRITE_B128_vi      : DS_Real_vi<0xdf, DS_WRITE_B128>;
1391def DS_READ_B96_vi        : DS_Real_vi<0xfe, DS_READ_B96>;
1392def DS_READ_B128_vi       : DS_Real_vi<0xff, DS_READ_B128>;
1393
1394let SubtargetPredicate = isGFX90APlus in {
1395  def DS_ADD_F64_vi     : DS_Real_vi<0x5c, DS_ADD_F64>;
1396  def DS_ADD_RTN_F64_vi : DS_Real_vi<0x7c, DS_ADD_RTN_F64>;
1397} // End SubtargetPredicate = isGFX90APlus
1398