1//===-- DSInstructions.td - DS Instruction Defintions ---------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10class DS_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> pattern=[]> :
11  InstSI <outs, ins, "", pattern>,
12  SIMCInstr <opName, SIEncodingFamily.NONE> {
13
14  let SubtargetPredicate = isGCN;
15
16  let LGKM_CNT = 1;
17  let DS = 1;
18  let Size = 8;
19  let UseNamedOperandTable = 1;
20  let Uses = [M0, EXEC];
21
22  // Most instruction load and store data, so set this as the default.
23  let mayLoad = 1;
24  let mayStore = 1;
25
26  let hasSideEffects = 0;
27  let SchedRW = [WriteLDS];
28
29  let isPseudo = 1;
30  let isCodeGenOnly = 1;
31
32  let AsmMatchConverter = "cvtDS";
33
34  string Mnemonic = opName;
35  string AsmOperands = asmOps;
36
37  // Well these bits a kind of hack because it would be more natural
38  // to test "outs" and "ins" dags for the presence of particular operands
39  bits<1> has_vdst = 1;
40  bits<1> has_addr = 1;
41  bits<1> has_data0 = 1;
42  bits<1> has_data1 = 1;
43
44  bits<1> has_offset  = 1; // has "offset" that should be split to offset0,1
45  bits<1> has_offset0 = 1;
46  bits<1> has_offset1 = 1;
47
48  bits<1> has_gds = 1;
49  bits<1> gdsValue = 0; // if has_gds == 0 set gds to this value
50}
51
52class DS_Real <DS_Pseudo ds> :
53  InstSI <ds.OutOperandList, ds.InOperandList, ds.Mnemonic # " " # ds.AsmOperands, []>,
54  Enc64 {
55
56  let isPseudo = 0;
57  let isCodeGenOnly = 0;
58
59  // copy relevant pseudo op flags
60  let SubtargetPredicate = ds.SubtargetPredicate;
61  let AsmMatchConverter  = ds.AsmMatchConverter;
62
63  // encoding fields
64  bits<8> vdst;
65  bits<1> gds;
66  bits<8> addr;
67  bits<8> data0;
68  bits<8> data1;
69  bits<8> offset0;
70  bits<8> offset1;
71
72  bits<16> offset;
73  let offset0 = !if(ds.has_offset, offset{7-0}, ?);
74  let offset1 = !if(ds.has_offset, offset{15-8}, ?);
75}
76
77
78// DS Pseudo instructions
79
80class DS_1A1D_NORET<string opName, RegisterClass rc = VGPR_32>
81: DS_Pseudo<opName,
82  (outs),
83  (ins VGPR_32:$addr, rc:$data0, offset:$offset, gds:$gds),
84  "$addr, $data0$offset$gds">,
85  AtomicNoRet<opName, 0> {
86
87  let has_data1 = 0;
88  let has_vdst = 0;
89}
90
91class DS_1A_Off8_NORET<string opName> : DS_Pseudo<opName,
92  (outs),
93  (ins VGPR_32:$addr, offset0:$offset0, offset1:$offset1, gds:$gds),
94  "$addr $offset0$offset1$gds"> {
95
96  let has_data0 = 0;
97  let has_data1 = 0;
98  let has_vdst  = 0;
99  let has_offset = 0;
100  let AsmMatchConverter = "cvtDSOffset01";
101}
102
103class DS_1A2D_NORET<string opName, RegisterClass rc = VGPR_32>
104: DS_Pseudo<opName,
105  (outs),
106  (ins VGPR_32:$addr, rc:$data0, rc:$data1, offset:$offset, gds:$gds),
107  "$addr, $data0, $data1"#"$offset"#"$gds">,
108  AtomicNoRet<opName, 0> {
109
110  let has_vdst = 0;
111}
112
113class DS_1A2D_Off8_NORET <string opName, RegisterClass rc = VGPR_32>
114: DS_Pseudo<opName,
115  (outs),
116  (ins VGPR_32:$addr, rc:$data0, rc:$data1,
117       offset0:$offset0, offset1:$offset1, gds:$gds),
118  "$addr, $data0, $data1$offset0$offset1$gds"> {
119
120  let has_vdst = 0;
121  let has_offset = 0;
122  let AsmMatchConverter = "cvtDSOffset01";
123}
124
125class DS_1A1D_RET <string opName, RegisterClass rc = VGPR_32>
126: DS_Pseudo<opName,
127  (outs rc:$vdst),
128  (ins VGPR_32:$addr, rc:$data0, offset:$offset, gds:$gds),
129  "$vdst, $addr, $data0$offset$gds"> {
130
131  let hasPostISelHook = 1;
132  let has_data1 = 0;
133}
134
135class DS_1A2D_RET<string opName,
136                  RegisterClass rc = VGPR_32,
137                  RegisterClass src = rc>
138: DS_Pseudo<opName,
139  (outs rc:$vdst),
140  (ins VGPR_32:$addr, src:$data0, src:$data1, offset:$offset, gds:$gds),
141  "$vdst, $addr, $data0, $data1$offset$gds"> {
142
143  let hasPostISelHook = 1;
144}
145
146class DS_1A_RET<string opName, RegisterClass rc = VGPR_32>
147: DS_Pseudo<opName,
148  (outs rc:$vdst),
149  (ins VGPR_32:$addr, offset:$offset, gds:$gds),
150  "$vdst, $addr$offset$gds"> {
151
152  let has_data0 = 0;
153  let has_data1 = 0;
154}
155
156class DS_1A_Off8_RET <string opName, RegisterClass rc = VGPR_32>
157: DS_Pseudo<opName,
158  (outs rc:$vdst),
159  (ins VGPR_32:$addr, offset0:$offset0, offset1:$offset1, gds:$gds),
160  "$vdst, $addr$offset0$offset1$gds"> {
161
162  let has_offset = 0;
163  let has_data0 = 0;
164  let has_data1 = 0;
165  let AsmMatchConverter = "cvtDSOffset01";
166}
167
168class DS_1A_RET_GDS <string opName> : DS_Pseudo<opName,
169  (outs VGPR_32:$vdst),
170  (ins VGPR_32:$addr, offset:$offset),
171  "$vdst, $addr$offset gds"> {
172
173  let has_data0 = 0;
174  let has_data1 = 0;
175  let has_gds = 0;
176  let gdsValue = 1;
177}
178
179class DS_0A_RET <string opName> : DS_Pseudo<opName,
180  (outs VGPR_32:$vdst),
181  (ins offset:$offset, gds:$gds),
182  "$vdst$offset$gds"> {
183
184  let mayLoad = 1;
185  let mayStore = 1;
186
187  let has_addr = 0;
188  let has_data0 = 0;
189  let has_data1 = 0;
190}
191
192class DS_1A <string opName> : DS_Pseudo<opName,
193  (outs),
194  (ins VGPR_32:$addr, offset:$offset, gds:$gds),
195  "$addr$offset$gds"> {
196
197  let mayLoad = 1;
198  let mayStore = 1;
199
200  let has_vdst = 0;
201  let has_data0 = 0;
202  let has_data1 = 0;
203}
204
205class DS_1A_GDS <string opName> : DS_Pseudo<opName,
206  (outs),
207  (ins VGPR_32:$addr),
208  "$addr gds"> {
209
210  let has_vdst    = 0;
211  let has_data0   = 0;
212  let has_data1   = 0;
213  let has_offset  = 0;
214  let has_offset0 = 0;
215  let has_offset1 = 0;
216
217  let has_gds     = 0;
218  let gdsValue    = 1;
219}
220
221class DS_1A1D_PERMUTE <string opName, SDPatternOperator node = null_frag>
222: DS_Pseudo<opName,
223  (outs VGPR_32:$vdst),
224  (ins VGPR_32:$addr, VGPR_32:$data0, offset:$offset),
225  "$vdst, $addr, $data0$offset",
226  [(set i32:$vdst,
227   (node (DS1Addr1Offset i32:$addr, i16:$offset), i32:$data0))] > {
228
229  let mayLoad = 0;
230  let mayStore = 0;
231  let isConvergent = 1;
232
233  let has_data1 = 0;
234  let has_gds = 0;
235}
236
237def DS_ADD_U32        : DS_1A1D_NORET<"ds_add_u32">;
238def DS_SUB_U32        : DS_1A1D_NORET<"ds_sub_u32">;
239def DS_RSUB_U32       : DS_1A1D_NORET<"ds_rsub_u32">;
240def DS_INC_U32        : DS_1A1D_NORET<"ds_inc_u32">;
241def DS_DEC_U32        : DS_1A1D_NORET<"ds_dec_u32">;
242def DS_MIN_I32        : DS_1A1D_NORET<"ds_min_i32">;
243def DS_MAX_I32        : DS_1A1D_NORET<"ds_max_i32">;
244def DS_MIN_U32        : DS_1A1D_NORET<"ds_min_u32">;
245def DS_MAX_U32        : DS_1A1D_NORET<"ds_max_u32">;
246def DS_AND_B32        : DS_1A1D_NORET<"ds_and_b32">;
247def DS_OR_B32         : DS_1A1D_NORET<"ds_or_b32">;
248def DS_XOR_B32        : DS_1A1D_NORET<"ds_xor_b32">;
249def DS_ADD_F32        : DS_1A1D_NORET<"ds_add_f32">;
250def DS_MIN_F32        : DS_1A1D_NORET<"ds_min_f32">;
251def DS_MAX_F32        : DS_1A1D_NORET<"ds_max_f32">;
252
253let mayLoad = 0 in {
254def DS_WRITE_B8       : DS_1A1D_NORET<"ds_write_b8">;
255def DS_WRITE_B16      : DS_1A1D_NORET<"ds_write_b16">;
256def DS_WRITE_B32      : DS_1A1D_NORET<"ds_write_b32">;
257def DS_WRITE2_B32     : DS_1A2D_Off8_NORET<"ds_write2_b32">;
258def DS_WRITE2ST64_B32 : DS_1A2D_Off8_NORET<"ds_write2st64_b32">;
259}
260
261def DS_MSKOR_B32      : DS_1A2D_NORET<"ds_mskor_b32">;
262def DS_CMPST_B32      : DS_1A2D_NORET<"ds_cmpst_b32">;
263def DS_CMPST_F32      : DS_1A2D_NORET<"ds_cmpst_f32">;
264
265def DS_ADD_U64        : DS_1A1D_NORET<"ds_add_u64", VReg_64>;
266def DS_SUB_U64        : DS_1A1D_NORET<"ds_sub_u64", VReg_64>;
267def DS_RSUB_U64       : DS_1A1D_NORET<"ds_rsub_u64", VReg_64>;
268def DS_INC_U64        : DS_1A1D_NORET<"ds_inc_u64", VReg_64>;
269def DS_DEC_U64        : DS_1A1D_NORET<"ds_dec_u64", VReg_64>;
270def DS_MIN_I64        : DS_1A1D_NORET<"ds_min_i64", VReg_64>;
271def DS_MAX_I64        : DS_1A1D_NORET<"ds_max_i64", VReg_64>;
272def DS_MIN_U64        : DS_1A1D_NORET<"ds_min_u64", VReg_64>;
273def DS_MAX_U64        : DS_1A1D_NORET<"ds_max_u64", VReg_64>;
274def DS_AND_B64        : DS_1A1D_NORET<"ds_and_b64", VReg_64>;
275def DS_OR_B64         : DS_1A1D_NORET<"ds_or_b64", VReg_64>;
276def DS_XOR_B64        : DS_1A1D_NORET<"ds_xor_b64", VReg_64>;
277def DS_MSKOR_B64      : DS_1A2D_NORET<"ds_mskor_b64", VReg_64>;
278let mayLoad = 0 in {
279def DS_WRITE_B64      : DS_1A1D_NORET<"ds_write_b64", VReg_64>;
280def DS_WRITE2_B64     : DS_1A2D_Off8_NORET<"ds_write2_b64", VReg_64>;
281def DS_WRITE2ST64_B64 : DS_1A2D_Off8_NORET<"ds_write2st64_b64", VReg_64>;
282}
283def DS_CMPST_B64      : DS_1A2D_NORET<"ds_cmpst_b64", VReg_64>;
284def DS_CMPST_F64      : DS_1A2D_NORET<"ds_cmpst_f64", VReg_64>;
285def DS_MIN_F64        : DS_1A1D_NORET<"ds_min_f64", VReg_64>;
286def DS_MAX_F64        : DS_1A1D_NORET<"ds_max_f64", VReg_64>;
287
288def DS_ADD_RTN_U32    : DS_1A1D_RET<"ds_add_rtn_u32">,
289                        AtomicNoRet<"ds_add_u32", 1>;
290def DS_ADD_RTN_F32    : DS_1A1D_RET<"ds_add_rtn_f32">,
291                        AtomicNoRet<"ds_add_f32", 1>;
292def DS_SUB_RTN_U32    : DS_1A1D_RET<"ds_sub_rtn_u32">,
293                        AtomicNoRet<"ds_sub_u32", 1>;
294def DS_RSUB_RTN_U32   : DS_1A1D_RET<"ds_rsub_rtn_u32">,
295                        AtomicNoRet<"ds_rsub_u32", 1>;
296def DS_INC_RTN_U32    : DS_1A1D_RET<"ds_inc_rtn_u32">,
297                        AtomicNoRet<"ds_inc_u32", 1>;
298def DS_DEC_RTN_U32    : DS_1A1D_RET<"ds_dec_rtn_u32">,
299                        AtomicNoRet<"ds_dec_u32", 1>;
300def DS_MIN_RTN_I32    : DS_1A1D_RET<"ds_min_rtn_i32">,
301                        AtomicNoRet<"ds_min_i32", 1>;
302def DS_MAX_RTN_I32    : DS_1A1D_RET<"ds_max_rtn_i32">,
303                        AtomicNoRet<"ds_max_i32", 1>;
304def DS_MIN_RTN_U32    : DS_1A1D_RET<"ds_min_rtn_u32">,
305                        AtomicNoRet<"ds_min_u32", 1>;
306def DS_MAX_RTN_U32    : DS_1A1D_RET<"ds_max_rtn_u32">,
307                        AtomicNoRet<"ds_max_u32", 1>;
308def DS_AND_RTN_B32    : DS_1A1D_RET<"ds_and_rtn_b32">,
309                        AtomicNoRet<"ds_and_b32", 1>;
310def DS_OR_RTN_B32     : DS_1A1D_RET<"ds_or_rtn_b32">,
311                        AtomicNoRet<"ds_or_b32", 1>;
312def DS_XOR_RTN_B32    : DS_1A1D_RET<"ds_xor_rtn_b32">,
313                        AtomicNoRet<"ds_xor_b32", 1>;
314def DS_MSKOR_RTN_B32  : DS_1A2D_RET<"ds_mskor_rtn_b32">,
315                        AtomicNoRet<"ds_mskor_b32", 1>;
316def DS_CMPST_RTN_B32  : DS_1A2D_RET <"ds_cmpst_rtn_b32">,
317                        AtomicNoRet<"ds_cmpst_b32", 1>;
318def DS_CMPST_RTN_F32  : DS_1A2D_RET <"ds_cmpst_rtn_f32">,
319                        AtomicNoRet<"ds_cmpst_f32", 1>;
320def DS_MIN_RTN_F32    : DS_1A1D_RET <"ds_min_rtn_f32">,
321                        AtomicNoRet<"ds_min_f32", 1>;
322def DS_MAX_RTN_F32    : DS_1A1D_RET <"ds_max_rtn_f32">,
323                        AtomicNoRet<"ds_max_f32", 1>;
324
325def DS_WRXCHG_RTN_B32      : DS_1A1D_RET<"ds_wrxchg_rtn_b32">,
326                             AtomicNoRet<"", 1>;
327def DS_WRXCHG2_RTN_B32     : DS_1A2D_RET<"ds_wrxchg2_rtn_b32", VReg_64, VGPR_32>,
328                             AtomicNoRet<"", 1>;
329def DS_WRXCHG2ST64_RTN_B32 : DS_1A2D_RET<"ds_wrxchg2st64_rtn_b32", VReg_64, VGPR_32>,
330                             AtomicNoRet<"", 1>;
331
332def DS_ADD_RTN_U64    : DS_1A1D_RET<"ds_add_rtn_u64", VReg_64>,
333                        AtomicNoRet<"ds_add_u64", 1>;
334def DS_SUB_RTN_U64    : DS_1A1D_RET<"ds_sub_rtn_u64", VReg_64>,
335                        AtomicNoRet<"ds_sub_u64", 1>;
336def DS_RSUB_RTN_U64   : DS_1A1D_RET<"ds_rsub_rtn_u64", VReg_64>,
337                        AtomicNoRet<"ds_rsub_u64", 1>;
338def DS_INC_RTN_U64    : DS_1A1D_RET<"ds_inc_rtn_u64", VReg_64>,
339                        AtomicNoRet<"ds_inc_u64", 1>;
340def DS_DEC_RTN_U64    : DS_1A1D_RET<"ds_dec_rtn_u64", VReg_64>,
341                        AtomicNoRet<"ds_dec_u64", 1>;
342def DS_MIN_RTN_I64    : DS_1A1D_RET<"ds_min_rtn_i64", VReg_64>,
343                        AtomicNoRet<"ds_min_i64", 1>;
344def DS_MAX_RTN_I64    : DS_1A1D_RET<"ds_max_rtn_i64", VReg_64>,
345                        AtomicNoRet<"ds_max_i64", 1>;
346def DS_MIN_RTN_U64    : DS_1A1D_RET<"ds_min_rtn_u64", VReg_64>,
347                        AtomicNoRet<"ds_min_u64", 1>;
348def DS_MAX_RTN_U64    : DS_1A1D_RET<"ds_max_rtn_u64", VReg_64>,
349                        AtomicNoRet<"ds_max_u64", 1>;
350def DS_AND_RTN_B64    : DS_1A1D_RET<"ds_and_rtn_b64", VReg_64>,
351                        AtomicNoRet<"ds_and_b64", 1>;
352def DS_OR_RTN_B64     : DS_1A1D_RET<"ds_or_rtn_b64", VReg_64>,
353                        AtomicNoRet<"ds_or_b64", 1>;
354def DS_XOR_RTN_B64    : DS_1A1D_RET<"ds_xor_rtn_b64", VReg_64>,
355                        AtomicNoRet<"ds_xor_b64", 1>;
356def DS_MSKOR_RTN_B64  : DS_1A2D_RET<"ds_mskor_rtn_b64", VReg_64>,
357                        AtomicNoRet<"ds_mskor_b64", 1>;
358def DS_CMPST_RTN_B64  : DS_1A2D_RET<"ds_cmpst_rtn_b64", VReg_64>,
359                        AtomicNoRet<"ds_cmpst_b64", 1>;
360def DS_CMPST_RTN_F64  : DS_1A2D_RET<"ds_cmpst_rtn_f64", VReg_64>,
361                        AtomicNoRet<"ds_cmpst_f64", 1>;
362def DS_MIN_RTN_F64    : DS_1A1D_RET<"ds_min_rtn_f64", VReg_64>,
363                        AtomicNoRet<"ds_min_f64", 1>;
364def DS_MAX_RTN_F64    : DS_1A1D_RET<"ds_max_rtn_f64", VReg_64>,
365                        AtomicNoRet<"ds_max_f64", 1>;
366
367def DS_WRXCHG_RTN_B64      : DS_1A1D_RET<"ds_wrxchg_rtn_b64", VReg_64>,
368                             AtomicNoRet<"ds_wrxchg_b64", 1>;
369def DS_WRXCHG2_RTN_B64     : DS_1A2D_RET<"ds_wrxchg2_rtn_b64", VReg_128, VReg_64>,
370                             AtomicNoRet<"ds_wrxchg2_b64", 1>;
371def DS_WRXCHG2ST64_RTN_B64 : DS_1A2D_RET<"ds_wrxchg2st64_rtn_b64", VReg_128, VReg_64>,
372                             AtomicNoRet<"ds_wrxchg2st64_b64", 1>;
373
374def DS_GWS_INIT       : DS_1A_GDS<"ds_gws_init">;
375def DS_GWS_SEMA_V     : DS_1A_GDS<"ds_gws_sema_v">;
376def DS_GWS_SEMA_BR    : DS_1A_GDS<"ds_gws_sema_br">;
377def DS_GWS_SEMA_P     : DS_1A_GDS<"ds_gws_sema_p">;
378def DS_GWS_BARRIER    : DS_1A_GDS<"ds_gws_barrier">;
379
380def DS_ADD_SRC2_U32   : DS_1A<"ds_add_src2_u32">;
381def DS_SUB_SRC2_U32   : DS_1A<"ds_sub_src2_u32">;
382def DS_RSUB_SRC2_U32  : DS_1A<"ds_rsub_src2_u32">;
383def DS_INC_SRC2_U32   : DS_1A<"ds_inc_src2_u32">;
384def DS_DEC_SRC2_U32   : DS_1A<"ds_dec_src2_u32">;
385def DS_MIN_SRC2_I32   : DS_1A<"ds_min_src2_i32">;
386def DS_MAX_SRC2_I32   : DS_1A<"ds_max_src2_i32">;
387def DS_MIN_SRC2_U32   : DS_1A<"ds_min_src2_u32">;
388def DS_MAX_SRC2_U32   : DS_1A<"ds_max_src2_u32">;
389def DS_AND_SRC2_B32   : DS_1A<"ds_and_src_b32">;
390def DS_OR_SRC2_B32    : DS_1A<"ds_or_src2_b32">;
391def DS_XOR_SRC2_B32   : DS_1A<"ds_xor_src2_b32">;
392def DS_MIN_SRC2_F32   : DS_1A<"ds_min_src2_f32">;
393def DS_MAX_SRC2_F32   : DS_1A<"ds_max_src2_f32">;
394
395def DS_ADD_SRC2_U64   : DS_1A<"ds_add_src2_u64">;
396def DS_SUB_SRC2_U64   : DS_1A<"ds_sub_src2_u64">;
397def DS_RSUB_SRC2_U64  : DS_1A<"ds_rsub_src2_u64">;
398def DS_INC_SRC2_U64   : DS_1A<"ds_inc_src2_u64">;
399def DS_DEC_SRC2_U64   : DS_1A<"ds_dec_src2_u64">;
400def DS_MIN_SRC2_I64   : DS_1A<"ds_min_src2_i64">;
401def DS_MAX_SRC2_I64   : DS_1A<"ds_max_src2_i64">;
402def DS_MIN_SRC2_U64   : DS_1A<"ds_min_src2_u64">;
403def DS_MAX_SRC2_U64   : DS_1A<"ds_max_src2_u64">;
404def DS_AND_SRC2_B64   : DS_1A<"ds_and_src2_b64">;
405def DS_OR_SRC2_B64    : DS_1A<"ds_or_src2_b64">;
406def DS_XOR_SRC2_B64   : DS_1A<"ds_xor_src2_b64">;
407def DS_MIN_SRC2_F64   : DS_1A<"ds_min_src2_f64">;
408def DS_MAX_SRC2_F64   : DS_1A<"ds_max_src2_f64">;
409
410def DS_WRITE_SRC2_B32 : DS_1A_Off8_NORET<"ds_write_src2_b32">;
411def DS_WRITE_SRC2_B64 : DS_1A_Off8_NORET<"ds_write_src2_b64">;
412
413let Uses = [EXEC], mayLoad = 0, mayStore = 0, isConvergent = 1 in {
414def DS_SWIZZLE_B32 : DS_1A_RET <"ds_swizzle_b32">;
415}
416
417let mayStore = 0 in {
418def DS_READ_I8       : DS_1A_RET<"ds_read_i8">;
419def DS_READ_U8       : DS_1A_RET<"ds_read_u8">;
420def DS_READ_I16      : DS_1A_RET<"ds_read_i16">;
421def DS_READ_U16      : DS_1A_RET<"ds_read_u16">;
422def DS_READ_B32      : DS_1A_RET<"ds_read_b32">;
423def DS_READ_B64      : DS_1A_RET<"ds_read_b64", VReg_64>;
424
425def DS_READ2_B32     : DS_1A_Off8_RET<"ds_read2_b32", VReg_64>;
426def DS_READ2ST64_B32 : DS_1A_Off8_RET<"ds_read2st64_b32", VReg_64>;
427
428def DS_READ2_B64     : DS_1A_Off8_RET<"ds_read2_b64", VReg_128>;
429def DS_READ2ST64_B64 : DS_1A_Off8_RET<"ds_read2st64_b64", VReg_128>;
430}
431
432let SubtargetPredicate = isSICI in {
433def DS_CONSUME       : DS_0A_RET<"ds_consume">;
434def DS_APPEND        : DS_0A_RET<"ds_append">;
435def DS_ORDERED_COUNT : DS_1A_RET_GDS<"ds_ordered_count">;
436}
437
438//===----------------------------------------------------------------------===//
439// Instruction definitions for CI and newer.
440//===----------------------------------------------------------------------===//
441// Remaining instructions:
442// DS_NOP
443// DS_GWS_SEMA_RELEASE_ALL
444// DS_WRAP_RTN_B32
445// DS_CNDXCHG32_RTN_B64
446// DS_WRITE_B96
447// DS_WRITE_B128
448// DS_CONDXCHG32_RTN_B128
449// DS_READ_B96
450// DS_READ_B128
451
452let SubtargetPredicate = isCIVI in {
453
454def DS_WRAP_RTN_F32 : DS_1A1D_RET <"ds_wrap_rtn_f32">,
455                      AtomicNoRet<"ds_wrap_f32", 1>;
456
457} // let SubtargetPredicate = isCIVI
458
459//===----------------------------------------------------------------------===//
460// Instruction definitions for VI and newer.
461//===----------------------------------------------------------------------===//
462
463let SubtargetPredicate = isVI in {
464
465let Uses = [EXEC] in {
466def DS_PERMUTE_B32  : DS_1A1D_PERMUTE <"ds_permute_b32",
467                                       int_amdgcn_ds_permute>;
468def DS_BPERMUTE_B32 : DS_1A1D_PERMUTE <"ds_bpermute_b32",
469                                       int_amdgcn_ds_bpermute>;
470}
471
472} // let SubtargetPredicate = isVI
473
474//===----------------------------------------------------------------------===//
475// DS Patterns
476//===----------------------------------------------------------------------===//
477
478let Predicates = [isGCN] in {
479
480def : Pat <
481  (int_amdgcn_ds_swizzle i32:$src, imm:$offset16),
482  (DS_SWIZZLE_B32 $src, (as_i16imm $offset16), (i1 0))
483>;
484
485class DSReadPat <DS_Pseudo inst, ValueType vt, PatFrag frag> : Pat <
486  (vt (frag (DS1Addr1Offset i32:$ptr, i32:$offset))),
487  (inst $ptr, (as_i16imm $offset), (i1 0))
488>;
489
490def : DSReadPat <DS_READ_I8,  i32, si_sextload_local_i8>;
491def : DSReadPat <DS_READ_U8,  i32, si_az_extload_local_i8>;
492def : DSReadPat <DS_READ_I8,  i16, si_sextload_local_i8>;
493def : DSReadPat <DS_READ_U8,  i16, si_az_extload_local_i8>;
494def : DSReadPat <DS_READ_I16, i32, si_sextload_local_i16>;
495def : DSReadPat <DS_READ_I16, i32, si_sextload_local_i16>;
496def : DSReadPat <DS_READ_U16, i32, si_az_extload_local_i16>;
497def : DSReadPat <DS_READ_U16, i16, si_load_local>;
498def : DSReadPat <DS_READ_B32, i32, si_load_local>;
499
500let AddedComplexity = 100 in {
501
502def : DSReadPat <DS_READ_B64, v2i32, si_load_local_align8>;
503
504} // End AddedComplexity = 100
505
506def : Pat <
507  (v2i32 (si_load_local (DS64Bit4ByteAligned i32:$ptr, i8:$offset0,
508                                                    i8:$offset1))),
509  (DS_READ2_B32 $ptr, $offset0, $offset1, (i1 0))
510>;
511
512class DSWritePat <DS_Pseudo inst, ValueType vt, PatFrag frag> : Pat <
513  (frag vt:$value, (DS1Addr1Offset i32:$ptr, i32:$offset)),
514  (inst $ptr, $value, (as_i16imm $offset), (i1 0))
515>;
516
517def : DSWritePat <DS_WRITE_B8, i32, si_truncstore_local_i8>;
518def : DSWritePat <DS_WRITE_B16, i32, si_truncstore_local_i16>;
519def : DSWritePat <DS_WRITE_B8, i16, si_truncstore_local_i8>;
520def : DSWritePat <DS_WRITE_B16, i16, si_store_local>;
521def : DSWritePat <DS_WRITE_B32, i32, si_store_local>;
522
523let AddedComplexity = 100 in {
524
525def : DSWritePat <DS_WRITE_B64, v2i32, si_store_local_align8>;
526} // End AddedComplexity = 100
527
528def : Pat <
529  (si_store_local v2i32:$value, (DS64Bit4ByteAligned i32:$ptr, i8:$offset0,
530                                                               i8:$offset1)),
531  (DS_WRITE2_B32 $ptr, (i32 (EXTRACT_SUBREG $value, sub0)),
532                       (i32 (EXTRACT_SUBREG $value, sub1)), $offset0, $offset1,
533                       (i1 0))
534>;
535
536class DSAtomicRetPat<DS_Pseudo inst, ValueType vt, PatFrag frag> : Pat <
537  (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$value),
538  (inst $ptr, $value, (as_i16imm $offset), (i1 0))
539>;
540
541class DSAtomicCmpXChg<DS_Pseudo inst, ValueType vt, PatFrag frag> : Pat <
542  (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$cmp, vt:$swap),
543  (inst $ptr, $cmp, $swap, (as_i16imm $offset), (i1 0))
544>;
545
546
547// 32-bit atomics.
548def : DSAtomicRetPat<DS_WRXCHG_RTN_B32, i32, si_atomic_swap_local>;
549def : DSAtomicRetPat<DS_ADD_RTN_U32, i32, si_atomic_load_add_local>;
550def : DSAtomicRetPat<DS_SUB_RTN_U32, i32, si_atomic_load_sub_local>;
551def : DSAtomicRetPat<DS_INC_RTN_U32, i32, si_atomic_inc_local>;
552def : DSAtomicRetPat<DS_DEC_RTN_U32, i32, si_atomic_dec_local>;
553def : DSAtomicRetPat<DS_AND_RTN_B32, i32, si_atomic_load_and_local>;
554def : DSAtomicRetPat<DS_OR_RTN_B32, i32, si_atomic_load_or_local>;
555def : DSAtomicRetPat<DS_XOR_RTN_B32, i32, si_atomic_load_xor_local>;
556def : DSAtomicRetPat<DS_MIN_RTN_I32, i32, si_atomic_load_min_local>;
557def : DSAtomicRetPat<DS_MAX_RTN_I32, i32, si_atomic_load_max_local>;
558def : DSAtomicRetPat<DS_MIN_RTN_U32, i32, si_atomic_load_umin_local>;
559def : DSAtomicRetPat<DS_MAX_RTN_U32, i32, si_atomic_load_umax_local>;
560def : DSAtomicCmpXChg<DS_CMPST_RTN_B32, i32, si_atomic_cmp_swap_32_local>;
561
562// 64-bit atomics.
563def : DSAtomicRetPat<DS_WRXCHG_RTN_B64, i64, si_atomic_swap_local>;
564def : DSAtomicRetPat<DS_ADD_RTN_U64, i64, si_atomic_load_add_local>;
565def : DSAtomicRetPat<DS_SUB_RTN_U64, i64, si_atomic_load_sub_local>;
566def : DSAtomicRetPat<DS_INC_RTN_U64, i64, si_atomic_inc_local>;
567def : DSAtomicRetPat<DS_DEC_RTN_U64, i64, si_atomic_dec_local>;
568def : DSAtomicRetPat<DS_AND_RTN_B64, i64, si_atomic_load_and_local>;
569def : DSAtomicRetPat<DS_OR_RTN_B64, i64, si_atomic_load_or_local>;
570def : DSAtomicRetPat<DS_XOR_RTN_B64, i64, si_atomic_load_xor_local>;
571def : DSAtomicRetPat<DS_MIN_RTN_I64, i64, si_atomic_load_min_local>;
572def : DSAtomicRetPat<DS_MAX_RTN_I64, i64, si_atomic_load_max_local>;
573def : DSAtomicRetPat<DS_MIN_RTN_U64, i64, si_atomic_load_umin_local>;
574def : DSAtomicRetPat<DS_MAX_RTN_U64, i64, si_atomic_load_umax_local>;
575
576def : DSAtomicCmpXChg<DS_CMPST_RTN_B64, i64, si_atomic_cmp_swap_64_local>;
577
578} // let Predicates = [isGCN]
579
580//===----------------------------------------------------------------------===//
581// Real instructions
582//===----------------------------------------------------------------------===//
583
584//===----------------------------------------------------------------------===//
585// SIInstructions.td
586//===----------------------------------------------------------------------===//
587
588class DS_Real_si <bits<8> op, DS_Pseudo ds> :
589  DS_Real <ds>,
590  SIMCInstr <ds.Mnemonic, SIEncodingFamily.SI> {
591  let AssemblerPredicates=[isSICI];
592  let DecoderNamespace="SICI";
593
594  // encoding
595  let Inst{7-0}   = !if(ds.has_offset0, offset0, 0);
596  let Inst{15-8}  = !if(ds.has_offset1, offset1, 0);
597  let Inst{17}    = !if(ds.has_gds, gds, ds.gdsValue);
598  let Inst{25-18} = op;
599  let Inst{31-26} = 0x36; // ds prefix
600  let Inst{39-32} = !if(ds.has_addr, addr, 0);
601  let Inst{47-40} = !if(ds.has_data0, data0, 0);
602  let Inst{55-48} = !if(ds.has_data1, data1, 0);
603  let Inst{63-56} = !if(ds.has_vdst, vdst, 0);
604}
605
606def DS_ADD_U32_si         : DS_Real_si<0x0,  DS_ADD_U32>;
607def DS_SUB_U32_si         : DS_Real_si<0x1,  DS_SUB_U32>;
608def DS_RSUB_U32_si        : DS_Real_si<0x2,  DS_RSUB_U32>;
609def DS_INC_U32_si         : DS_Real_si<0x3,  DS_INC_U32>;
610def DS_DEC_U32_si         : DS_Real_si<0x4,  DS_DEC_U32>;
611def DS_MIN_I32_si         : DS_Real_si<0x5,  DS_MIN_I32>;
612def DS_MAX_I32_si         : DS_Real_si<0x6,  DS_MAX_I32>;
613def DS_MIN_U32_si         : DS_Real_si<0x7,  DS_MIN_U32>;
614def DS_MAX_U32_si         : DS_Real_si<0x8,  DS_MAX_U32>;
615def DS_AND_B32_si         : DS_Real_si<0x9,  DS_AND_B32>;
616def DS_OR_B32_si          : DS_Real_si<0xa,  DS_OR_B32>;
617def DS_XOR_B32_si         : DS_Real_si<0xb,  DS_XOR_B32>;
618def DS_MSKOR_B32_si       : DS_Real_si<0xc,  DS_MSKOR_B32>;
619def DS_WRITE_B32_si       : DS_Real_si<0xd,  DS_WRITE_B32>;
620def DS_WRITE2_B32_si      : DS_Real_si<0xe,  DS_WRITE2_B32>;
621def DS_WRITE2ST64_B32_si  : DS_Real_si<0xf,  DS_WRITE2ST64_B32>;
622def DS_CMPST_B32_si       : DS_Real_si<0x10, DS_CMPST_B32>;
623def DS_CMPST_F32_si       : DS_Real_si<0x11, DS_CMPST_F32>;
624def DS_MIN_F32_si         : DS_Real_si<0x12, DS_MIN_F32>;
625def DS_MAX_F32_si         : DS_Real_si<0x13, DS_MAX_F32>;
626def DS_GWS_INIT_si        : DS_Real_si<0x19, DS_GWS_INIT>;
627def DS_GWS_SEMA_V_si      : DS_Real_si<0x1a, DS_GWS_SEMA_V>;
628def DS_GWS_SEMA_BR_si     : DS_Real_si<0x1b, DS_GWS_SEMA_BR>;
629def DS_GWS_SEMA_P_si      : DS_Real_si<0x1c, DS_GWS_SEMA_P>;
630def DS_GWS_BARRIER_si     : DS_Real_si<0x1d, DS_GWS_BARRIER>;
631def DS_WRITE_B8_si        : DS_Real_si<0x1e, DS_WRITE_B8>;
632def DS_WRITE_B16_si       : DS_Real_si<0x1f, DS_WRITE_B16>;
633def DS_ADD_RTN_U32_si     : DS_Real_si<0x20, DS_ADD_RTN_U32>;
634def DS_SUB_RTN_U32_si     : DS_Real_si<0x21, DS_SUB_RTN_U32>;
635def DS_RSUB_RTN_U32_si    : DS_Real_si<0x22, DS_RSUB_RTN_U32>;
636def DS_INC_RTN_U32_si     : DS_Real_si<0x23, DS_INC_RTN_U32>;
637def DS_DEC_RTN_U32_si     : DS_Real_si<0x24, DS_DEC_RTN_U32>;
638def DS_MIN_RTN_I32_si     : DS_Real_si<0x25, DS_MIN_RTN_I32>;
639def DS_MAX_RTN_I32_si     : DS_Real_si<0x26, DS_MAX_RTN_I32>;
640def DS_MIN_RTN_U32_si     : DS_Real_si<0x27, DS_MIN_RTN_U32>;
641def DS_MAX_RTN_U32_si     : DS_Real_si<0x28, DS_MAX_RTN_U32>;
642def DS_AND_RTN_B32_si     : DS_Real_si<0x29, DS_AND_RTN_B32>;
643def DS_OR_RTN_B32_si      : DS_Real_si<0x2a, DS_OR_RTN_B32>;
644def DS_XOR_RTN_B32_si     : DS_Real_si<0x2b, DS_XOR_RTN_B32>;
645def DS_MSKOR_RTN_B32_si   : DS_Real_si<0x2c, DS_MSKOR_RTN_B32>;
646def DS_WRXCHG_RTN_B32_si  : DS_Real_si<0x2d, DS_WRXCHG_RTN_B32>;
647def DS_WRXCHG2_RTN_B32_si : DS_Real_si<0x2e, DS_WRXCHG2_RTN_B32>;
648def DS_WRXCHG2ST64_RTN_B32_si : DS_Real_si<0x2f, DS_WRXCHG2ST64_RTN_B32>;
649def DS_CMPST_RTN_B32_si   : DS_Real_si<0x30, DS_CMPST_RTN_B32>;
650def DS_CMPST_RTN_F32_si   : DS_Real_si<0x31, DS_CMPST_RTN_F32>;
651def DS_MIN_RTN_F32_si     : DS_Real_si<0x32, DS_MIN_RTN_F32>;
652def DS_MAX_RTN_F32_si     : DS_Real_si<0x33, DS_MAX_RTN_F32>;
653
654// FIXME: this instruction is actually CI/VI
655def DS_WRAP_RTN_F32_si    : DS_Real_si<0x34, DS_WRAP_RTN_F32>;
656
657def DS_SWIZZLE_B32_si     : DS_Real_si<0x35, DS_SWIZZLE_B32>;
658def DS_READ_B32_si        : DS_Real_si<0x36, DS_READ_B32>;
659def DS_READ2_B32_si       : DS_Real_si<0x37, DS_READ2_B32>;
660def DS_READ2ST64_B32_si   : DS_Real_si<0x38, DS_READ2ST64_B32>;
661def DS_READ_I8_si         : DS_Real_si<0x39, DS_READ_I8>;
662def DS_READ_U8_si         : DS_Real_si<0x3a, DS_READ_U8>;
663def DS_READ_I16_si        : DS_Real_si<0x3b, DS_READ_I16>;
664def DS_READ_U16_si        : DS_Real_si<0x3c, DS_READ_U16>;
665def DS_CONSUME_si         : DS_Real_si<0x3d, DS_CONSUME>;
666def DS_APPEND_si          : DS_Real_si<0x3e, DS_APPEND>;
667def DS_ORDERED_COUNT_si   : DS_Real_si<0x3f, DS_ORDERED_COUNT>;
668def DS_ADD_U64_si         : DS_Real_si<0x40, DS_ADD_U64>;
669def DS_SUB_U64_si         : DS_Real_si<0x41, DS_SUB_U64>;
670def DS_RSUB_U64_si        : DS_Real_si<0x42, DS_RSUB_U64>;
671def DS_INC_U64_si         : DS_Real_si<0x43, DS_INC_U64>;
672def DS_DEC_U64_si         : DS_Real_si<0x44, DS_DEC_U64>;
673def DS_MIN_I64_si         : DS_Real_si<0x45, DS_MIN_I64>;
674def DS_MAX_I64_si         : DS_Real_si<0x46, DS_MAX_I64>;
675def DS_MIN_U64_si         : DS_Real_si<0x47, DS_MIN_U64>;
676def DS_MAX_U64_si         : DS_Real_si<0x48, DS_MAX_U64>;
677def DS_AND_B64_si         : DS_Real_si<0x49, DS_AND_B64>;
678def DS_OR_B64_si          : DS_Real_si<0x4a, DS_OR_B64>;
679def DS_XOR_B64_si         : DS_Real_si<0x4b, DS_XOR_B64>;
680def DS_MSKOR_B64_si       : DS_Real_si<0x4c, DS_MSKOR_B64>;
681def DS_WRITE_B64_si       : DS_Real_si<0x4d, DS_WRITE_B64>;
682def DS_WRITE2_B64_si      : DS_Real_si<0x4E, DS_WRITE2_B64>;
683def DS_WRITE2ST64_B64_si  : DS_Real_si<0x4f, DS_WRITE2ST64_B64>;
684def DS_CMPST_B64_si       : DS_Real_si<0x50, DS_CMPST_B64>;
685def DS_CMPST_F64_si       : DS_Real_si<0x51, DS_CMPST_F64>;
686def DS_MIN_F64_si         : DS_Real_si<0x52, DS_MIN_F64>;
687def DS_MAX_F64_si         : DS_Real_si<0x53, DS_MAX_F64>;
688
689def DS_ADD_RTN_U64_si     : DS_Real_si<0x60, DS_ADD_RTN_U64>;
690def DS_SUB_RTN_U64_si     : DS_Real_si<0x61, DS_SUB_RTN_U64>;
691def DS_RSUB_RTN_U64_si    : DS_Real_si<0x62, DS_RSUB_RTN_U64>;
692def DS_INC_RTN_U64_si     : DS_Real_si<0x63, DS_INC_RTN_U64>;
693def DS_DEC_RTN_U64_si     : DS_Real_si<0x64, DS_DEC_RTN_U64>;
694def DS_MIN_RTN_I64_si     : DS_Real_si<0x65, DS_MIN_RTN_I64>;
695def DS_MAX_RTN_I64_si     : DS_Real_si<0x66, DS_MAX_RTN_I64>;
696def DS_MIN_RTN_U64_si     : DS_Real_si<0x67, DS_MIN_RTN_U64>;
697def DS_MAX_RTN_U64_si     : DS_Real_si<0x68, DS_MAX_RTN_U64>;
698def DS_AND_RTN_B64_si     : DS_Real_si<0x69, DS_AND_RTN_B64>;
699def DS_OR_RTN_B64_si      : DS_Real_si<0x6a, DS_OR_RTN_B64>;
700def DS_XOR_RTN_B64_si     : DS_Real_si<0x6b, DS_XOR_RTN_B64>;
701def DS_MSKOR_RTN_B64_si   : DS_Real_si<0x6c, DS_MSKOR_RTN_B64>;
702def DS_WRXCHG_RTN_B64_si  : DS_Real_si<0x6d, DS_WRXCHG_RTN_B64>;
703def DS_WRXCHG2_RTN_B64_si : DS_Real_si<0x6e, DS_WRXCHG2_RTN_B64>;
704def DS_WRXCHG2ST64_RTN_B64_si : DS_Real_si<0x6f, DS_WRXCHG2ST64_RTN_B64>;
705def DS_CMPST_RTN_B64_si   : DS_Real_si<0x70, DS_CMPST_RTN_B64>;
706def DS_CMPST_RTN_F64_si   : DS_Real_si<0x71, DS_CMPST_RTN_F64>;
707def DS_MIN_RTN_F64_si     : DS_Real_si<0x72, DS_MIN_RTN_F64>;
708def DS_MAX_RTN_F64_si     : DS_Real_si<0x73, DS_MAX_RTN_F64>;
709
710def DS_READ_B64_si        : DS_Real_si<0x76, DS_READ_B64>;
711def DS_READ2_B64_si       : DS_Real_si<0x77, DS_READ2_B64>;
712def DS_READ2ST64_B64_si   : DS_Real_si<0x78, DS_READ2ST64_B64>;
713
714def DS_ADD_SRC2_U32_si    : DS_Real_si<0x80, DS_ADD_SRC2_U32>;
715def DS_SUB_SRC2_U32_si    : DS_Real_si<0x81, DS_SUB_SRC2_U32>;
716def DS_RSUB_SRC2_U32_si   : DS_Real_si<0x82, DS_RSUB_SRC2_U32>;
717def DS_INC_SRC2_U32_si    : DS_Real_si<0x83, DS_INC_SRC2_U32>;
718def DS_DEC_SRC2_U32_si    : DS_Real_si<0x84, DS_DEC_SRC2_U32>;
719def DS_MIN_SRC2_I32_si    : DS_Real_si<0x85, DS_MIN_SRC2_I32>;
720def DS_MAX_SRC2_I32_si    : DS_Real_si<0x86, DS_MAX_SRC2_I32>;
721def DS_MIN_SRC2_U32_si    : DS_Real_si<0x87, DS_MIN_SRC2_U32>;
722def DS_MAX_SRC2_U32_si    : DS_Real_si<0x88, DS_MAX_SRC2_U32>;
723def DS_AND_SRC2_B32_si    : DS_Real_si<0x89, DS_AND_SRC2_B32>;
724def DS_OR_SRC2_B32_si     : DS_Real_si<0x8a, DS_OR_SRC2_B32>;
725def DS_XOR_SRC2_B32_si    : DS_Real_si<0x8b, DS_XOR_SRC2_B32>;
726def DS_WRITE_SRC2_B32_si  : DS_Real_si<0x8d, DS_WRITE_SRC2_B32>;
727
728def DS_MIN_SRC2_F32_si    : DS_Real_si<0x92, DS_MIN_SRC2_F32>;
729def DS_MAX_SRC2_F32_si    : DS_Real_si<0x93, DS_MAX_SRC2_F32>;
730
731def DS_ADD_SRC2_U64_si    : DS_Real_si<0xc0, DS_ADD_SRC2_U64>;
732def DS_SUB_SRC2_U64_si    : DS_Real_si<0xc1, DS_SUB_SRC2_U64>;
733def DS_RSUB_SRC2_U64_si   : DS_Real_si<0xc2, DS_RSUB_SRC2_U64>;
734def DS_INC_SRC2_U64_si    : DS_Real_si<0xc3, DS_INC_SRC2_U64>;
735def DS_DEC_SRC2_U64_si    : DS_Real_si<0xc4, DS_DEC_SRC2_U64>;
736def DS_MIN_SRC2_I64_si    : DS_Real_si<0xc5, DS_MIN_SRC2_I64>;
737def DS_MAX_SRC2_I64_si    : DS_Real_si<0xc6, DS_MAX_SRC2_I64>;
738def DS_MIN_SRC2_U64_si    : DS_Real_si<0xc7, DS_MIN_SRC2_U64>;
739def DS_MAX_SRC2_U64_si    : DS_Real_si<0xc8, DS_MAX_SRC2_U64>;
740def DS_AND_SRC2_B64_si    : DS_Real_si<0xc9, DS_AND_SRC2_B64>;
741def DS_OR_SRC2_B64_si     : DS_Real_si<0xca, DS_OR_SRC2_B64>;
742def DS_XOR_SRC2_B64_si    : DS_Real_si<0xcb, DS_XOR_SRC2_B64>;
743def DS_WRITE_SRC2_B64_si  : DS_Real_si<0xcd, DS_WRITE_SRC2_B64>;
744
745def DS_MIN_SRC2_F64_si    : DS_Real_si<0xd2, DS_MIN_SRC2_F64>;
746def DS_MAX_SRC2_F64_si    : DS_Real_si<0xd3, DS_MAX_SRC2_F64>;
747
748//===----------------------------------------------------------------------===//
749// VIInstructions.td
750//===----------------------------------------------------------------------===//
751
752class DS_Real_vi <bits<8> op, DS_Pseudo ds> :
753  DS_Real <ds>,
754  SIMCInstr <ds.Mnemonic, SIEncodingFamily.VI> {
755  let AssemblerPredicates = [isVI];
756  let DecoderNamespace="VI";
757
758  // encoding
759  let Inst{7-0}   = !if(ds.has_offset0, offset0, 0);
760  let Inst{15-8}  = !if(ds.has_offset1, offset1, 0);
761  let Inst{16}    = !if(ds.has_gds, gds, ds.gdsValue);
762  let Inst{24-17} = op;
763  let Inst{31-26} = 0x36; // ds prefix
764  let Inst{39-32} = !if(ds.has_addr, addr, 0);
765  let Inst{47-40} = !if(ds.has_data0, data0, 0);
766  let Inst{55-48} = !if(ds.has_data1, data1, 0);
767  let Inst{63-56} = !if(ds.has_vdst, vdst, 0);
768}
769
770def DS_ADD_U32_vi         : DS_Real_vi<0x0,  DS_ADD_U32>;
771def DS_SUB_U32_vi         : DS_Real_vi<0x1,  DS_SUB_U32>;
772def DS_RSUB_U32_vi        : DS_Real_vi<0x2,  DS_RSUB_U32>;
773def DS_INC_U32_vi         : DS_Real_vi<0x3,  DS_INC_U32>;
774def DS_DEC_U32_vi         : DS_Real_vi<0x4,  DS_DEC_U32>;
775def DS_MIN_I32_vi         : DS_Real_vi<0x5,  DS_MIN_I32>;
776def DS_MAX_I32_vi         : DS_Real_vi<0x6,  DS_MAX_I32>;
777def DS_MIN_U32_vi         : DS_Real_vi<0x7,  DS_MIN_U32>;
778def DS_MAX_U32_vi         : DS_Real_vi<0x8,  DS_MAX_U32>;
779def DS_AND_B32_vi         : DS_Real_vi<0x9,  DS_AND_B32>;
780def DS_OR_B32_vi          : DS_Real_vi<0xa,  DS_OR_B32>;
781def DS_XOR_B32_vi         : DS_Real_vi<0xb,  DS_XOR_B32>;
782def DS_MSKOR_B32_vi       : DS_Real_vi<0xc,  DS_MSKOR_B32>;
783def DS_WRITE_B32_vi       : DS_Real_vi<0xd,  DS_WRITE_B32>;
784def DS_WRITE2_B32_vi      : DS_Real_vi<0xe,  DS_WRITE2_B32>;
785def DS_WRITE2ST64_B32_vi  : DS_Real_vi<0xf,  DS_WRITE2ST64_B32>;
786def DS_CMPST_B32_vi       : DS_Real_vi<0x10, DS_CMPST_B32>;
787def DS_CMPST_F32_vi       : DS_Real_vi<0x11, DS_CMPST_F32>;
788def DS_MIN_F32_vi         : DS_Real_vi<0x12, DS_MIN_F32>;
789def DS_MAX_F32_vi         : DS_Real_vi<0x13, DS_MAX_F32>;
790def DS_ADD_F32_vi         : DS_Real_vi<0x15, DS_ADD_F32>;
791def DS_GWS_INIT_vi        : DS_Real_vi<0x19, DS_GWS_INIT>;
792def DS_GWS_SEMA_V_vi      : DS_Real_vi<0x1a, DS_GWS_SEMA_V>;
793def DS_GWS_SEMA_BR_vi     : DS_Real_vi<0x1b, DS_GWS_SEMA_BR>;
794def DS_GWS_SEMA_P_vi      : DS_Real_vi<0x1c, DS_GWS_SEMA_P>;
795def DS_GWS_BARRIER_vi     : DS_Real_vi<0x1d, DS_GWS_BARRIER>;
796def DS_WRITE_B8_vi        : DS_Real_vi<0x1e, DS_WRITE_B8>;
797def DS_WRITE_B16_vi       : DS_Real_vi<0x1f, DS_WRITE_B16>;
798def DS_ADD_RTN_U32_vi     : DS_Real_vi<0x20, DS_ADD_RTN_U32>;
799def DS_SUB_RTN_U32_vi     : DS_Real_vi<0x21, DS_SUB_RTN_U32>;
800def DS_RSUB_RTN_U32_vi    : DS_Real_vi<0x22, DS_RSUB_RTN_U32>;
801def DS_INC_RTN_U32_vi     : DS_Real_vi<0x23, DS_INC_RTN_U32>;
802def DS_DEC_RTN_U32_vi     : DS_Real_vi<0x24, DS_DEC_RTN_U32>;
803def DS_MIN_RTN_I32_vi     : DS_Real_vi<0x25, DS_MIN_RTN_I32>;
804def DS_MAX_RTN_I32_vi     : DS_Real_vi<0x26, DS_MAX_RTN_I32>;
805def DS_MIN_RTN_U32_vi     : DS_Real_vi<0x27, DS_MIN_RTN_U32>;
806def DS_MAX_RTN_U32_vi     : DS_Real_vi<0x28, DS_MAX_RTN_U32>;
807def DS_AND_RTN_B32_vi     : DS_Real_vi<0x29, DS_AND_RTN_B32>;
808def DS_OR_RTN_B32_vi      : DS_Real_vi<0x2a, DS_OR_RTN_B32>;
809def DS_XOR_RTN_B32_vi     : DS_Real_vi<0x2b, DS_XOR_RTN_B32>;
810def DS_MSKOR_RTN_B32_vi   : DS_Real_vi<0x2c, DS_MSKOR_RTN_B32>;
811def DS_WRXCHG_RTN_B32_vi  : DS_Real_vi<0x2d, DS_WRXCHG_RTN_B32>;
812def DS_WRXCHG2_RTN_B32_vi : DS_Real_vi<0x2e, DS_WRXCHG2_RTN_B32>;
813def DS_WRXCHG2ST64_RTN_B32_vi : DS_Real_vi<0x2f, DS_WRXCHG2ST64_RTN_B32>;
814def DS_CMPST_RTN_B32_vi   : DS_Real_vi<0x30, DS_CMPST_RTN_B32>;
815def DS_CMPST_RTN_F32_vi   : DS_Real_vi<0x31, DS_CMPST_RTN_F32>;
816def DS_MIN_RTN_F32_vi     : DS_Real_vi<0x32, DS_MIN_RTN_F32>;
817def DS_MAX_RTN_F32_vi     : DS_Real_vi<0x33, DS_MAX_RTN_F32>;
818def DS_WRAP_RTN_F32_vi    : DS_Real_vi<0x34, DS_WRAP_RTN_F32>;
819def DS_ADD_RTN_F32_vi     : DS_Real_vi<0x35, DS_ADD_RTN_F32>;
820def DS_READ_B32_vi        : DS_Real_vi<0x36, DS_READ_B32>;
821def DS_READ2_B32_vi       : DS_Real_vi<0x37, DS_READ2_B32>;
822def DS_READ2ST64_B32_vi   : DS_Real_vi<0x38, DS_READ2ST64_B32>;
823def DS_READ_I8_vi         : DS_Real_vi<0x39, DS_READ_I8>;
824def DS_READ_U8_vi         : DS_Real_vi<0x3a, DS_READ_U8>;
825def DS_READ_I16_vi        : DS_Real_vi<0x3b, DS_READ_I16>;
826def DS_READ_U16_vi        : DS_Real_vi<0x3c, DS_READ_U16>;
827def DS_SWIZZLE_B32_vi     : DS_Real_vi<0x3d, DS_SWIZZLE_B32>;
828def DS_PERMUTE_B32_vi     : DS_Real_vi<0x3e, DS_PERMUTE_B32>;
829def DS_BPERMUTE_B32_vi    : DS_Real_vi<0x3f, DS_BPERMUTE_B32>;
830
831def DS_ADD_U64_vi         : DS_Real_vi<0x40, DS_ADD_U64>;
832def DS_SUB_U64_vi         : DS_Real_vi<0x41, DS_SUB_U64>;
833def DS_RSUB_U64_vi        : DS_Real_vi<0x42, DS_RSUB_U64>;
834def DS_INC_U64_vi         : DS_Real_vi<0x43, DS_INC_U64>;
835def DS_DEC_U64_vi         : DS_Real_vi<0x44, DS_DEC_U64>;
836def DS_MIN_I64_vi         : DS_Real_vi<0x45, DS_MIN_I64>;
837def DS_MAX_I64_vi         : DS_Real_vi<0x46, DS_MAX_I64>;
838def DS_MIN_U64_vi         : DS_Real_vi<0x47, DS_MIN_U64>;
839def DS_MAX_U64_vi         : DS_Real_vi<0x48, DS_MAX_U64>;
840def DS_AND_B64_vi         : DS_Real_vi<0x49, DS_AND_B64>;
841def DS_OR_B64_vi          : DS_Real_vi<0x4a, DS_OR_B64>;
842def DS_XOR_B64_vi         : DS_Real_vi<0x4b, DS_XOR_B64>;
843def DS_MSKOR_B64_vi       : DS_Real_vi<0x4c, DS_MSKOR_B64>;
844def DS_WRITE_B64_vi       : DS_Real_vi<0x4d, DS_WRITE_B64>;
845def DS_WRITE2_B64_vi      : DS_Real_vi<0x4E, DS_WRITE2_B64>;
846def DS_WRITE2ST64_B64_vi  : DS_Real_vi<0x4f, DS_WRITE2ST64_B64>;
847def DS_CMPST_B64_vi       : DS_Real_vi<0x50, DS_CMPST_B64>;
848def DS_CMPST_F64_vi       : DS_Real_vi<0x51, DS_CMPST_F64>;
849def DS_MIN_F64_vi         : DS_Real_vi<0x52, DS_MIN_F64>;
850def DS_MAX_F64_vi         : DS_Real_vi<0x53, DS_MAX_F64>;
851
852def DS_ADD_RTN_U64_vi     : DS_Real_vi<0x60, DS_ADD_RTN_U64>;
853def DS_SUB_RTN_U64_vi     : DS_Real_vi<0x61, DS_SUB_RTN_U64>;
854def DS_RSUB_RTN_U64_vi    : DS_Real_vi<0x62, DS_RSUB_RTN_U64>;
855def DS_INC_RTN_U64_vi     : DS_Real_vi<0x63, DS_INC_RTN_U64>;
856def DS_DEC_RTN_U64_vi     : DS_Real_vi<0x64, DS_DEC_RTN_U64>;
857def DS_MIN_RTN_I64_vi     : DS_Real_vi<0x65, DS_MIN_RTN_I64>;
858def DS_MAX_RTN_I64_vi     : DS_Real_vi<0x66, DS_MAX_RTN_I64>;
859def DS_MIN_RTN_U64_vi     : DS_Real_vi<0x67, DS_MIN_RTN_U64>;
860def DS_MAX_RTN_U64_vi     : DS_Real_vi<0x68, DS_MAX_RTN_U64>;
861def DS_AND_RTN_B64_vi     : DS_Real_vi<0x69, DS_AND_RTN_B64>;
862def DS_OR_RTN_B64_vi      : DS_Real_vi<0x6a, DS_OR_RTN_B64>;
863def DS_XOR_RTN_B64_vi     : DS_Real_vi<0x6b, DS_XOR_RTN_B64>;
864def DS_MSKOR_RTN_B64_vi   : DS_Real_vi<0x6c, DS_MSKOR_RTN_B64>;
865def DS_WRXCHG_RTN_B64_vi  : DS_Real_vi<0x6d, DS_WRXCHG_RTN_B64>;
866def DS_WRXCHG2_RTN_B64_vi : DS_Real_vi<0x6e, DS_WRXCHG2_RTN_B64>;
867def DS_WRXCHG2ST64_RTN_B64_vi : DS_Real_vi<0x6f, DS_WRXCHG2ST64_RTN_B64>;
868def DS_CMPST_RTN_B64_vi   : DS_Real_vi<0x70, DS_CMPST_RTN_B64>;
869def DS_CMPST_RTN_F64_vi   : DS_Real_vi<0x71, DS_CMPST_RTN_F64>;
870def DS_MIN_RTN_F64_vi     : DS_Real_vi<0x72, DS_MIN_RTN_F64>;
871def DS_MAX_RTN_F64_vi     : DS_Real_vi<0x73, DS_MAX_RTN_F64>;
872
873def DS_READ_B64_vi        : DS_Real_vi<0x76, DS_READ_B64>;
874def DS_READ2_B64_vi       : DS_Real_vi<0x77, DS_READ2_B64>;
875def DS_READ2ST64_B64_vi   : DS_Real_vi<0x78, DS_READ2ST64_B64>;
876
877def DS_ADD_SRC2_U32_vi    : DS_Real_vi<0x80, DS_ADD_SRC2_U32>;
878def DS_SUB_SRC2_U32_vi    : DS_Real_vi<0x81, DS_SUB_SRC2_U32>;
879def DS_RSUB_SRC2_U32_vi   : DS_Real_vi<0x82, DS_RSUB_SRC2_U32>;
880def DS_INC_SRC2_U32_vi    : DS_Real_vi<0x83, DS_INC_SRC2_U32>;
881def DS_DEC_SRC2_U32_vi    : DS_Real_vi<0x84, DS_DEC_SRC2_U32>;
882def DS_MIN_SRC2_I32_vi    : DS_Real_vi<0x85, DS_MIN_SRC2_I32>;
883def DS_MAX_SRC2_I32_vi    : DS_Real_vi<0x86, DS_MAX_SRC2_I32>;
884def DS_MIN_SRC2_U32_vi    : DS_Real_vi<0x87, DS_MIN_SRC2_U32>;
885def DS_MAX_SRC2_U32_vi    : DS_Real_vi<0x88, DS_MAX_SRC2_U32>;
886def DS_AND_SRC2_B32_vi    : DS_Real_vi<0x89, DS_AND_SRC2_B32>;
887def DS_OR_SRC2_B32_vi     : DS_Real_vi<0x8a, DS_OR_SRC2_B32>;
888def DS_XOR_SRC2_B32_vi    : DS_Real_vi<0x8b, DS_XOR_SRC2_B32>;
889def DS_WRITE_SRC2_B32_vi  : DS_Real_vi<0x8d, DS_WRITE_SRC2_B32>;
890def DS_MIN_SRC2_F32_vi    : DS_Real_vi<0x92, DS_MIN_SRC2_F32>;
891def DS_MAX_SRC2_F32_vi    : DS_Real_vi<0x93, DS_MAX_SRC2_F32>;
892def DS_ADD_SRC2_U64_vi    : DS_Real_vi<0xc0, DS_ADD_SRC2_U64>;
893def DS_SUB_SRC2_U64_vi    : DS_Real_vi<0xc1, DS_SUB_SRC2_U64>;
894def DS_RSUB_SRC2_U64_vi   : DS_Real_vi<0xc2, DS_RSUB_SRC2_U64>;
895def DS_INC_SRC2_U64_vi    : DS_Real_vi<0xc3, DS_INC_SRC2_U64>;
896def DS_DEC_SRC2_U64_vi    : DS_Real_vi<0xc4, DS_DEC_SRC2_U64>;
897def DS_MIN_SRC2_I64_vi    : DS_Real_vi<0xc5, DS_MIN_SRC2_I64>;
898def DS_MAX_SRC2_I64_vi    : DS_Real_vi<0xc6, DS_MAX_SRC2_I64>;
899def DS_MIN_SRC2_U64_vi    : DS_Real_vi<0xc7, DS_MIN_SRC2_U64>;
900def DS_MAX_SRC2_U64_vi    : DS_Real_vi<0xc8, DS_MAX_SRC2_U64>;
901def DS_AND_SRC2_B64_vi    : DS_Real_vi<0xc9, DS_AND_SRC2_B64>;
902def DS_OR_SRC2_B64_vi     : DS_Real_vi<0xca, DS_OR_SRC2_B64>;
903def DS_XOR_SRC2_B64_vi    : DS_Real_vi<0xcb, DS_XOR_SRC2_B64>;
904def DS_WRITE_SRC2_B64_vi  : DS_Real_vi<0xcd, DS_WRITE_SRC2_B64>;
905def DS_MIN_SRC2_F64_vi    : DS_Real_vi<0xd2, DS_MIN_SRC2_F64>;
906def DS_MAX_SRC2_F64_vi    : DS_Real_vi<0xd3, DS_MAX_SRC2_F64>;
907