1 //===-- AMDGPUTargetTransformInfo.h - AMDGPU specific TTI -------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file a TargetTransformInfo::Concept conforming object specific to the
11 /// AMDGPU target machine. It uses the target's detailed information to
12 /// provide more precise answers to certain TTI queries, while letting the
13 /// target independent and default TTI implementations handle the rest.
14 ///
15 //===----------------------------------------------------------------------===//
16 
17 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETTRANSFORMINFO_H
18 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETTRANSFORMINFO_H
19 
20 #include "AMDGPU.h"
21 #include "AMDGPUTargetMachine.h"
22 #include "llvm/Analysis/TargetTransformInfo.h"
23 #include "llvm/CodeGen/BasicTTIImpl.h"
24 
25 namespace llvm {
26 class AMDGPUTargetLowering;
27 
28 class AMDGPUTTIImpl final : public BasicTTIImplBase<AMDGPUTTIImpl> {
29   typedef BasicTTIImplBase<AMDGPUTTIImpl> BaseT;
30   typedef TargetTransformInfo TTI;
31   friend BaseT;
32 
33   const AMDGPUSubtarget *ST;
34   const AMDGPUTargetLowering *TLI;
35 
36   const AMDGPUSubtarget *getST() const { return ST; }
37   const AMDGPUTargetLowering *getTLI() const { return TLI; }
38 
39 
40   static inline int getFullRateInstrCost() {
41     return TargetTransformInfo::TCC_Basic;
42   }
43 
44   static inline int getHalfRateInstrCost() {
45     return 2 * TargetTransformInfo::TCC_Basic;
46   }
47 
48   // TODO: The size is usually 8 bytes, but takes 4x as many cycles. Maybe
49   // should be 2 or 4.
50   static inline int getQuarterRateInstrCost() {
51     return 3 * TargetTransformInfo::TCC_Basic;
52   }
53 
54    // On some parts, normal fp64 operations are half rate, and others
55    // quarter. This also applies to some integer operations.
56   inline int get64BitInstrCost() const {
57     return ST->hasHalfRate64Ops() ?
58       getHalfRateInstrCost() : getQuarterRateInstrCost();
59   }
60 
61 public:
62   explicit AMDGPUTTIImpl(const AMDGPUTargetMachine *TM, const DataLayout &DL)
63       : BaseT(TM, DL), ST(TM->getSubtargetImpl()),
64         TLI(ST->getTargetLowering()) {}
65 
66   // Provide value semantics. MSVC requires that we spell all of these out.
67   AMDGPUTTIImpl(const AMDGPUTTIImpl &Arg)
68       : BaseT(static_cast<const BaseT &>(Arg)), ST(Arg.ST), TLI(Arg.TLI) {}
69   AMDGPUTTIImpl(AMDGPUTTIImpl &&Arg)
70       : BaseT(std::move(static_cast<BaseT &>(Arg))), ST(std::move(Arg.ST)),
71         TLI(std::move(Arg.TLI)) {}
72 
73   bool hasBranchDivergence() { return true; }
74 
75   void getUnrollingPreferences(Loop *L, TTI::UnrollingPreferences &UP);
76 
77   TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth) {
78     assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
79     return ST->hasBCNT(TyWidth) ? TTI::PSK_FastHardware : TTI::PSK_Software;
80   }
81 
82   unsigned getNumberOfRegisters(bool Vector);
83   unsigned getRegisterBitWidth(bool Vector);
84   unsigned getMaxInterleaveFactor(unsigned VF);
85 
86   int getArithmeticInstrCost(
87     unsigned Opcode, Type *Ty,
88     TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue,
89     TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue,
90     TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None,
91     TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None);
92 
93   unsigned getCFInstrCost(unsigned Opcode);
94 
95   int getVectorInstrCost(unsigned Opcode, Type *ValTy, unsigned Index);
96   bool isSourceOfDivergence(const Value *V) const;
97 };
98 
99 } // end namespace llvm
100 
101 #endif
102